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| author | Daisuke Nojiri <dnojiri@chromium.org> | 2019-04-30 02:16:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-05-04 03:17:54 -0700 |
| commit | b26d8bdc5ef3ed670c5f797f0b412696cb9ac16a (patch) | |
| tree | bc5d63c984ca5bb87c97db18e17e5819f1a11634 /chip/stm32/registers.h | |
| parent | fd12ea66de5374065983a1ba1a8f698e300020b6 (diff) | |
| download | chrome-ec-b26d8bdc5ef3ed670c5f797f0b412696cb9ac16a.tar.gz | |
stm32f0: Set ADC sampling rate before every read
Currently, the sampling rate is set only once in adc_init. This patch
makes EC set the sampling rate every time ADC is sampled.
This patch also adds STM32_ADC_SMPR_DEFAULT so that zero can be used to
specify the default sampling rate.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/131579158
BRANCH=none
TEST=Verified ADC readings match with externally measured voltage
for LCM_ID, BATT_ID, and USBC_THERM.
TEST=buildall
Change-Id: I73a1352dec907c2a8724e2f3f3d0258a706910a7
Reviewed-on: https://chromium-review.googlesource.com/1589253
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index a6c9636098..23215b26db 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -2266,14 +2266,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ #define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_SMPR_1_5_CY 0x0 -#define STM32_ADC_SMPR_7_5_CY 0x1 -#define STM32_ADC_SMPR_13_5_CY 0x2 -#define STM32_ADC_SMPR_28_5_CY 0x3 -#define STM32_ADC_SMPR_41_5_CY 0x4 -#define STM32_ADC_SMPR_55_5_CY 0x5 -#define STM32_ADC_SMPR_71_5_CY 0x6 -#define STM32_ADC_SMPR_239_5_CY 0x7 +/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ +#define STM32_ADC_SMPR_SMP(s) ((s) - 1) #define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) #define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) #define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) |