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| author | Anton Staaf <robotboy@chromium.org> | 2015-07-28 10:30:44 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-10 17:54:17 +0000 |
| commit | 014d180b1da90a5e23f2ebd4df3d00457bc5fb28 (patch) | |
| tree | e6ac67ab0e24d86d82e2e93fc811261bddd66568 /chip/stm32/registers.h | |
| parent | 77f68f204f2e27f7ed7e80bcdd1e36280bbcff83 (diff) | |
| download | chrome-ec-014d180b1da90a5e23f2ebd4df3d00457bc5fb28.tar.gz | |
USART: Split RX driver between L and F families
The USART peripheral in the L and F families is different enough to need
different receive drivers. In particular, the L family USART perihperal
has no way of disabling the overflow error bit. So for that family we
check and clear the bit, and keep a count of overflows.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Iea26c242d5177afd552a3bd4d6ab1a9c7a65f90e
Reviewed-on: https://chromium-review.googlesource.com/288978
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index f9f27f25f5..617abd98f9 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -189,16 +189,19 @@ #define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) #define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) #define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF (1 << 3) #define STM32_USART_ICR_TCCF (1 << 6) #define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) #define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) /* register alias */ #define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE (1 << 3) #define STM32_USART_SR_RXNE (1 << 5) #define STM32_USART_SR_TC (1 << 6) #define STM32_USART_SR_TXE (1 << 7) #else /* !CHIP_FAMILY_STM32F0 */ #define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_SR_ORE (1 << 3) #define STM32_USART_SR_RXNE (1 << 5) #define STM32_USART_SR_TC (1 << 6) #define STM32_USART_SR_TXE (1 << 7) |