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| author | Rong Chang <rongchang@chromium.org> | 2015-04-24 06:56:33 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-20 09:18:59 +0000 |
| commit | 6791ac717438ea7d53c640cb3c0f6da6f1114a59 (patch) | |
| tree | 27d556b49776d6c521a395d19882dd06f4747d07 /chip/stm32/registers.h | |
| parent | 3402e760a95e4c632d11f25a392bde488e3fa69d (diff) | |
| download | chrome-ec-6791ac717438ea7d53c640cb3c0f6da6f1114a59.tar.gz | |
stm32f0: i2c: Add i2c_xfer repeated start support
stm32f051 I2C slave does not clear transmit interrupt status (TXIS) on
receiving NACK. That fails to support I2C master repeated-start read.
This change moves slave transmit from host command thread's TXIS loop to
interrupt event loop. And enables NACK interrupt to handle master
restart. On the I2C master side, this CL adds i2c_xfer flags.
With this CL, stm32f0 EC can talk to stm32f051 PD through host commands.
BRANCH=None
BUG=None
TEST=make BOARD=<board with stm32f0 EC and PD>
Verify EC console command "pdcmd 1 0 0x10 0x20 0x30 0x40"
Change-Id: I771b4fb3de3732f18da90ea5e27a79afb09689b0
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267041
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 261e9fb26c..52c74ef64f 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -484,11 +484,13 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_I2C_ISR_DIR (1 << 16) #define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) #define STM32_I2C_ICR_ADDRCF (1 << 3) +#define STM32_I2C_ICR_NACKCF (1 << 4) #define STM32_I2C_ICR_STOPCF (1 << 5) #define STM32_I2C_ICR_BERRCF (1 << 8) #define STM32_I2C_ICR_ARLOCF (1 << 9) #define STM32_I2C_ICR_OVRCF (1 << 10) #define STM32_I2C_ICR_TIMEOUTCF (1 << 12) +#define STM32_I2C_ICR_ALL 0x3F38 #define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) #define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) #define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) |