diff options
| author | Sam Hurst <shurst@google.com> | 2017-01-25 14:14:09 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-26 18:43:53 -0800 |
| commit | 90383450f6e12b409872c63875d33e58ab948906 (patch) | |
| tree | 012b0be5101317db4ac852222d843fb4081baa34 /chip/stm32/registers.h | |
| parent | 17515de32c7dffc5a9afd7e365a4dd31b3d3074a (diff) | |
| download | chrome-ec-90383450f6e12b409872c63875d33e58ab948906.tar.gz | |
usb: activate CRS on STM32F0
Enable the Clock Recovery Subsystem to automatically adjust the internal
HSI48 clock for proper USB operation on the STM32F0.
BUG=chrome-os-partner:34160
TEST=Manual testing on STM32F072B-DISCOVERY
Plugged in board and verified that device was detected with dmesg.
[1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd
[1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f
[1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[1400698.720072] usb 3-10: Product: PDeval-stm32f072
[1400698.720075] usb 3-10: Manufacturer: Google Inc.
BRANCH=none
Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236
Reviewed-on: https://chromium-review.googlesource.com/433059
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/registers.h')
| -rw-r--r-- | chip/stm32/registers.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 9660e86273..472d7595c7 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -846,6 +846,42 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) #elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ + +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ +#define STM32_CRS_CR_SYNCOKIE (1 << 0) +#define STM32_CRS_CR_SYNCWARNIE (1 << 1) +#define STM32_CRS_CR_ERRIE (1 << 2) +#define STM32_CRS_CR_ESYNCIE (1 << 3) +#define STM32_CRS_CR_CEN (1 << 5) +#define STM32_CRS_CR_AUTOTRIMEN (1 << 6) +#define STM32_CRS_CR_SWSYNC (1 << 7) +#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) + +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ +#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) +#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) +#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) +#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) +#define STM32_CRS_CFGR_SYNCPOL (1 << 31) + +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ +#define STM32_CRS_ISR_SYNCOKF (1 << 0) +#define STM32_CRS_ISR_SYNCWARNF (1 << 1) +#define STM32_CRS_ISR_ERRF (1 << 2) +#define STM32_CRS_ISR_ESYNCF (1 << 3) +#define STM32_CRS_ISR_SYNCERR (1 << 8) +#define STM32_CRS_ISR_SYNCMISS (1 << 9) +#define STM32_CRS_ISR_TRIMOVF (1 << 10) +#define STM32_CRS_ISR_FEDIR (1 << 15) +#define STM32_CRS_ISR_FECAP (0xffff << 16) + +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ +#define STM32_CRS_ICR_SYNCOKC (1 << 0) +#define STM32_CRS_ICR_SYNCWARINC (1 << 1) +#define STM32_CRS_ICR_ERRC (1 << 2) +#define STM32_CRS_ICR_ESYNCC (1 << 3) + #define STM32_RCC_BASE 0x40021000 #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) @@ -883,6 +919,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_PB1_TIM14 (1 << 8) /* STM32F0XX and STM32F373 */ #define STM32_RCC_PB1_TIM18 (1 << 9) /* STM32F373 */ #define STM32_RCC_PB1_USB (1 << 23) +#define STM32_RCC_PB1_CRS (1 << 27) #define STM32_SYSCFG_BASE 0x40010000 |