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authorVincent Palatin <vpalatin@chromium.org>2018-05-18 15:47:45 +0200
committerchrome-bot <chrome-bot@chromium.org>2018-06-04 17:23:27 -0700
commiteee7778fcfc5e555d119cff65caa7c045343e356 (patch)
treea5e43bc8e5f85345f204b725a68cbdfcadd9f6a1 /chip/stm32/spi.c
parentb49d5872e9eacae9cee17c9bf011835bc5e3eb45 (diff)
downloadchrome-ec-eee7778fcfc5e555d119cff65caa7c045343e356.tar.gz
stm32: use D-cache on STM32H7
Enable the D-cache on STM32H7. Use the ahb4 RAM region as uncached memory for DMA buffers. Mark the serial, SPI and fingerprint DMA buffers as uncached for proper operations. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=On ZerbleBarn, run fingerprint match. CQ-DEPEND=CL:*616448 Change-Id: Ia33496ebde3508d3427e522cc7ba060829f8f3fd Reviewed-on: https://chromium-review.googlesource.com/1065822 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/spi.c')
-rw-r--r--chip/stm32/spi.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 6cbb1a80e5..2cf604891e 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -15,6 +15,7 @@
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
+#include "link_defs.h"
#include "registers.h"
#include "spi.h"
#include "stm32-dma.h"
@@ -111,8 +112,8 @@ static const uint8_t out_preamble[4] = {
* message, including protocol overhead, and must be 32-bit aligned.
*/
static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) +
- EC_SPI_PAST_END_LENGTH] __aligned(4);
-static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4);
+ EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
+static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached;
static uint8_t enabled;
#ifdef CONFIG_SPI_PROTOCOL_V2
static struct host_cmd_handler_args args;