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authorAlexandru M Stan <amstan@chromium.org>2014-08-13 13:42:07 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-08-14 02:34:07 +0000
commitaa3ca9bc536880a17963bbccba1ecf8489e7203b (patch)
treed646810d82c9822d458804e0850c1af22fb60bb0 /chip/stm32/spi.c
parentcb7468744d8292590ddc4fb0a0b6ed7752b1490a (diff)
downloadchrome-ec-aa3ca9bc536880a17963bbccba1ecf8489e7203b.tar.gz
STM32F0 SPI Fixes: 4x Dummy Bytes
Seems like STM32_SPI_CR2_FRXTH from 5d208b99(STM32F0 SPI Fixes) was not enough to "disable" RX FIFO from the F0 series. There were still a few bytes stuck in the FIFO just after a command with a long sequence of 00 bytes. This increases the dummy bytes read just before a DMA transfer to 4(size of the FIFO). BUG=none BRANCH=none TEST=Veyron with the new EC should survive the AP booting. ectool version will work right away after boot. This change should not affect other STM32 chips because reading dummy bytes from an empty register is essentially a NOP. Change-Id: I812208622a75ecce82433eb6c12595fee3c1428b Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/212297 Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/spi.c')
-rw-r--r--chip/stm32/spi.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index f784d94e31..3129343e85 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -255,10 +255,14 @@ static void setup_for_transaction(void)
dma_disable(STM32_DMAC_SPI1_TX);
/*
- * Read a byte in case there is one pending; this prevents the receive
- * DMA from getting that byte right when we start it
+ * Read dummy bytes in case there are some pending; this prevents the
+ * receive DMA from getting that byte right when we start it. 4 Bytes
+ * makes sure the RX FIFO on the F0 is empty as well.
*/
dummy = spi->dr;
+ dummy = spi->dr;
+ dummy = spi->dr;
+ dummy = spi->dr;
/* Start DMA */
dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg);