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| author | Gwendal Grignou <gwendal@chromium.org> | 2015-07-25 02:49:00 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-30 19:58:09 +0000 |
| commit | ff550b0e1abfc97a8531eed5515c75e0f37deba3 (patch) | |
| tree | 9a9148a436f719437996d4703e2198942b9b5b3d /chip/stm32/spi_master.c | |
| parent | a3a5c90b54670ddc865defc16757f1fef78ca322 (diff) | |
| download | chrome-ec-ff550b0e1abfc97a8531eed5515c75e0f37deba3.tar.gz | |
stm32: Enable 3rd SPI interface
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Diffstat (limited to 'chip/stm32/spi_master.c')
| -rw-r--r-- | chip/stm32/spi_master.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c index 858fede3f0..26d279f19c 100644 --- a/chip/stm32/spi_master.c +++ b/chip/stm32/spi_master.c @@ -17,6 +17,9 @@ /* The second (and third if available) SPI port are used as master */ static stm32_spi_regs_t *SPI_REGS[] = { STM32_SPI2_REGS, +#ifdef CHIP_VARIANT_STM32F373 + STM32_SPI3_REGS, +#endif }; #define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC) @@ -27,6 +30,12 @@ static const struct dma_option dma_tx_option[] = { STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, +#ifdef CHIP_VARIANT_STM32F373 + { + STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT + }, +#endif }; static const struct dma_option dma_rx_option[] = { @@ -34,6 +43,12 @@ static const struct dma_option dma_rx_option[] = { STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, +#ifdef CHIP_VARIANT_STM32F373 + { + STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT + }, +#endif }; static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; |