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| author | Vic Yang <victoryang@chromium.org> | 2014-10-09 15:19:22 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-15 23:55:55 +0000 |
| commit | 82915c25029c0bc2c018cfc080d913255ed82aac (patch) | |
| tree | 1da32cff8e9e01142b63960fd454ff2b1832278a /chip/stm32/system.c | |
| parent | 5ff320f66e990a5efe8270f6125ed7c55699d50c (diff) | |
| download | chrome-ec-82915c25029c0bc2c018cfc080d913255ed82aac.tar.gz | |
Write protect support for STM32F0
On STM32F0, we cannot work around the hard fault triggered when trying
to protect the whole flash. Therefore, we need to go with the
ALL_AT_BOOT approach. When write protect is enabled, instead of setting
ALL_NOW flag to immediately lock down the entire flash, we need to set
ALL_AT_BOOT and then reboot to have the protection take effect.
BUG=chrome-os-partner:32745
TEST=Along with the next CL. On Ryu:
1. Enable HW WP. Check the output of 'ectool flashprotect' and see
correct flags.
2. 'flashrom -p ec --wp-range 0 0x10000'. Check RO_AT_BOOT is set.
3. Reboot EC and check RO_NOW is enabled.
4. Boot the system and check ALL_NOW is set.
5. Update BIOS and reboot. Check software sync updates EC-RW.
6. 'flashrom -p ec --wp-disable' and check it fails.
7. Disable HW WP and reboot EC. Check RO_NOW and ALL_NOW are cleared.
8. 'flashrom -p ec --wp-disable' and check RO_AT_BOOT is cleared.
TEST=Enable/disable WP on Spring. Check RO_AT_BOOT/ALL_NOW can be set
properly.
BRANCH=samus
Change-Id: I1c7c4f98f2535f1c8a1c7daaa88d47412d015977
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222622
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/system.c')
| -rw-r--r-- | chip/stm32/system.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index fa7b199325..52b200ea11 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -231,11 +231,21 @@ void system_reset(int flags) /* Fall through to watchdog if that fails */ #endif +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) + /* + * On some chips, a reboot doesn't always reload the option + * bytes, and we need to explicitly request for a reload. + * The reload request triggers a chip reset, so let's just + * use this for hard reset. + */ + STM32_FLASH_CR |= STM32_FLASH_CR_OBL_LAUNCH; +#else /* Ask the watchdog to trigger a hard reboot */ STM32_IWDG_KR = 0x5555; STM32_IWDG_RLR = 0x1; STM32_IWDG_KR = 0xcccc; - /* wait for the watchdog */ +#endif + /* wait for the chip to reboot */ while (1) ; } else { |