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| author | Tom Hughes <tomhughes@chromium.org> | 2019-07-08 17:49:11 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-07-10 01:06:56 +0000 |
| commit | 20ab5ee3c8a97e6bea27a6db550f9ab3c7df89a7 (patch) | |
| tree | f3ed555624166ff5984212ae2823a986c6692a3b /chip/stm32/system.c | |
| parent | 15ad0fd2427e81b8cd2aa378163ede227ecf301b (diff) | |
| download | chrome-ec-20ab5ee3c8a97e6bea27a6db550f9ab3c7df89a7.tar.gz | |
stm32: Make sure watchdog is enabled when using it to reset
On hatch (using hatch_fp), the watchdog appears to never fire when
issuing the following commands:
ectool --name=cros_fp flashprotect enable
ectool --name=cros_fp reboot_ec
Adding the explicit enable of the watchdog here fixes that.
BRANCH=none
BUG=b:137045370
TEST=On hatch:
ectool --name=cros_fp flashprotect enable
ectool --name=cros_fp reboot_ec
Change-Id: Ib42b67a2c88a5c11e3064523d74c9ded51f71379
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692078
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/stm32/system.c')
| -rw-r--r-- | chip/stm32/system.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index c81406bdc2..d5884375c9 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -417,6 +417,36 @@ void system_reset(int flags) STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH; #else + /* + * RM0433 Rev 6 + * Section 44.3.3 + * https://www.st.com/resource/en/reference_manual/dm00314099.pdf#page=1898 + * + * When the window option is not used, the IWDG can be + * configured as follows: + * + * 1. Enable the IWDG by writing 0x0000 CCCC in the Key + * register (IWDG_KR). + * 2. Enable register access by writing 0x0000 5555 in the Key + * register (IWDG_KR). + * 3. Write the prescaler by programming the Prescaler register + * (IWDG_PR) from 0 to 7. + * 4. Write the Reload register (IWDG_RLR). + * 5. Wait for the registers to be updated + * (IWDG_SR = 0x0000 0000). + * 6. Refresh the counter value with IWDG_RLR + * (IWDG_KR = 0x0000 AAAA) + */ + + /* + * Enable IWDG, which shouldn't be necessary since the IWDG + * only needs to be started once, but STM32F412 hangs unless + * this is added. + * + * See http://b/137045370. + */ + STM32_IWDG_KR = STM32_IWDG_KR_START; + /* Ask the watchdog to trigger a hard reboot */ STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; STM32_IWDG_RLR = 0x1; |