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| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-07-12 10:23:17 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-13 02:22:12 -0700 |
| commit | 49f2ca508e4ae588c08da523c4832fd9f778875d (patch) | |
| tree | 49d3e0a88487a35d4c8af3b1c9bf66a945d302ac /chip/stm32/system.c | |
| parent | 7e972ab9860d594c0db9d4c2df1742a96f64bc67 (diff) | |
| download | chrome-ec-49f2ca508e4ae588c08da523c4832fd9f778875d.tar.gz | |
stm32/system: Fix watchdog-initiated reset
The Reference Manuals for STM32H7 and STM32F4 makes it clear that,
when updating the watchog reload value, one needs to wait until
IWDG_SR bit RVU is reset before reloading the watchdog.
(the code in question is only used on STM32H7 and STM32F4, as other
variants use OBL_LAUNCH to reset themselves, so I didn't check
the other RMs).
This probably has not been seen before, as, normally, we use a 1s
watchdog timeout, so the EC would reset anyway after a second
(since it is stuck in the while loop below).
On meowth_fp, however, we use a 10 seconds watchdog, and the EC
takes too _long_ time to reboot, which breaks things like flashrom.
BRANCH=none
BUG=b:111144409
TEST=On nocturne_fp, run:
for i in `seq 1 1000`; do echo $i; \
./ectool --name=cros_fp reboot_ec cold; sleep 1; done
No watchdog warning, no error.
Change-Id: I110fa9873ed974bfafce23389866aac8cabb662a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1134631
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/system.c')
| -rw-r--r-- | chip/stm32/system.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index ea4309c965..a03550d7f9 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -388,6 +388,9 @@ void system_reset(int flags) /* Ask the watchdog to trigger a hard reboot */ STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; STM32_IWDG_RLR = 0x1; + /* Wait for value to be reloaded. */ + while (STM32_IWDG_SR & STM32_IWDG_SR_RVU) + ; STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; #endif /* wait for the chip to reboot */ |