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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-04-27 08:15:57 +0200 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-04 10:09:42 -0700 |
| commit | edbfb3a43b6c4e1dd28f6d00a59896cae198f68b (patch) | |
| tree | e2fe1d6f4e5da6b0fc1b96853ed3a4819959d982 /chip/stm32/system.c | |
| parent | a6c9a3cd2194d555b926d4a0789827b5dd341b9d (diff) | |
| download | chrome-ec-edbfb3a43b6c4e1dd28f6d00a59896cae198f68b.tar.gz | |
cortex-m: add D-cache support
Add support to enable the architectural D-cache on ARMv7-M CPU
supporting it.
Update the MPU code in order to be able to declare an 'uncached' RAM
region (e.g. to store the DMA buffer).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78535052, b:75068419
TEST=with the following CL, on ZerbleBarn, boot and capture a finger
image.
Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285
Reviewed-on: https://chromium-review.googlesource.com/1032776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/system.c')
| -rw-r--r-- | chip/stm32/system.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index b77f0e8457..ea4309c965 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -205,10 +205,6 @@ void chip_pre_init(void) uint32_t apb1fz_reg = 0; uint32_t apb2fz_reg = 0; -#ifdef CONFIG_ARMV7M_CACHE - cpu_enable_icache(); -#endif - #if defined(CHIP_FAMILY_STM32F0) apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | |