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authorScott Collyer <scollyer@google.com>2020-06-17 20:22:56 -0700
committerCommit Bot <commit-bot@chromium.org>2021-03-04 21:18:11 +0000
commit22c4439064728d0d83e708724c3f3da5fd5e65b3 (patch)
tree38c8471d10351e36e0be7238d315412017c01297 /chip/stm32/system.c
parent5906ecf9d006259ed51afddc3ada0469d08253a7 (diff)
downloadchrome-ec-22c4439064728d0d83e708724c3f3da5fd5e65b3.tar.gz
stm32g4: Add USB endpoint support
This CL enables USB-EP for the STM32G4 family. It also fixes backup domain register access issues which are required for fw updates via USB. BUG=b:148493929 BRANCH=None TEST=Verified on quiche that STM32G4 enumerates as an USB endpoint and can be used successfully with fwupd. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I75e6b6e70e9ca2589ace76f0aa0facadd9e94142 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2268139 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/stm32/system.c')
-rw-r--r--chip/stm32/system.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
index 0304c7b3be..42525deb48 100644
--- a/chip/stm32/system.c
+++ b/chip/stm32/system.c
@@ -280,6 +280,13 @@ void system_pre_init(void)
/* Wait for LSI to be ready */
while (!(STM32_RCC_CSR & BIT(1)))
;
+
+#if defined(CHIP_FAMILY_STM32G4)
+ /* Make sure PWR clock is enabled */
+ STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
+ /* Enable access to backup domain registers */
+ STM32_PWR_CR1 |= STM32_PWR_CR1_DBP;
+#endif
/* re-configure RTC if needed */
#ifdef CHIP_FAMILY_STM32L
if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
@@ -399,7 +406,7 @@ void system_reset(int flags)
* use this for hard reset.
*/
STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#elif defined(CHIP_FAMILY_STM32L4)
+#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4)
STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;