diff options
| author | Bossen WU <bossen.wu@stmicro.corp-partner.google.com> | 2021-05-18 17:21:56 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-30 08:36:48 +0000 |
| commit | 59b286058cf184e1dfc8b8332aa8adc811d8221d (patch) | |
| tree | caa7a17d679e52b6ed81de8eca011a7baccf7beb /chip/stm32/system.c | |
| parent | 55f7cce1dcc9441979426fbe4226b3308a5df60e (diff) | |
| download | chrome-ec-59b286058cf184e1dfc8b8332aa8adc811d8221d.tar.gz | |
stm32: add stm32l431 ec in chip/stm32 : system / clock / timer
stm32l431 related driver: system / clock / timer.
The stm32l476g-eval is the only board which would be impacted.
BRANCH=main
BUG=b:188117811
TEST=make buildall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'chip/stm32/system.c')
| -rw-r--r-- | chip/stm32/system.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 1f5f9c9108..8d63ba8567 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -168,11 +168,20 @@ void chip_pre_init(void) STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32L4) + +#ifdef CHIP_VARIANT_STM32L431X + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = + STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16; +#else apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; +#endif #elif defined(CHIP_FAMILY_STM32L) apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | @@ -254,14 +263,21 @@ void system_pre_init(void) /* enable clock on Power module */ #ifndef CHIP_FAMILY_STM32H7 +#ifdef CHIP_FAMILY_STM32L4 + STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; +#else STM32_RCC_APB1ENR |= STM32_RCC_PWREN; #endif +#endif #if defined(CHIP_FAMILY_STM32F4) /* enable backup registers */ STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN; #elif defined(CHIP_FAMILY_STM32H7) /* enable backup registers */ STM32_RCC_AHB4ENR |= BIT(28); +#elif defined(CHIP_FAMILY_STM32L4) + /* enable RTC APB clock */ + STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN; #else /* enable backup registers */ STM32_RCC_APB1ENR |= BIT(27); |