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| author | Jes B. Klinke <jbk@chromium.org> | 2021-08-10 10:03:18 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-25 17:27:51 +0000 |
| commit | 7dddeb52f1f4e0d44b99424a7b8c69b38f48b996 (patch) | |
| tree | e327b63228551177aaa3035e5a78297427211a48 /chip/stm32/system.c | |
| parent | 6fc57405b6f9d38edf62824cd2d2fdae1f6e5bbf (diff) | |
| download | chrome-ec-7dddeb52f1f4e0d44b99424a7b8c69b38f48b996.tar.gz | |
chip/stm32: Add initial support for STM32L5xx series
Introduce L5xx mostly as copy of L4xx, though registers-stm32l5.c is
extensively modified.
BUG=b:192262089
TEST=Compile and upload board/hyperdebug to Nucleo board
BRANCH=none
Signed-off-by: Jes B. Klinke <jbk@opentitan.org>
Change-Id: Iccc7b05e4f2dfa732559b8099cf856882401e31c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086362
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Diffstat (limited to 'chip/stm32/system.c')
| -rw-r--r-- | chip/stm32/system.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 66158991d2..03e9a74ac4 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -87,12 +87,16 @@ static void check_reset_cause(void) { uint32_t flags = chip_read_reset_flags(); uint32_t raw_cause = STM32_RCC_RESET_CAUSE; +#ifdef STM32_PWR_RESET_CAUSE uint32_t pwr_status = STM32_PWR_RESET_CAUSE; +#endif /* Clear the hardware reset cause by setting the RMVF bit */ STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF; +#ifdef STM32_PWR_RESET_CAUSE /* Clear SBF in PWR_CSR */ STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR; +#endif /* Clear saved reset flags */ chip_save_reset_flags(0); @@ -114,9 +118,11 @@ static void check_reset_cause(void) if (raw_cause & RESET_CAUSE_PIN) flags |= EC_RESET_FLAG_RESET_PIN; +#ifdef STM32_PWR_RESET_CAUSE if (pwr_status & RESET_CAUSE_SBF) /* Hibernated and subsequently awakened */ flags |= EC_RESET_FLAG_HIBERNATE; +#endif if (!flags && (raw_cause & RESET_CAUSE_OTHER)) flags |= EC_RESET_FLAG_OTHER; @@ -202,11 +208,15 @@ void chip_pre_init(void) #elif defined(CHIP_FAMILY_STM32H7) /* TODO(b/67081508) */ #endif - +#if defined(CHIP_FAMILY_STM32L5) + (void)apb1fz_reg; + (void)apb2fz_reg; +#else if (apb1fz_reg) STM32_DBGMCU_APB1FZ |= apb1fz_reg; if (apb2fz_reg) STM32_DBGMCU_APB2FZ |= apb2fz_reg; +#endif } #ifdef CONFIG_PVD @@ -312,7 +322,8 @@ void system_pre_init(void) STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000; } #elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32F4) || \ + defined(CHIP_FAMILY_STM32L4) || \ + defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) || \ defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4) if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) { /* The RTC settings are bad, we need to reset it */ @@ -604,6 +615,9 @@ int system_is_reboot_warm(void) #elif defined(CHIP_FAMILY_STM32L4) return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == STM32_RCC_AHB2ENR_GPIOMASK); +#elif defined(CHIP_FAMILY_STM32L5) + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) + == STM32_RCC_AHB2ENR_GPIOMASK); #elif defined(CHIP_FAMILY_STM32F4) return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) == gpio_required_clocks()); |