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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-06-07 16:01:51 +0200 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-15 10:56:48 -0700 |
| commit | 13a0b3437eb59a168c4f9c4d1ebc3d217ced3ba5 (patch) | |
| tree | 54ed4c967c27ec40009086a54779ad73bb2a2ab1 /chip/stm32/uart.c | |
| parent | 727c5dad9bad954c4b62144dc1a536dccd281666 (diff) | |
| download | chrome-ec-13a0b3437eb59a168c4f9c4d1ebc3d217ced3ba5.tar.gz | |
stm32: low power idle for STM32H7
Enter STOP mode when possible.
Use LPTIM1 clocked on the 32-Khz LSI as a time keeper / wake-up event
during STOP mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75105319
TEST=On ZerbleBarn, use on-board INAs to measure idle power consumption,
w/o CONFIG_LOW_POWER_IDLE pp3300_h7_ma:14.0
with CONFIG_LOW_POWER_IDLE pp3300_h7_ma:1.84
Change-Id: I1b72a8f6964c7bc6174c07458f307dda57fe71f3
Reviewed-on: https://chromium-review.googlesource.com/1096767
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32/uart.c')
| -rw-r--r-- | chip/stm32/uart.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index 313d2df91c..ce11126746 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -317,7 +317,8 @@ void uart_init(void) /* Configure GPIOs */ gpio_config_module(MODULE_UART, 1); -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \ +|| defined(CHIP_FAMILY_STM32H7) /* * Wake up on start bit detection. WUS can only be written when UE=0, * so clear UE first. |