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author | Bhanu Prakash Maiya <bhanumaiya@google.com> | 2020-04-30 15:26:52 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-06-05 10:06:44 +0000 |
commit | 86aacabcd3c2e496a43d291d9dee61e29edcc2d0 (patch) | |
tree | 5a87bbbee684ce95de718f654b0086abfa87daac /chip/stm32/usart_tx_interrupt.c | |
parent | bc96d7077db615d849d398115af76b7b85f63e01 (diff) | |
download | chrome-ec-86aacabcd3c2e496a43d291d9dee61e29edcc2d0.tar.gz |
Bloonchipper: USART based transport layer for host command
1. USART host command layer in chip/stm32
2. Fix usart implementation in stm32
BUG=b:147849609
BRANCH=none
TEST=1. make BOARD=bloonchipper -j
2. usart request and response works on dragonclaw
Change-Id: Idd89d3e490f23aa528ecaf6510c13d16b405de13
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2190531
Tested-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
Diffstat (limited to 'chip/stm32/usart_tx_interrupt.c')
-rw-r--r-- | chip/stm32/usart_tx_interrupt.c | 55 |
1 files changed, 53 insertions, 2 deletions
diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c index 7c7f1f84de..6a6aaf65f7 100644 --- a/chip/stm32/usart_tx_interrupt.c +++ b/chip/stm32/usart_tx_interrupt.c @@ -10,8 +10,13 @@ #include "common.h" #include "registers.h" #include "system.h" +#include "task.h" +#include "usart_host_command.h" #include "util.h" +typedef size_t (*remove_data_t)(struct usart_config const *config, + uint8_t *dest); + static void usart_tx_init(struct usart_config const *config) { intptr_t base = config->hw->base; @@ -32,7 +37,9 @@ static void usart_written(struct consumer const *consumer, size_t count) STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE; } -static void usart_tx_interrupt_handler(struct usart_config const *config) +static void usart_tx_interrupt_handler_common( + struct usart_config const *config, + remove_data_t remove_data) { intptr_t base = config->hw->base; uint8_t byte; @@ -40,7 +47,7 @@ static void usart_tx_interrupt_handler(struct usart_config const *config) if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE)) return; - if (queue_remove_unit(config->consumer.queue, &byte)) { + if (remove_data(config, &byte)) { STM32_USART_TDR(base) = byte; /* @@ -64,6 +71,30 @@ static void usart_tx_interrupt_handler(struct usart_config const *config) } } +static size_t queue_remove(struct usart_config const *config, uint8_t *dest) +{ + return queue_remove_unit(config->producer.queue, (void *) dest); +} + +static void usart_tx_interrupt_handler(struct usart_config const *config) +{ + usart_tx_interrupt_handler_common(config, &queue_remove); +} + +void usart_tx_start(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + + /* If interrupt is already enabled, nothing to do */ + if (STM32_USART_CR1(base) & STM32_USART_CR1_TXEIE) + return; + + disable_sleep(SLEEP_MASK_UART); + STM32_USART_CR1(base) |= (STM32_USART_CR1_TXEIE); + + task_trigger_irq(config->hw->irq); +} + struct usart_tx const usart_tx_interrupt = { .consumer_ops = { .written = usart_written, @@ -73,3 +104,23 @@ struct usart_tx const usart_tx_interrupt = { .interrupt = usart_tx_interrupt_handler, .info = NULL, }; + +#if defined(CONFIG_USART_HOST_COMMAND) + +static void usart_host_command_tx_interrupt_handler( + struct usart_config const *config) +{ + usart_tx_interrupt_handler_common(config, + &usart_host_command_tx_remove_data); +} + +struct usart_tx const usart_host_command_tx_interrupt = { + .consumer_ops = { + .written = usart_written, + }, + + .init = usart_tx_init, + .interrupt = usart_host_command_tx_interrupt_handler, + .info = NULL, +}; +#endif /* CONFIG_USART_HOST_COMMAND */ |