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| author | Jes B. Klinke <jbk@chromium.org> | 2021-08-10 10:03:18 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-25 17:27:51 +0000 |
| commit | 7dddeb52f1f4e0d44b99424a7b8c69b38f48b996 (patch) | |
| tree | e327b63228551177aaa3035e5a78297427211a48 /chip/stm32/usb.c | |
| parent | 6fc57405b6f9d38edf62824cd2d2fdae1f6e5bbf (diff) | |
| download | chrome-ec-7dddeb52f1f4e0d44b99424a7b8c69b38f48b996.tar.gz | |
chip/stm32: Add initial support for STM32L5xx series
Introduce L5xx mostly as copy of L4xx, though registers-stm32l5.c is
extensively modified.
BUG=b:192262089
TEST=Compile and upload board/hyperdebug to Nucleo board
BRANCH=none
Signed-off-by: Jes B. Klinke <jbk@opentitan.org>
Change-Id: Iccc7b05e4f2dfa732559b8099cf856882401e31c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086362
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Diffstat (limited to 'chip/stm32/usb.c')
| -rw-r--r-- | chip/stm32/usb.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index b3f1189b9d..70acdf6486 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -498,8 +498,13 @@ static void usb_wake_deferred(void) * interface. */ CPRINTF("USB stuck\n"); +#if defined(STM32_RCC_APB1RSTR2_USBFSRST) + STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST; + STM32_RCC_APB1RSTR2 &= STM32_RCC_APB1RSTR2_USBFSRST; +#else STM32_RCC_APB1RSTR |= STM32_RCC_PB1_USB; STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_USB; +#endif usb_init(); } } @@ -673,7 +678,11 @@ DECLARE_IRQ(STM32_IRQ_USB_LP, usb_interrupt, 1); void usb_init(void) { /* Enable USB device clock. */ +#if defined(STM32_RCC_APB1ENR2_USBFSEN) + STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_USBFSEN; +#else STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; +#endif /* we need a proper 48MHz clock */ clock_enable_module(MODULE_USB, 1); @@ -742,14 +751,22 @@ void usb_release(void) clock_enable_module(MODULE_USB, 0); /* disable USB device clock */ +#if defined(STM32_RCC_APB1ENR2_USBFSEN) + STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_USBFSEN; +#else STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; +#endif } /* ensure the host disconnects and reconnects over a sysjump */ DECLARE_HOOK(HOOK_SYSJUMP, usb_release, HOOK_PRIO_DEFAULT); int usb_is_enabled(void) { +#if defined(STM32_RCC_APB1ENR2_USBFSEN) + return (STM32_RCC_APB1ENR2 & STM32_RCC_APB1ENR2_USBFSEN) ? 1 : 0; +#else return (STM32_RCC_APB1ENR & STM32_RCC_PB1_USB) ? 1 : 0; +#endif } void *memcpy_to_usbram(void *dest, const void *src, size_t n) |