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authorNick Sanders <nsanders@chromium.org>2016-08-02 19:35:44 -0700
committerchrome-bot <chrome-bot@chromium.org>2016-09-01 22:56:22 -0700
commita4bfc663a3cd645b43963bb814269efe864f8d1e (patch)
tree185ab7cc413c4b580ea50845a024838aba577732 /chip/stm32/usb_hw.h
parent54f4612764e07e5e3ccd8a4af04ee83a46454612 (diff)
downloadchrome-ec-a4bfc663a3cd645b43963bb814269efe864f8d1e.tar.gz
sweetberry: add dwc usb support
stm32f446 uses a synopsys designware USB block rather than the typical ST one. This change adds driver support for the new block, including usb console support. BUG=chromium:608039 TEST=usb console works BRANCH=None Change-Id: I0e143758ae0b5285f1c94ea2ec5aee159e22e00c Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365448 Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/usb_hw.h')
-rw-r--r--chip/stm32/usb_hw.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h
index b44a33dcac..29bb347e3c 100644
--- a/chip/stm32/usb_hw.h
+++ b/chip/stm32/usb_hw.h
@@ -6,6 +6,11 @@
#ifndef __CROS_EC_USB_HW_H
#define __CROS_EC_USB_HW_H
+#if defined(CHIP_FAMILY_STM32F4)
+#include "usb_dwc_hw.h"
+#else
+
+
/*
* The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads &
* writes are 16-bits wide). The endpoint tables and the data buffers live in
@@ -82,4 +87,5 @@ extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
usb_uint *epo_buf_tx) \
__attribute__ ((alias(STRINGIFY(handler))));
+#endif
#endif /* __CROS_EC_USB_HW_H */