diff options
| author | Vic Yang <victoryang@chromium.org> | 2014-10-17 00:12:10 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-21 00:44:07 +0000 |
| commit | 46f033171171f93bbb6021f1e8c1b6b2adf925cf (patch) | |
| tree | a9d0b9381199a893901642f671c160ad6091df7d /chip/stm32/usb_pd_phy.c | |
| parent | 0e3497762c71e6c4cd7fe6b7f71beb15ff654f6f (diff) | |
| download | chrome-ec-46f033171171f93bbb6021f1e8c1b6b2adf925cf.tar.gz | |
pd: allow selection of Tx timer channel
So far, we always use channel 1 of the Tx timer and the configuration
code is hard coded. We need to support other channels for new Ryu
boards. Let's make this a configurable bit.
BRANCH=samus
BUG=chrome-os-partner:32660
TEST=make buildall
TEST=Plug in Zinger to Ryu and see 20V come up.
Change-Id: Id08d4eb0d6a5721d8a03672484d0892a0714383b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223836
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/usb_pd_phy.c')
| -rw-r--r-- | chip/stm32/usb_pd_phy.c | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index 7fa2007eda..162e613cfb 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -472,6 +472,8 @@ void pd_hw_release(int port) void pd_hw_init(int port) { struct pd_physical *phy = &pd_phy[port]; + uint32_t val; + /* set 40 MHz pin speed on communication pins */ pd_set_pins_speed(port); @@ -511,10 +513,16 @@ void pd_hw_init(int port) /* Auto-reload value : 600000 Khz overflow */ phy->tim_tx->arr = TX_CLOCK_DIV; /* 50% duty cycle on the output */ - phy->tim_tx->ccr[1] = phy->tim_tx->arr / 2; - /* Timer CH1 output configuration */ - phy->tim_tx->ccmr1 = (6 << 4) | (1 << 3); - phy->tim_tx->ccer = 1; + phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2; + /* Timer channel output configuration */ + val = (6 << 4) | (1 << 3); + if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */ + val <<= 8; + if (TIM_TX_CCR_IDX(port) <= 2) + phy->tim_tx->ccmr1 = val; + else + phy->tim_tx->ccmr2 = val; + phy->tim_tx->ccer = 1 << ((TIM_TX_CCR_IDX(port) - 1) * 4); phy->tim_tx->bdtr = 0x8000; /* set prescaler to /1 */ phy->tim_tx->psc = 0; @@ -534,19 +542,19 @@ void pd_hw_init(int port) /* Timeout for message receive */ phy->tim_rx->ccr[2] = (2400000 / 1000) * USB_PD_RX_TMOUT_US / 1000; /* Timer ICx input configuration */ - if (TIM_CCR_IDX(port) == 1) + if (TIM_RX_CCR_IDX(port) == 1) phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0; else /* Unsupported RX timer capture input */ ASSERT(0); - phy->tim_rx->ccer = 0xB << ((TIM_CCR_IDX(port) - 1) * 4); + phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4); /* configure DMA request on CCRx update */ - phy->tim_rx->dier |= 1 << (8 + TIM_CCR_IDX(port)); /* CCxDE */; + phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */; /* set prescaler to /26 (F=1.2Mhz, T=0.8us) */ phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1; /* Reload the pre-scaler and reset the counter (clear CCRx) */ - phy->tim_rx->egr = 0x0001 | (1 << TIM_CCR_IDX(port)); + phy->tim_rx->egr = 0x0001 | (1 << TIM_RX_CCR_IDX(port)); /* clear update event from reloading */ phy->tim_rx->sr = 0; |