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| author | Vic Yang <victoryang@chromium.org> | 2014-10-05 16:29:04 +0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-22 00:30:42 +0000 |
| commit | 00551f7331119b0dbde124c01810daeb9dcdd665 (patch) | |
| tree | 5ae3da00bb3a764e4611a8b824bc71334bb2c93a /chip/stm32/usb_pd_phy.c | |
| parent | fbefbbca1ef380d41478d7616d5b5d4b0b25c4b6 (diff) | |
| download | chrome-ec-00551f7331119b0dbde124c01810daeb9dcdd665.tar.gz | |
Add new build target ryu_p2 for Ryu P2 boards
The new build target ryu_p2 is mostly based on ryu. On ryu_p2, we have a
new EC chip with bigger flash, so make the corresponding changes:
- Pinout changes
- HW Timer: TIM5
- USB PD Tx Timer: TIM3_CH4
- USB PD Rx Timer: TIM2_CH4
- Use UART2 for EC console
- Disable UART Tx DMA as it conflicts with USB PD Tx DMA
- Use 24MHz HSE x2 = 48MHz for SYSCLK
BRANCH=None
BUG=chrome-os-partner:32660
TEST=Sanity check on a new board:
- i2cscan
- PD negotiation
- UART console
- gettime
Change-Id: I4ef6b53a928a2777721e3874032aeb0e6b2b4c92
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221404
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/usb_pd_phy.c')
| -rw-r--r-- | chip/stm32/usb_pd_phy.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index 162e613cfb..784e294fd7 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -544,6 +544,8 @@ void pd_hw_init(int port) /* Timer ICx input configuration */ if (TIM_RX_CCR_IDX(port) == 1) phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0; + else if (TIM_RX_CCR_IDX(port) == 4) + phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8; else /* Unsupported RX timer capture input */ ASSERT(0); |