diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-07-01 13:32:02 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-07-02 09:32:49 -0700 |
| commit | c830c036dcf18b230de81b800ce9e9fd8b3dc19e (patch) | |
| tree | 96ab1da4e8498b82d19ffc5332c72558dee3093c /chip/stm32/watchdog.c | |
| parent | c2a29498dc1af8caafcf3b8371499a92c6797a8d (diff) | |
| download | chrome-ec-c830c036dcf18b230de81b800ce9e9fd8b3dc19e.tar.gz | |
stm32: Clean up watchdog registers
No functional changes, just cleanup.
BUG=chrome-os-partner:20529
BRANCH=none
TEST='waitms 2000' reboots the system with a watchdog reset cause
Change-Id: I8fcee92476a287e6cb81bf9012f29c87d2aca0ba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60680
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Diffstat (limited to 'chip/stm32/watchdog.c')
| -rw-r--r-- | chip/stm32/watchdog.c | 33 |
1 files changed, 17 insertions, 16 deletions
diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c index 6a7c0d3983..aa9a3cd168 100644 --- a/chip/stm32/watchdog.c +++ b/chip/stm32/watchdog.c @@ -15,21 +15,26 @@ #include "util.h" #include "watchdog.h" -/* LSI oscillator frequency is typically 38 kHz - * but might vary from 28 to 56kHz. - * So let's pick 56kHz to ensure we reload - * early enough. +/* + * LSI oscillator frequency is typically 38 kHz, but it may be between 28-56 + * kHz and we don't calibrate it to know. Use 56 kHz so that we pick a counter + * value large enough that we reload before the worst-case watchdog delay + * (fastest LSI clock). */ #define LSI_CLOCK 56000 -/* Prescaler divider = /256 */ +/* + * Use largest prescaler divider = /256. This gives a worst-case watchdog + * clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) = + * 18.7 sec. + */ #define IWDG_PRESCALER 6 -#define IWDG_PRESCALER_DIV (1 << ((IWDG_PRESCALER) + 2)) +#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER) void watchdog_reload(void) { /* Reload the watchdog */ - STM32_IWDG_KR = 0xaaaa; + STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; #ifdef CONFIG_WATCHDOG_HELP hwtimer_reset_watchdog(); @@ -39,22 +44,18 @@ DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); int watchdog_init(void) { - uint32_t watchdog_period; - - /* set the time-out period */ - watchdog_period = WATCHDOG_PERIOD_MS * - (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000; - /* Unlock watchdog registers */ - STM32_IWDG_KR = 0x5555; + STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; /* Set the prescaler between the LSI clock and the watchdog counter */ STM32_IWDG_PR = IWDG_PRESCALER & 7; + /* Set the reload value of the watchdog counter */ - STM32_IWDG_RLR = watchdog_period & 0x7FF ; + STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, WATCHDOG_PERIOD_MS * + (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); /* Start the watchdog (and re-lock registers) */ - STM32_IWDG_KR = 0xcccc; + STM32_IWDG_KR = STM32_IWDG_KR_START; #ifdef CONFIG_WATCHDOG_HELP /* Use a harder timer to warn about an impending watchdog reset */ |