diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2012-05-01 09:10:14 -0700 |
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committer | Vincent Palatin <vpalatin@chromium.org> | 2012-05-01 22:59:51 +0000 |
commit | 539c397fb16460561aa451d121041ed36c13a845 (patch) | |
tree | fd31a40a7e1e373262ef04d392d5742fe584ae83 /chip/stm32/watchdog.c | |
parent | 285fa08d10c2e5fce6e0db6f217a83b5a42e8004 (diff) | |
download | chrome-ec-539c397fb16460561aa451d121041ed36c13a845.tar.gz |
introducing chip variant for stm32 family [1/3]
just rename STM32L to STM32.
Most of the STM32L15x code is common with STM32F1xx.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
Diffstat (limited to 'chip/stm32/watchdog.c')
-rw-r--r-- | chip/stm32/watchdog.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c new file mode 100644 index 0000000000..9a2d76a422 --- /dev/null +++ b/chip/stm32/watchdog.c @@ -0,0 +1,73 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Watchdog driver */ + +#include "board.h" +#include "common.h" +#include "config.h" +#include "registers.h" +#include "gpio.h" +#include "task.h" +#include "timer.h" +#include "util.h" + +/* LSI oscillator frequency is typically 38 kHz + * but might vary from 28 to 56kHz. + * So let's pick 56kHz to ensure we reload + * early enough. + */ +#define LSI_CLOCK 56000 + +/* Prescaler divider = /256 */ +#define IWDG_PRESCALER 6 +#define IWDG_PRESCALER_DIV (1 << ((IWDG_PRESCALER) + 2)) + + +void watchdog_reload(void) +{ + /* Reload the watchdog */ + STM32_IWDG_KR = 0xaaaa; +} + + +int watchdog_init(int period_ms) +{ + uint32_t watchdog_period; + + /* set the time-out period */ + watchdog_period = period_ms * (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000; + + /* Unlock watchdog registers */ + STM32_IWDG_KR = 0x5555; + + /* Set the prescaler between the LSI clock and the watchdog counter */ + STM32_IWDG_PR = IWDG_PRESCALER & 7; + /* Set the reload value of the watchdog counter */ + STM32_IWDG_RLR = watchdog_period & 0x7FF ; + + /* Start the watchdog (and re-lock registers) */ + STM32_IWDG_KR = 0xcccc; + + return EC_SUCCESS; +} + + +/* Low priority task to reload the watchdog */ +void watchdog_task(void) +{ + while (1) { +#ifdef BOARD_discovery + gpio_set_level(GPIO_GREEN_LED, 1); +#endif + usleep(500000); + watchdog_reload(); +#ifdef BOARD_discovery + gpio_set_level(GPIO_GREEN_LED, 0); +#endif + usleep(500000); + watchdog_reload(); + } +} |