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| author | Wei-Ning Huang <wnhuang@google.com> | 2017-05-07 14:42:46 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-05-12 10:49:49 -0700 |
| commit | 00da0f8c87e04ef5aaacebfc882e9055056bb30f (patch) | |
| tree | b74fa0a3432fd9e6c245183761fc9cca960d85b1 /chip/stm32 | |
| parent | 8df3b161e946b2b9aaa5e475766864d3fdb2a9ca (diff) | |
| download | chrome-ec-00da0f8c87e04ef5aaacebfc882e9055056bb30f.tar.gz | |
stm32: add clock configuration for stm32f412 to run at 96 MHz
Add clock definition for stmf412. New stm32f4 chip variant will have to
define their own clock definitions.
BUG=b:37187312
TEST=`make BOARD=rose- j`
Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004
Reviewed-on: https://chromium-review.googlesource.com/487848
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/clock-stm32f4.c | 13 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 15 |
2 files changed, 23 insertions, 5 deletions
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index 975effd564..353718f564 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -91,22 +91,25 @@ void config_hispeed_clock(void) pllinputclock = srcclock / plldiv; /* PLL output clock: Must be 100-432MHz */ - /* Valid values 50-432, we'll get 336MHz */ pllmult = (STM32F4_VCO_CLOCK + (pllinputclock / 2)) / pllinputclock; vcoclock = pllinputclock * pllmult; - /* CPU/System clock: Below 180MHz */ - /* We'll do 84MHz */ + /* CPU/System clock */ systemclock = vcoclock / 4; systemdivq = 1; /* USB clock = 48MHz exactly */ usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ; + assert(vcoclock / usbdiv == STM32F4_USB_REQ); + /* SYSTEM/I2S: same system clock */ i2sdiv = (vcoclock + (systemclock / 2)) / systemclock; - /* All IO clocks at 42MHz */ + /* All IO clocks at STM32F4_IO_CLOCK + * For STM32F446: max 45 MHz + * For STM32F412: max 50 MHz + */ /* AHB Prescalar */ - ahbpre = 0x8; /* AHB = system clock / 2*/ + ahbpre = 0x8; /* AHB = system clock / 2 */ /* NOTE: If apbXpre is not 0, timers are x2 clocked. RM0390 Fig. 13 */ apb1pre = 0; /* APB1 = AHB */ apb2pre = 0; /* APB2 = AHB */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 9ea87b7162..80c41c02b9 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -956,6 +956,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_CR_PLLON (1 << 24) #define STM32_RCC_CR_PLLRDY (1 << 25) +#if defined(CHIP_VARIANT_STM32F446) /* Required or recommended clocks for stm32f446 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 @@ -965,6 +966,20 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 +#elif defined(CHIP_VARIANT_STM32F412) +/* Required or recommended clocks for stm32f412 */ +#define STM32F4_PLL_REQ 2000000 +#define STM32F4_RTC_REQ 1000000 +#define STM32F4_IO_CLOCK 48000000 +#define STM32F4_USB_REQ 48000000 +#define STM32F4_VCO_CLOCK 384000000 +#define STM32F4_HSI_CLOCK 16000000 +#define STM32F4_LSI_CLOCK 32000 + +#else +#error "No valid clocks defined" +#endif + #define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) /* PLL Division factor */ #define PLLCFGR_PLLM_OFF 0 |