diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:28:10 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-29 08:18:52 +0000 |
| commit | a6e49676204857ec058c32ea8ff2703d6cd74bff (patch) | |
| tree | d57e22a0150827feeaa24ab74413e1c2c89fac48 /chip/stm32 | |
| parent | a64accc7e2116e70cabb72cf30d64c444f1820e6 (diff) | |
| download | chrome-ec-a6e49676204857ec058c32ea8ff2703d6cd74bff.tar.gz | |
chip/stm32/config-stm32l552xe.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I12e82c6905a3b2b520fd27dbf21595643bede41f
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729485
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/config-stm32l552xe.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h index 1b9c34c4aa..346da9320a 100644 --- a/chip/stm32/config-stm32l552xe.h +++ b/chip/stm32/config-stm32l552xe.h @@ -4,36 +4,36 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 109 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x4000D800 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x4000D800 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 16 /* DFU Address */ -#define STM32_DFU_BASE 0x0bf90000 +#define STM32_DFU_BASE 0x0bf90000 |