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| author | Yicheng Li <yichengli@chromium.org> | 2020-06-01 17:57:16 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-03 03:56:35 +0000 |
| commit | b2251706ae8e3850dace9f95156aba906986e2e6 (patch) | |
| tree | 19daf1658166bb9f189281b0ed664592e5a23106 /chip/stm32 | |
| parent | 1c036fc18ba017480ab8b3bc9811d8c86771ab98 (diff) | |
| download | chrome-ec-b2251706ae8e3850dace9f95156aba906986e2e6.tar.gz | |
chip/stm32: Don't reset the backup domain when initializing clock
For the STM32F4 chip family, this software reset of the backup domain
causes the RTC backup registers to be reset, which causes all backup
data to be lost.
The reset flag was not impacted because it's copied out before this
reset.
BRANCH=none
BUG=b:157059753
TEST=make -j BOARD=bloonchipper test-scratchpad
On console:
> runtest
=> PASS
> reboot
> runtest
=> FAIL, which is CORRECT
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Change-Id: I85777b7d8a99561198d0b9dc1f795b8f8f6e26c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226955
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Commit-Queue: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/clock-stm32f4.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index 1d1eff91e0..928e75771c 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -164,7 +164,6 @@ void config_hispeed_clock(void) ; /* Setup RTC Clock input */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; #ifdef CONFIG_STM32_CLOCK_HSE_HZ STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE); #else |