diff options
author | Vic Yang <victoryang@chromium.org> | 2014-10-17 15:13:37 -0700 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-21 00:44:39 +0000 |
commit | 959dcf9854cc6267a1e7ab642dadadacdc7c3ff7 (patch) | |
tree | 386a2182eabd3a3bc9e889d49d66e54819832e27 /chip/stm32 | |
parent | d0d6befc3f1195f993e22dfff97b16f6657f3dcc (diff) | |
download | chrome-ec-959dcf9854cc6267a1e7ab642dadadacdc7c3ff7.tar.gz |
stm32f: Add DMA interrupt handlers for channel 1 to 3
We already have interrupt handlers for channel 4 to 7. We need channel 3
for the new Ryu boards. Add the handlers for channel 1 to 3. Also,
instead of copy-pasting interrupt handlers, define a macro and declare
interrupt handlers with it.
BRANCH=None
BUG=chrome-os-partner:32660
TEST=make buildall
TEST=Check PD communication on the new Ryu board (with other CLs to
enable the new boards.)
Change-Id: I51d6bd16739f31a7efbeb4ec19bb91a1546fe21d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224175
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32')
-rw-r--r-- | chip/stm32/dma.c | 47 |
1 files changed, 17 insertions, 30 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index 290013ed8d..d151d3044f 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -292,36 +292,23 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 3); #else /* !CHIP_FAMILY_STM32F0 */ -void dma_event_interrupt_channel_4(void) -{ - dma_clear_isr(STM32_DMAC_CH4); - if (id[STM32_DMAC_CH4] != TASK_ID_INVALID) - task_wake(id[STM32_DMAC_CH4]); -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4, dma_event_interrupt_channel_4, 3); - -void dma_event_interrupt_channel_5(void) -{ - dma_clear_isr(STM32_DMAC_CH5); - if (id[STM32_DMAC_CH5] != TASK_ID_INVALID) - task_wake(id[STM32_DMAC_CH5]); -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_5, dma_event_interrupt_channel_5, 3); +#define DECLARE_DMA_IRQ(x) \ + void CONCAT2(dma_event_interrupt_channel_, x)(void) \ + { \ + dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ + if (id[CONCAT2(STM32_DMAC_CH, x)] != TASK_ID_INVALID) \ + task_wake(id[CONCAT2(STM32_DMAC_CH, x)]); \ + } \ + DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ + CONCAT2(dma_event_interrupt_channel_, x), 3); + +DECLARE_DMA_IRQ(1); +DECLARE_DMA_IRQ(2); +DECLARE_DMA_IRQ(3); +DECLARE_DMA_IRQ(4); +DECLARE_DMA_IRQ(5); +DECLARE_DMA_IRQ(6); +DECLARE_DMA_IRQ(7); -void dma_event_interrupt_channel_6(void) -{ - dma_clear_isr(STM32_DMAC_CH6); - if (id[STM32_DMAC_CH6] != TASK_ID_INVALID) - task_wake(id[STM32_DMAC_CH6]); -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_6, dma_event_interrupt_channel_6, 3); - -void dma_event_interrupt_channel_7(void) -{ - dma_clear_isr(STM32_DMAC_CH7); - if (id[STM32_DMAC_CH7] != TASK_ID_INVALID) - task_wake(id[STM32_DMAC_CH7]); -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_7, dma_event_interrupt_channel_7, 3); #endif /* CHIP_FAMILY_STM32F0 */ #endif /* CONFIG_DMA_DEFAULT_HANDLERS */ |