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| author | Moritz Fischer <moritz.fischer@ettus.com> | 2017-11-10 23:31:59 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-15 00:39:52 -0800 |
| commit | 2e7a6bc39e59c27620f7b7d14587a892b4fa988f (patch) | |
| tree | 16dc1a21e71056c64296a0a848633b8c3be01f33 /chip/stm32 | |
| parent | 2bb1811f074db4d33fa22209d4be1b303d93ef04 (diff) | |
| download | chrome-ec-2e7a6bc39e59c27620f7b7d14587a892b4fa988f.tar.gz | |
stm32: jtag: Enable clock to debug module on stm32f0x
Enables the clock to the debug module so that when connecting via SWD
debugger the watchdog and timers are stopped.
BRANCH=master
TEST=Build on stm32f0x board and connect via SWD, observe no watchdog
reset.
Change-Id: Ic40b16c09acc5920da2c1a39e9391a6b21849d2c
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/765290
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/registers.h | 1 | ||||
| -rw-r--r-- | chip/stm32/system.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 491718f631..cc43ba32bb 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -906,6 +906,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) #define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_DBGMCUEN (1 << 22) #define STM32_RCC_SYSCFGEN (1 << 0) #define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 884a5d9ed2..c9bc61a818 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -199,6 +199,9 @@ void chip_pre_init(void) STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; + + /* enable clock to debug module before writing */ + STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN; #elif defined(CHIP_FAMILY_STM32F3) apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | |