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authorNicolas Boichat <drinkcat@google.com>2017-01-11 14:17:33 +0800
committerchrome-bot <chrome-bot@chromium.org>2017-02-12 21:05:11 -0800
commit8c12f0a53f93e12530081fcbe164dab48257e58d (patch)
treece2873f66b05e28ad2d9b0170c52f5856f74eb1e /chip/stm32
parent14533749af1c89f3b0224092c580ebe147611299 (diff)
downloadchrome-ec-8c12f0a53f93e12530081fcbe164dab48257e58d.tar.gz
flash: Pass more precise parameter to flash_[physical_]protect_at_boot
In preparation for adding the rollback protection block, pass EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot, instead of an enumeration no protection/RO/ALL. This will later allow us to protect/unprotect the rollback region only, by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag. BRANCH=none BUG=chrome-os-partner:61671 TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection can be checked with flasherase/flashwrite. TEST=On hammer (stm32f072): flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp rw; reboot => RO+RW protected flashwp norw; reboot => only RO protected TEST=On reef (npcx): deassert WP, flashwp false; flashinfo => RO+RW not protected flashwp true => only RO protected reboot => only RO protected flashwp rw => RO+RW protected reboot => only RO protected Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f Reviewed-on: https://chromium-review.googlesource.com/430518 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32')
-rw-r--r--chip/stm32/flash-f.c19
-rw-r--r--chip/stm32/flash-stm32f4.c2
-rw-r--r--chip/stm32/flash-stm32l.c13
3 files changed, 16 insertions, 18 deletions
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
index 09a52ded2e..0c99ec398d 100644
--- a/chip/stm32/flash-f.c
+++ b/chip/stm32/flash-f.c
@@ -338,12 +338,11 @@ static int flash_physical_get_protect_at_boot(int block)
return (!(val & (1 << (block % 8)))) ? 1 : 0;
}
-int flash_physical_protect_at_boot(enum flash_wp_range range)
+int flash_physical_protect_at_boot(uint32_t new_flags)
{
int block;
int i;
int original_val[4], val[4];
- enum flash_wp_range cur_range;
for (i = 0; i < 4; ++i)
original_val[i] = val[i] = read_optb(i * 2 + 8);
@@ -351,14 +350,14 @@ int flash_physical_protect_at_boot(enum flash_wp_range range)
for (block = WP_BANK_OFFSET;
block < WP_BANK_OFFSET + PHYSICAL_BANKS;
block++) {
+ int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4;
- if (block >= WP_BANK_OFFSET + WP_BANK_COUNT)
- cur_range = FLASH_WP_ALL;
- else
- cur_range = FLASH_WP_RO;
+ if (block >= WP_BANK_OFFSET &&
+ block < WP_BANK_OFFSET + WP_BANK_COUNT)
+ protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT;
- if (cur_range <= range)
+ if (protect)
val[byte_off] = val[byte_off] & (~(1 << (block % 8)));
else
val[byte_off] = val[byte_off] | (1 << (block % 8));
@@ -434,7 +433,8 @@ int flash_pre_init(void)
* update to the write protect register and reboot so
* it takes effect.
*/
- flash_physical_protect_at_boot(FLASH_WP_RO);
+ flash_physical_protect_at_boot(
+ EC_FLASH_PROTECT_RO_AT_BOOT);
need_reset = 1;
}
@@ -448,8 +448,7 @@ int flash_pre_init(void)
* go away.
*/
flash_protect_at_boot(
- (prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) ?
- FLASH_WP_RO : FLASH_WP_NONE);
+ prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
need_reset = 1;
}
} else {
diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c
index 48815d6956..6b6b64f73a 100644
--- a/chip/stm32/flash-stm32f4.c
+++ b/chip/stm32/flash-stm32f4.c
@@ -196,7 +196,7 @@ static void clear_flash_errors(void)
/*****************************************************************************/
/* Physical layer APIs */
-int flash_physical_protect_at_boot(enum flash_wp_range range)
+int flash_physical_protect_at_boot(uint32_t new_flags)
{
return EC_SUCCESS;
}
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
index ce292bb58d..f796f4efaa 100644
--- a/chip/stm32/flash-stm32l.c
+++ b/chip/stm32/flash-stm32l.c
@@ -317,20 +317,20 @@ int flash_physical_get_protect(int block)
return STM32_FLASH_WRPR & (1 << block);
}
-int flash_physical_protect_at_boot(enum flash_wp_range range)
+int flash_physical_protect_at_boot(uint32_t new_flags)
{
uint32_t prot;
uint32_t mask = ((1 << WP_BANK_COUNT) - 1) << WP_BANK_OFFSET;
int rv;
- if (range == FLASH_WP_ALL)
+ if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT)
return EC_ERROR_UNIMPLEMENTED;
/* Read the current protection status */
prot = read_optb_wrp();
/* Set/clear bits */
- if (range == FLASH_WP_RO)
+ if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT)
prot |= mask;
else
prot &= ~mask;
@@ -448,7 +448,7 @@ int flash_pre_init(void)
* update to the write protect register and reboot so
* it takes effect.
*/
- flash_protect_at_boot(FLASH_WP_RO);
+ flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT);
need_reset = 1;
}
@@ -457,9 +457,8 @@ int flash_pre_init(void)
* Write protect register was in an inconsistent state.
* Set it back to a good state and reboot.
*/
- flash_protect_at_boot(
- (prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) ?
- FLASH_WP_RO : FLASH_WP_NONE);
+ flash_protect_at_boot(prot_flags &
+ EC_FLASH_PROTECT_RO_AT_BOOT);
need_reset = 1;
}
} else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW |