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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-06-08 16:02:10 +0200 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-13 09:19:52 -0700 |
| commit | 61e6d7cb5068b1d7ee0bf93763bb40d3b753581e (patch) | |
| tree | 3e3a9f701d7fd87b1980c66faa4d8b6d7b227645 /chip/stm32 | |
| parent | cbccb79691fc66e4958cc4f1c0d306dfd01a9f10 (diff) | |
| download | chrome-ec-61e6d7cb5068b1d7ee0bf93763bb40d3b753581e.tar.gz | |
stm32: move UART wake-up to uart code
Move the low-power mode UART register settings out of the STM32F0 low
power mode code into the UART driver as a preparation for adding STM32H7
low power mode code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75105319
TEST=make buildall
Change-Id: Iecac8c387edd80c15fc3a211cf7969bbc6b8a15e
Reviewed-on: https://chromium-review.googlesource.com/1096766
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 27 | ||||
| -rw-r--r-- | chip/stm32/uart.c | 17 |
2 files changed, 20 insertions, 24 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index d324e8bab5..d5f9d33d58 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -17,6 +17,7 @@ #include "system.h" #include "task.h" #include "timer.h" +#include "uart.h" #include "util.h" /* Console output macros */ @@ -288,28 +289,6 @@ void clock_refresh_console_in_use(void) { } -#ifdef CONFIG_FORCE_CONSOLE_RESUME -#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) -static void enable_serial_wakeup(int enable) -{ - if (enable) { - /* - * Allow UART wake up from STOP mode. Note, UART clock must - * be HSI(8MHz) for wakeup to work. - */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UESM; - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUFIE; - } else { - /* Disable wake up from STOP mode. */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UESM; - } -} -#else -static void enable_serial_wakeup(int enable) -{ -} -#endif - void __idle(void) { timestamp_t t0; @@ -343,7 +322,7 @@ void __idle(void) /* deep-sleep in STOP mode */ idle_dsleep_cnt++; - enable_serial_wakeup(1); + uart_enable_wakeup(1); /* set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; @@ -354,7 +333,7 @@ void __idle(void) CPU_SCB_SYSCTRL &= ~0x4; - enable_serial_wakeup(0); + uart_enable_wakeup(0); /* * By default only HSI 8MHz is enabled here. Re-enable diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index 8410497d72..313d2df91c 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -376,3 +376,20 @@ void uart_init(void) init_done = 1; } + +#ifdef CONFIG_FORCE_CONSOLE_RESUME +void uart_enable_wakeup(int enable) +{ + if (enable) { + /* + * Allow UART wake up from STOP mode. Note, UART clock must + * be HSI(8MHz) for wakeup to work. + */ + STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UESM; + STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUFIE; + } else { + /* Disable wake up from STOP mode. */ + STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UESM; + } +} +#endif |