stm32gx: ucpd: BIST mode control and correct nRetryCount

This CL implements the driver method to enable/disable BIST test mode
in the ucpd driver. When this mode is enabled, the upcd driver only
needs to send GoodCRC messages in response to BIST data messages which
are received.

This CL also fixes the value of nRetryCount to make it based off the
port partner'd USB-PD version.

BUG=b:181179550
BRANCH=None
TEST=Manual
Verified that nRetryCount fix enables TD.PD.LL.E3. Soft Reset Usage
to pass.

Verfied that adding BIST mode control enables TD.PD.PHY.E1. BIST
Test Data to pass.

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I251e1c3c235d976d934406cdb22df0c177c6f14b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2667241
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

2 files changed, 41 insertions, 11 deletions

diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
index c66dc7cc3e..bca99456f1 100644
--- a/chip/stm32/ucpd-stm32gx.c
+++ b/chip/stm32/ucpd-stm32gx.c
@@ -76,11 +76,9 @@ enum ucpd_state {
 #define UCPD_EVT_RX_MSG         BIT(9)
 
 #define UCPD_T_RECEIVE_US (1 * MSEC)
-#ifdef CONFIG_USB_PD_REV30
-#define UCPD_N_RETRY_COUNT 2
-#else
-#define UCPD_N_RETRY_COUNT 3
-#endif
+
+#define UCPD_N_RETRY_COUNT_REV20 3
+#define UCPD_N_RETRY_COUNT_REV30 2
 
 /*
  * Tx messages are iniated either by TCPM/PRL layer or from ucpd when a GoodCRC
@@ -116,6 +114,7 @@ static int ucpd_timeout_us;
 static enum ucpd_state ucpd_tx_state;
 static int msg_id_match;
 static int tx_retry_count;
+static int tx_retry_max;
 
 static int ucpd_txorderset[] = {
 	TX_ORDERSET_SOP,
@@ -133,6 +132,7 @@ static uint8_t ucpd_rx_buffer[UCPD_BUF_LEN];
 static int ucpd_crc_id;
 static bool ucpd_rx_sop_prime_enabled;
 static int ucpd_rx_msg_active;
+static bool ucpd_rx_bist_mode;
 
 #ifdef CONFIG_STM32G4_UCPD_DEBUG
 /* Defines and macros for ucpd state logging */
@@ -400,6 +400,7 @@ static void stm32gx_ucpd_state_init(int port)
 	/* Init variables used to manage rx */
 	ucpd_rx_sop_prime_enabled = 0;
 	ucpd_rx_msg_active = 0;
+	ucpd_rx_bist_mode = 0;
 }
 
 int stm32gx_ucpd_init(int port)
@@ -909,6 +910,9 @@ static void ucpd_manage_tx(int port, int evt)
 				/* Save msgID required for GoodCRC check */
 				hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header;
 				msg_id_match = PD_HEADER_ID(hdr);
+				tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ?
+					UCPD_N_RETRY_COUNT_REV30 :
+					UCPD_N_RETRY_COUNT_REV20;
 			}
 		}
 
@@ -933,7 +937,7 @@ static void ucpd_manage_tx(int port, int evt)
 			ucpd_timeout_us = UCPD_T_RECEIVE_US;
 		} else if (evt & UCPD_EVT_TX_MSG_DISC ||
 			   evt & UCPD_EVT_TX_MSG_FAIL) {
-			if (tx_retry_count < UCPD_N_RETRY_COUNT) {
+			if (tx_retry_count < tx_retry_max) {
 				if (evt & UCPD_EVT_RX_MSG) {
 					/*
 					 * A message was received so there is no
@@ -991,7 +995,7 @@ static void ucpd_manage_tx(int port, int evt)
 		} else if ((evt & UCPD_EVT_RX_GOOD_CRC) ||
 			   (evt & TASK_EVENT_TIMER)) {
 			/* GoodCRC w/out match or timeout waiting */
-			if (tx_retry_count < UCPD_N_RETRY_COUNT) {
+			if (tx_retry_count < tx_retry_max) {
 				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
 				msg_src = TX_MSG_TCPM;
 				tx_retry_count++;
@@ -1221,6 +1225,15 @@ int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head)
 	return EC_SUCCESS;
 }
 
+enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
+						   const bool enable)
+{
+	ucpd_rx_bist_mode = enable;
+	CPRINTS("ucpd: Bist test mode = %d", enable);
+
+	return EC_SUCCESS;
+}
+
 void stm32gx_ucpd1_irq(void)
 {
 	/* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */
@@ -1288,7 +1301,6 @@ void stm32gx_ucpd1_irq(void)
 		ucpd_rx_msg_active = 0;
 		/* Check for errors */
 		if (!(sr & STM32_UCPD_SR_RXERR)) {
-			int rv;
 			uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer;
 			enum tcpm_transmit_type type;
 			int good_crc = 0;
@@ -1312,10 +1324,16 @@ void stm32gx_ucpd1_irq(void)
 			if (!good_crc && (ucpd_rx_sop_prime_enabled ||
 					  type == TCPC_TX_SOP)) {
 
-				rv = tcpm_enqueue_message(port);
-				if (rv)
-					hook_call_deferred(&ucpd_rx_enque_error_data,
+				/*
+				 * If BIST test mode is active, then still need
+				 * to send GoodCRC reply, but there is no need
+				 * to send the message up to the tcpm layer.
+				 */
+				if(!ucpd_rx_bist_mode) {
+					if (tcpm_enqueue_message(port))
+						hook_call_deferred(&ucpd_rx_enque_error_data,
 							   0);
+				}
 
 				task_set_event(TASK_ID_UCPD,
 						       UCPD_EVT_RX_MSG);
diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h
index 59b2b7f9bc..0ffb8ffcd8 100644
--- a/chip/stm32/ucpd-stm32gx.h
+++ b/chip/stm32/ucpd-stm32gx.h
@@ -216,4 +216,16 @@ int stm32gx_ucpd_get_chip_info(int port, int live,
  */
 void ucpd_cc_detect_notify_enable(int enable);
 
+/**
+ * This function is used to enable/disable rx bist test mode in the ucpd
+ * driver. This mode is controlled at the PE layer. When this mode is enabled,
+ * the ucpd receiver will not pass BIST data messages to the protocol layer and
+ * only send GoodCRC replies.
+ *
+ * @param usbc_port -> USB-C Port number
+ * @param enable -> on/off control for rx bist mode
+ */
+enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port,
+						   const bool enable);
+
 #endif /* __CROS_EC_UCPD_STM32GX_H */