common: replace 1 << digits, with BIT(digits)

Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.

Fix an error in motion_lid try to set bit 31 of a signed integer.

BUG=None
BRANCH=None
TEST=compile

Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

17 files changed, 113 insertions, 113 deletions

diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c
index 0f31e3b286..3836767d1f 100644
--- a/chip/stm32/adc-stm32f0.c
+++ b/chip/stm32/adc-stm32f0.c
@@ -75,7 +75,7 @@ static void adc_init(void)
 	 * If clock is already enabled, and ADC module is enabled
 	 * then this is a warm reboot and ADC is already initialized.
 	 */
-	if (STM32_RCC_APB2ENR & (1 << 9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN))
+	if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN))
 		return;
 
 	/* Enable ADC clock */
@@ -107,7 +107,7 @@ static void adc_init(void)
 static void adc_configure(int ain_id)
 {
 	/* Select channel to convert */
-	STM32_ADC_CHSELR = 1 << ain_id;
+	STM32_ADC_CHSELR = BIT(ain_id);
 
 	/* Disable DMA */
 	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN;
@@ -126,16 +126,16 @@ static void adc_continuous_read(int ain_id)
 	STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT;
 
 	/* Start continuous conversion */
-	STM32_ADC_CR |= 1 << 2; /* ADSTART */
+	STM32_ADC_CR |= BIT(2); /* ADSTART */
 }
 
 static void adc_continuous_stop(void)
 {
 	/* Stop on-going conversion */
-	STM32_ADC_CR |= 1 << 4; /* ADSTP */
+	STM32_ADC_CR |= BIT(4); /* ADSTP */
 
 	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & (1 << 4))
+	while (STM32_ADC_CR & BIT(4))
 		;
 
 	/* CONT=0 -> continuous mode off */
@@ -173,7 +173,7 @@ static void adc_interval_read(int ain_id, int interval_ms)
 	STM32_TIM_CR1(TIM_ADC) |= 1;
 
 	/* Start ADC conversion */
-	STM32_ADC_CR |= 1 << 2; /* ADSTART */
+	STM32_ADC_CR |= BIT(2); /* ADSTART */
 }
 
 static void adc_interval_stop(void)
@@ -182,10 +182,10 @@ static void adc_interval_stop(void)
 	STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK;
 
 	/* Set ADSTP to clear ADSTART */
-	STM32_ADC_CR |= 1 << 4; /* ADSTP */
+	STM32_ADC_CR |= BIT(4); /* ADSTP */
 
 	/* Wait for conversion to stop */
-	while (STM32_ADC_CR & (1 << 4))
+	while (STM32_ADC_CR & BIT(4))
 		;
 
 	/* Stop the timer */
@@ -307,10 +307,10 @@ int adc_read_channel(enum adc_channel ch)
 	STM32_ADC_ISR = 0xe;
 
 	/* Start conversion */
-	STM32_ADC_CR |= 1 << 2; /* ADSTART */
+	STM32_ADC_CR |= BIT(2); /* ADSTART */
 
 	/* Wait for end of conversion */
-	while (!(STM32_ADC_ISR & (1 << 2)))
+	while (!(STM32_ADC_ISR & BIT(2)))
 		;
 	/* read converted value */
 	value = STM32_ADC_DR;
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c
index 6e22c49ac3..7bee47c319 100644
--- a/chip/stm32/adc-stm32f3.c
+++ b/chip/stm32/adc-stm32f3.c
@@ -59,10 +59,10 @@ static void adc_configure(int ain_id)
 	adc_set_channel(0, ain_id);
 
 	/* Disable DMA */
-	STM32_ADC_CR2 &= ~(1 << 8);
+	STM32_ADC_CR2 &= ~BIT(8);
 
 	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~(1 << 8);
+	STM32_ADC_CR1 &= ~BIT(8);
 }
 
 static void __attribute__((unused)) adc_configure_all(void)
@@ -75,25 +75,25 @@ static void __attribute__((unused)) adc_configure_all(void)
 		adc_set_channel(i, adc_channels[i].channel);
 
 	/* Enable DMA */
-	STM32_ADC_CR2 |= (1 << 8);
+	STM32_ADC_CR2 |= BIT(8);
 
 	/* Enable scan mode */
-	STM32_ADC_CR1 |= (1 << 8);
+	STM32_ADC_CR1 |= BIT(8);
 }
 
 static inline int adc_powered(void)
 {
-	return STM32_ADC_CR2 & (1 << 0);
+	return STM32_ADC_CR2 & BIT(0);
 }
 
 static inline int adc_conversion_ended(void)
 {
-	return STM32_ADC_SR & (1 << 1);
+	return STM32_ADC_SR & BIT(1);
 }
 
 static int adc_watchdog_enabled(void)
 {
-	return STM32_ADC_CR1 & (1 << 23);
+	return STM32_ADC_CR1 & BIT(23);
 }
 
 static int adc_enable_watchdog_no_lock(void)
@@ -111,16 +111,16 @@ static int adc_enable_watchdog_no_lock(void)
 	STM32_ADC_SR &= ~0x1;
 
 	/* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */
-	STM32_ADC_CR1 |= (1 << 9) | (1 << 8) | (1 << 6) | (1 << 23);
+	STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23);
 
 	/* Disable DMA */
-	STM32_ADC_CR2 &= ~(1 << 8);
+	STM32_ADC_CR2 &= ~BIT(8);
 
 	/* CONT=1 */
-	STM32_ADC_CR2 |= (1 << 1);
+	STM32_ADC_CR2 |= BIT(1);
 
 	/* Start conversion */
-	STM32_ADC_CR2 |= (1 << 0);
+	STM32_ADC_CR2 |= BIT(0);
 
 	return EC_SUCCESS;
 }
@@ -152,10 +152,10 @@ static int adc_disable_watchdog_no_lock(void)
 		return EC_ERROR_UNKNOWN;
 
 	/* AWDEN=0, AWDIE=0 */
-	STM32_ADC_CR1 &= ~(1 << 23) & ~(1 << 6);
+	STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6);
 
 	/* CONT=0 */
-	STM32_ADC_CR2 &= ~(1 << 1);
+	STM32_ADC_CR2 &= ~BIT(1);
 
 	return EC_SUCCESS;
 }
@@ -193,7 +193,7 @@ int adc_read_channel(enum adc_channel ch)
 	adc_configure(adc->channel);
 
 	/* Clear EOC bit */
-	STM32_ADC_SR &= ~(1 << 1);
+	STM32_ADC_SR &= ~BIT(1);
 
 	/* Start conversion (Note: For now only confirmed on F4) */
 #if defined(CHIP_FAMILY_STM32F4)
diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c
index 270d953252..69cacb0d0e 100644
--- a/chip/stm32/adc-stm32l.c
+++ b/chip/stm32/adc-stm32l.c
@@ -42,10 +42,10 @@ static void adc_configure(int ain_id)
 	adc_set_channel(0, ain_id);
 
 	/* Disable DMA */
-	STM32_ADC_CR2 &= ~(1 << 8);
+	STM32_ADC_CR2 &= ~BIT(8);
 
 	/* Disable scan mode */
-	STM32_ADC_CR1 &= ~(1 << 8);
+	STM32_ADC_CR1 &= ~BIT(8);
 }
 
 static void adc_configure_all(void)
@@ -58,22 +58,22 @@ static void adc_configure_all(void)
 		adc_set_channel(i, adc_channels[i].channel);
 
 	/* Enable DMA */
-	STM32_ADC_CR2 |= (1 << 8);
+	STM32_ADC_CR2 |= BIT(8);
 
 	/* Enable scan mode */
-	STM32_ADC_CR1 |= (1 << 8);
+	STM32_ADC_CR1 |= BIT(8);
 }
 
 static inline int adc_powered(void)
 {
-	return STM32_ADC_SR & (1 << 6); /* ADONS */
+	return STM32_ADC_SR & BIT(6); /* ADONS */
 }
 
 static void adc_enable_clock(void)
 {
-	STM32_RCC_APB2ENR |= (1 << 9);
+	STM32_RCC_APB2ENR |= BIT(9);
 	/* ADCCLK = HSI / 2 = 8MHz*/
-	STM32_ADC_CCR |= (1 << 16);
+	STM32_ADC_CCR |= BIT(16);
 }
 
 static void adc_init(void)
@@ -92,10 +92,10 @@ static void adc_init(void)
 
 	if (!adc_powered())
 		/* Power on ADC module */
-		STM32_ADC_CR2 |= (1 << 0);  /* ADON */
+		STM32_ADC_CR2 |= BIT(0);  /* ADON */
 
 	/* Set right alignment */
-	STM32_ADC_CR2 &= ~(1 << 11);
+	STM32_ADC_CR2 &= ~BIT(11);
 
 	/*
 	 * Set sample time of all channels to 16 cycles.
@@ -132,7 +132,7 @@ static void adc_release(void)
 
 static inline int adc_conversion_ended(void)
 {
-	return STM32_ADC_SR & (1 << 1);
+	return STM32_ADC_SR & BIT(1);
 }
 
 int adc_read_channel(enum adc_channel ch)
@@ -148,10 +148,10 @@ int adc_read_channel(enum adc_channel ch)
 	adc_configure(adc->channel);
 
 	/* Clear EOC bit */
-	STM32_ADC_SR &= ~(1 << 1);
+	STM32_ADC_SR &= ~BIT(1);
 
 	/* Start conversion */
-	STM32_ADC_CR2 |= (1 << 30); /* SWSTART */
+	STM32_ADC_CR2 |= BIT(30); /* SWSTART */
 
 	/* Wait for EOC bit set */
 	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
index 26188d97fd..24da104c3d 100644
--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -113,11 +113,11 @@ void config_hispeed_clock(void)
 {
 #ifdef CHIP_FAMILY_STM32F3
 	/* Ensure that HSE is ON */
-	if (!(STM32_RCC_CR & (1 << 17))) {
+	if (!(STM32_RCC_CR & BIT(17))) {
 		/* Enable HSE */
-		STM32_RCC_CR |= 1 << 16;
+		STM32_RCC_CR |= BIT(16);
 		/* Wait for HSE to be ready */
-		while (!(STM32_RCC_CR & (1 << 17)))
+		while (!(STM32_RCC_CR & BIT(17)))
 			;
 	}
 
@@ -186,11 +186,11 @@ defined(CHIP_VARIANT_STM32F070)
 		;
 #else
 	/* Ensure that HSI48 is ON */
-	if (!(STM32_RCC_CR2 & (1 << 17))) {
+	if (!(STM32_RCC_CR2 & BIT(17))) {
 		/* Enable HSI */
-		STM32_RCC_CR2 |= 1 << 16;
+		STM32_RCC_CR2 |= BIT(16);
 		/* Wait for HSI to be ready */
-		while (!(STM32_RCC_CR2 & (1 << 17)))
+		while (!(STM32_RCC_CR2 & BIT(17)))
 			;
 	}
 
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index 95d9b1e96c..30faa0035a 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -249,8 +249,8 @@ static void low_power_init(void)
 	task_enable_irq(STM32_IRQ_LPTIM1);
 
 	/* Wake-up interrupts from EXTI for USART and LPTIM */
-	STM32_EXTI_CPUIMR1 |= 1 << 26; /* [26] wkup26: USART1 wake-up */
-	STM32_EXTI_CPUIMR2 |= 1 << 15; /* [15] wkup47: LPTIM1 wake-up */
+	STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */
+	STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */
 
 	/* optimize power vs latency in STOP mode */
 	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK)
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c
index 93706c7019..b0903b5cb1 100644
--- a/chip/stm32/clock-stm32l.c
+++ b/chip/stm32/clock-stm32l.c
@@ -33,8 +33,8 @@ static int fake_hibernate;
  * because it's the lowest clock rate we can still run 115200 baud serial
  * for the debug console.
  */
-#define MSI_2MHZ_CLOCK (1 << 21)
-#define MSI_1MHZ_CLOCK (1 << 20)
+#define MSI_2MHZ_CLOCK BIT(21)
+#define MSI_1MHZ_CLOCK BIT(20)
 
 enum clock_osc {
 	OSC_INIT = 0,	/* Uninitialized */
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h
index d6959310d6..038dc76f7c 100644
--- a/chip/stm32/crc_hw.h
+++ b/chip/stm32/crc_hw.h
@@ -13,7 +13,7 @@
 static inline void crc32_init(void)
 {
 	/* switch on CRC controller */
-	STM32_RCC_AHBENR |= 1 << 6; /* switch on CRC controller */
+	STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */
 	/* Delay 1 AHB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_AHB, 1);
 	/* reset CRC state */
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
index fcd4b19e12..dd248e62f8 100644
--- a/chip/stm32/hwtimer.c
+++ b/chip/stm32/hwtimer.c
@@ -414,7 +414,7 @@ void hwtimer_setup_watchdog(void)
 	 * Timer configuration : Down counter, counter disabled, update
 	 * event only on overflow.
 	 */
-	timer->cr1 = 0x0014 | (1 << 7);
+	timer->cr1 = 0x0014 | BIT(7);
 
 	/* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */
 	timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4);
@@ -426,7 +426,7 @@ void hwtimer_setup_watchdog(void)
 	 * to obtain the number of times TIM_CLOCK_LSB can overflow before we
 	 * generate an interrupt.
 	 */
-	timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / (1 << 16);
+	timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16);
 
 	/* count on every TIM_CLOCK_LSB overflow */
 	timer->psc = 0;
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c
index ce2f8636f6..45d489a8c0 100644
--- a/chip/stm32/pwm.c
+++ b/chip/stm32/pwm.c
@@ -69,9 +69,9 @@ static void pwm_configure(enum pwm_channel ch)
 
 	/* Output, PWM mode 1, preload enable */
 	if (pwm->channel & 0x1)
-		*ccmr = (6 << 4) | (1 << 3);
+		*ccmr = (6 << 4) | BIT(3);
 	else
-		*ccmr = (6 << 12) | (1 << 11);
+		*ccmr = (6 << 12) | BIT(11);
 
 	/* Output enable. Set active high/low. */
 	if (pwm->flags & PWM_CONFIG_ACTIVE_LOW)
@@ -90,13 +90,13 @@ static void pwm_configure(enum pwm_channel ch)
 	 * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't
 	 * harmful on STM32L.
 	 */
-	tim->bdtr |= (1 << 15);
+	tim->bdtr |= BIT(15);
 
 	/* Generate update event to force loading of shadow registers */
 	tim->egr |= 1;
 
 	/* Enable auto-reload preload, start counting */
-	tim->cr1 |= (1 << 7) | (1 << 0);
+	tim->cr1 |= BIT(7) | BIT(0);
 
 	atomic_or(&using_pwm, 1 << ch);
 
@@ -113,7 +113,7 @@ static void pwm_disable(enum pwm_channel ch)
 		return;
 
 	/* Main output disable */
-	tim->bdtr &= ~(1 << 15);
+	tim->bdtr &= ~BIT(15);
 
 	/* Disable counter */
 	tim->cr1 &= ~0x1;
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index de10176c77..eda4e0960f 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -715,9 +715,9 @@ static int spi_get_protocol_info(struct host_cmd_handler_args *args)
 
 	memset(r, 0, sizeof(*r));
 #ifdef CONFIG_SPI_PROTOCOL_V2
-	r->protocol_versions |= (1 << 2);
+	r->protocol_versions |= BIT(2);
 #endif
-	r->protocol_versions |= (1 << 3);
+	r->protocol_versions |= BIT(3);
 	r->max_request_packet_size = SPI_MAX_REQUEST_SIZE;
 	r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE;
 	r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED;
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
index c7ff4f23d9..5f6124657e 100644
--- a/chip/stm32/system.c
+++ b/chip/stm32/system.c
@@ -285,24 +285,24 @@ void system_pre_init(void)
 	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN;
 #elif defined(CHIP_FAMILY_STM32H7)
 	/* enable backup registers */
-	STM32_RCC_AHB4ENR |= 1 << 28;
+	STM32_RCC_AHB4ENR |= BIT(28);
 #else
 	/* enable backup registers */
-	STM32_RCC_APB1ENR |= 1 << 27;
+	STM32_RCC_APB1ENR |= BIT(27);
 #endif
 	/* Delay 1 APB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* Enable access to RCC CSR register and RTC backup registers */
-	STM32_PWR_CR |= 1 << 8;
+	STM32_PWR_CR |= BIT(8);
 #ifdef CHIP_VARIANT_STM32L476
 	/* Enable Vddio2 */
-	STM32_PWR_CR2 |= 1 << 9;
+	STM32_PWR_CR2 |= BIT(9);
 #endif
 
 	/* switch on LSI */
-	STM32_RCC_CSR |= 1 << 0;
+	STM32_RCC_CSR |= BIT(0);
 	/* Wait for LSI to be ready */
-	while (!(STM32_RCC_CSR & (1 << 1)))
+	while (!(STM32_RCC_CSR & BIT(1)))
 		;
 	/* re-configure RTC if needed */
 #ifdef CHIP_FAMILY_STM32L
diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c
index 0ef357466c..4d3ea20b8c 100644
--- a/chip/stm32/usart.c
+++ b/chip/stm32/usart.c
@@ -47,12 +47,12 @@ void usart_init(struct usart_config const *config)
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
     defined(CHIP_FAMILY_STM32L4)
 	if (config->flags & USART_CONFIG_FLAG_RX_INV)
-		cr2 |= (1 << 16);
+		cr2 |= BIT(16);
 	if (config->flags & USART_CONFIG_FLAG_TX_INV)
-		cr2 |= (1 << 17);
+		cr2 |= BIT(17);
 #endif
 	if (config->flags & USART_CONFIG_FLAG_HDSEL)
-		cr3 |= (1 << 3);
+		cr3 |= BIT(3);
 
 	STM32_USART_CR1(base) = 0x0000;
 	STM32_USART_CR2(base) = cr2;
diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h
index 53b13762e9..771c0ccfde 100644
--- a/chip/stm32/usart.h
+++ b/chip/stm32/usart.h
@@ -134,9 +134,9 @@ struct usart_config {
 	int baud;
 
 	/* Other flags (rx/tx inversion, half-duplex). */
-#define USART_CONFIG_FLAG_RX_INV (1 << 0)
-#define USART_CONFIG_FLAG_TX_INV (1 << 1)
-#define USART_CONFIG_FLAG_HDSEL (1 << 2)
+#define USART_CONFIG_FLAG_RX_INV BIT(0)
+#define USART_CONFIG_FLAG_TX_INV BIT(1)
+#define USART_CONFIG_FLAG_HDSEL BIT(2)
 	unsigned int flags;
 
 	struct consumer consumer;
diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c
index 97bb93cafd..de755f2fdd 100644
--- a/chip/stm32/usb-stm32f0.c
+++ b/chip/stm32/usb-stm32f0.c
@@ -14,13 +14,13 @@ void usb_connect(void)
 	/* USB is in use */
 	disable_sleep(SLEEP_MASK_USB_DEVICE);
 
-	STM32_USB_BCDR |= (1 << 15) /* DPPU */;
+	STM32_USB_BCDR |= BIT(15) /* DPPU */;
 }
 
 void usb_disconnect(void)
 {
 	/* disable pull-up on DP to disconnect */
-	STM32_USB_BCDR &= ~(1 << 15) /* DPPU */;
+	STM32_USB_BCDR &= ~BIT(15) /* DPPU */;
 
 	/* USB is off, so sleep whenever */
 	enable_sleep(SLEEP_MASK_USB_DEVICE);
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c
index c8768823d7..82b418707a 100644
--- a/chip/stm32/usb.c
+++ b/chip/stm32/usb.c
@@ -351,7 +351,7 @@ static void ep0_event(enum usb_ep_event evt)
 	if (evt != USB_EVENT_RESET)
 		return;
 
-	STM32_USB_EP(0) = (1 << 9) /* control EP */ |
+	STM32_USB_EP(0) = BIT(9) /* control EP */ |
 			  (2 << 4) /* TX NAK */ |
 			  (3 << 12) /* RX VALID */;
 
@@ -673,8 +673,8 @@ void usb_init(void)
 	STM32_USB_BTABLE = 0;
 
 	/* EXTI18 is USB wake up interrupt */
-	/* STM32_EXTI_RTSR |= 1 << 18; */
-	/* STM32_EXTI_IMR |= 1 << 18; */
+	/* STM32_EXTI_RTSR |= BIT(18); */
+	/* STM32_EXTI_IMR |= BIT(18); */
 
 	/* Enable interrupt handlers */
 	task_enable_irq(STM32_IRQ_USB_LP);
diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h
index 9d656df22d..f8b90c1d1f 100644
--- a/chip/stm32/usb_dwc_registers.h
+++ b/chip/stm32/usb_dwc_registers.h
@@ -131,8 +131,8 @@ extern struct dwc_usb usb_ctl;
 #define GR_USB_GNPTXFSIZ              GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
 /*#define GR_USB_GGPIO                  GR_USB_REG(GC_USB_GGPIO_OFFSET)*/
 #define GR_USB_GCCFG                  GR_USB_REG(GC_USB_GCCFG_OFFSET)
-#define  GCCFG_VBDEN            (1 << 21)
-#define  GCCFG_PWRDWN           (1 << 16)
+#define  GCCFG_VBDEN            BIT(21)
+#define  GCCFG_PWRDWN           BIT(16)
 #define GR_USB_PCGCCTL                GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
 
 #define GR_USB_GSNPSID                GR_USB_REG(GC_USB_GSNPSID_OFFSET)
@@ -156,9 +156,9 @@ extern struct dwc_usb usb_ctl;
 #define GR_USB_DTHRCTL                GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
 #define  DTHRCTL_TXTHRLEN_6           (0x40 << 2)
 #define  DTHRCTL_RXTHRLEN_6           (0x40 << 17)
-#define  DTHRCTL_RXTHREN              (1 << 16)
-#define  DTHRCTL_ISOTHREN             (1 << 1)
-#define  DTHRCTL_NONISOTHREN          (1 << 0)
+#define  DTHRCTL_RXTHREN              BIT(16)
+#define  DTHRCTL_ISOTHREN             BIT(1)
+#define  DTHRCTL_NONISOTHREN          BIT(0)
 #define GR_USB_DIEPEMPMSK             GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
 
 #define GR_USB_EPIREG(off, n)         GR_USB_REG(0x900 + (n) * 0x20 + (off))
@@ -176,7 +176,7 @@ extern struct dwc_usb usb_ctl;
 #define GR_USB_DOEPDMAB(n)            GR_USB_EPOREG(0x1c, n)
 
 #define GOTGCTL_BVALOEN               (1 << GC_USB_GOTGCTL_BVALIDOVEN_LSB)
-#define GOTGCTL_BVALOVAL              (1 << 7)
+#define GOTGCTL_BVALOVAL              BIT(7)
 
 /* Bit 5 */
 #define GAHBCFG_DMA_EN                (1 << GC_USB_GAHBCFG_DMAEN_LSB)
@@ -187,7 +187,7 @@ extern struct dwc_usb usb_ctl;
 /* Bit 7 */
 #define GAHBCFG_NP_TXF_EMP_LVL        (1 <<  GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
 #define GAHBCFG_TXFELVL               GAHBCFG_NP_TXF_EMP_LVL
-#define GAHBCFG_PTXFELVL              (1 << 8)
+#define GAHBCFG_PTXFELVL              BIT(8)
 
 #define GUSBCFG_TOUTCAL(n)            (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \
 				       & GC_USB_GUSBCFG_TOUTCAL_MASK)
@@ -195,19 +195,19 @@ extern struct dwc_usb usb_ctl;
 				       & GC_USB_GUSBCFG_USBTRDTIM_MASK)
 /* Force device mode */
 #define GUSBCFG_FDMOD                 (1 << GC_USB_GUSBCFG_FDMOD_LSB)
-#define GUSBCFG_PHYSEL                (1 << 6)
-#define GUSBCFG_SRPCAP                (1 << 8)
-#define GUSBCFG_HNPCAP                (1 << 9)
-#define GUSBCFG_ULPIFSLS              (1 << 17)
-#define GUSBCFG_ULPIAR                (1 << 18)
-#define GUSBCFG_ULPICSM               (1 << 19)
-#define GUSBCFG_ULPIEVBUSD            (1 << 20)
-#define GUSBCFG_ULPIEVBUSI            (1 << 21)
-#define GUSBCFG_TSDPS                 (1 << 22)
-#define GUSBCFG_PCCI                  (1 << 23)
-#define GUSBCFG_PTCI                  (1 << 24)
-#define GUSBCFG_ULPIIPD               (1 << 25)
-#define GUSBCFG_TSDPS                 (1 << 22)
+#define GUSBCFG_PHYSEL                BIT(6)
+#define GUSBCFG_SRPCAP                BIT(8)
+#define GUSBCFG_HNPCAP                BIT(9)
+#define GUSBCFG_ULPIFSLS              BIT(17)
+#define GUSBCFG_ULPIAR                BIT(18)
+#define GUSBCFG_ULPICSM               BIT(19)
+#define GUSBCFG_ULPIEVBUSD            BIT(20)
+#define GUSBCFG_ULPIEVBUSI            BIT(21)
+#define GUSBCFG_TSDPS                 BIT(22)
+#define GUSBCFG_PCCI                  BIT(23)
+#define GUSBCFG_PTCI                  BIT(24)
+#define GUSBCFG_ULPIIPD               BIT(25)
+#define GUSBCFG_TSDPS                 BIT(22)
 
 
 #define GRSTCTL_CSFTRST               (1 << GC_USB_GRSTCTL_CSFTRST_LSB)
@@ -313,12 +313,12 @@ extern struct dwc_usb usb_ctl;
 #define DOEPDMA_BS_HOST_BSY           (3 << 30)
 #define DOEPDMA_BS_MASK               (3 << 30)
 #define DOEPDMA_RXSTS_MASK            (3 << 28)
-#define DOEPDMA_LAST                  (1 << 27)
-#define DOEPDMA_SP                    (1 << 26)
-#define DOEPDMA_IOC                   (1 << 25)
-#define DOEPDMA_SR                    (1 << 24)
-#define DOEPDMA_MTRF                  (1 << 23)
-#define DOEPDMA_NAK                   (1 << 16)
+#define DOEPDMA_LAST                  BIT(27)
+#define DOEPDMA_SP                    BIT(26)
+#define DOEPDMA_IOC                   BIT(25)
+#define DOEPDMA_SR                    BIT(24)
+#define DOEPDMA_MTRF                  BIT(23)
+#define DOEPDMA_NAK                   BIT(16)
 #define DOEPDMA_RXBYTES(n)            (((n) & 0xFFFF) << 0)
 #define DOEPDMA_RXBYTES_MASK          (0xFFFF << 0)
 
@@ -328,9 +328,9 @@ extern struct dwc_usb usb_ctl;
 #define DIEPDMA_BS_HOST_BSY           (3 << 30)
 #define DIEPDMA_BS_MASK               (3 << 30)
 #define DIEPDMA_TXSTS_MASK            (3 << 28)
-#define DIEPDMA_LAST                  (1 << 27)
-#define DIEPDMA_SP                    (1 << 26)
-#define DIEPDMA_IOC                   (1 << 25)
+#define DIEPDMA_LAST                  BIT(27)
+#define DIEPDMA_SP                    BIT(26)
+#define DIEPDMA_IOC                   BIT(25)
 #define DIEPDMA_TXBYTES(n)            (((n) & 0xFFFF) << 0)
 #define DIEPDMA_TXBYTES_MASK          (0xFFFF << 0)
 
@@ -942,31 +942,31 @@ extern struct dwc_usb usb_ctl;
 #define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET     0xc
 
 #define GC_USB_GUSBCFG_PCCI_LSB                  23
-#define GC_USB_GUSBCFG_PCCI_MASK                 (1 << 23)
+#define GC_USB_GUSBCFG_PCCI_MASK                 BIT(23)
 #define GC_USB_GUSBCFG_PCCI_SIZE                 0x1
 #define GC_USB_GUSBCFG_PCCI_DEFAULT              0x0
 #define GC_USB_GUSBCFG_PCCI_OFFSET               0xc
 
 #define GC_USB_GUSBCFG_PTCI_LSB                  24
-#define GC_USB_GUSBCFG_PTCI_MASK                 (1 << 24)
+#define GC_USB_GUSBCFG_PTCI_MASK                 BIT(24)
 #define GC_USB_GUSBCFG_PTCI_SIZE                 0x1
 #define GC_USB_GUSBCFG_PTCI_DEFAULT              0x0
 #define GC_USB_GUSBCFG_PTCI_OFFSET               0xc
 
 #define GC_USB_GUSBCFG_ULPIIPD_LSB               25
-#define GC_USB_GUSBCFG_ULPIIPD_MASK              (1 << 25)
+#define GC_USB_GUSBCFG_ULPIIPD_MASK              BIT(25)
 #define GC_USB_GUSBCFG_ULPIIPD_SIZE              0x1
 #define GC_USB_GUSBCFG_ULPIIPD_DEFAULT           0x0
 #define GC_USB_GUSBCFG_ULPIIPD_OFFSET            0xc
 
 #define GC_USB_GUSBCFG_FHMOD_LSB                 29
-#define GC_USB_GUSBCFG_FHMOD_MASK                (1 << 29)
+#define GC_USB_GUSBCFG_FHMOD_MASK                BIT(29)
 #define GC_USB_GUSBCFG_FHMOD_SIZE                0x1
 #define GC_USB_GUSBCFG_FHMOD_DEFAULT             0x0
 #define GC_USB_GUSBCFG_FHMOD_OFFSET              0xc
 
 #define GC_USB_GUSBCFG_FDMOD_LSB                 30
-#define GC_USB_GUSBCFG_FDMOD_MASK                (1 << 30)
+#define GC_USB_GUSBCFG_FDMOD_MASK                BIT(30)
 #define GC_USB_GUSBCFG_FDMOD_SIZE                0x1
 #define GC_USB_GUSBCFG_FDMOD_DEFAULT             0x0
 #define GC_USB_GUSBCFG_FDMOD_OFFSET              0xc
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
index 8c6ecca110..92656a1582 100644
--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -176,7 +176,7 @@ int pd_find_preamble(int port)
 			}
 		}
 		cnt = vals[bit] - vals[bit-1];
-		all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? 1 << 31 : 0);
+		all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0);
 		if (all == 0x36db6db6)
 			return bit - 1; /* should be SYNC-1 */
 		if (all == 0xF33F3F3F)
@@ -557,7 +557,7 @@ void pd_hw_init_rx(int port)
 	/* --- DAC configuration for comparator at 850mV --- */
 #ifdef CONFIG_PD_USE_DAC_AS_REF
 	/* Enable DAC interface clock. */
-	STM32_RCC_APB1ENR |= (1 << 29);
+	STM32_RCC_APB1ENR |= BIT(29);
 	/* Delay 1 APB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* set voltage Vout=0.850V (Vref = 3.0V) */
@@ -570,7 +570,7 @@ void pd_hw_init_rx(int port)
 #ifdef CONFIG_USB_PD_INTERNAL_COMP
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
 	/* turn on COMP/SYSCFG */
-	STM32_RCC_APB2ENR |= 1 << 0;
+	STM32_RCC_APB2ENR |= BIT(0);
 	/* Delay 1 APB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
@@ -583,12 +583,12 @@ void pd_hw_init_rx(int port)
 			 CMP2OUTSEL |
 			 STM32_COMP_CMP2HYST_HI;
 #elif defined(CHIP_FAMILY_STM32L)
-	STM32_RCC_APB1ENR |= 1 << 31; /* turn on COMP */
+	STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */
 
 	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1
 			| STM32_COMP_SPEED_FAST;
 	/* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */
-	STM32_RI_ASCR2 |= 1 << 4;
+	STM32_RI_ASCR2 |= BIT(4);
 #else
 #error Unsupported chip family
 #endif
@@ -641,7 +641,7 @@ void pd_hw_init(int port, int role)
 	/* 50% duty cycle on the output */
 	phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2;
 	/* Timer channel output configuration */
-	val = (6 << 4) | (1 << 3);
+	val = (6 << 4) | BIT(3);
 	if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */
 		val <<= 8;
 	if (TIM_TX_CCR_IDX(port) <= 2)