diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2021-11-04 12:11:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-05 04:22:34 +0000 |
| commit | 252457d4b21f46889eebad61d4c0a65331919cec (patch) | |
| tree | 01856c4d31d710b20e85a74c8d7b5836e35c3b98 /chip/stm32 | |
| parent | 08f5a1e6fc2c9467230444ac9b582dcf4d9f0068 (diff) | |
| download | chrome-ec-252457d4b21f46889eebad61d4c0a65331919cec.tar.gz | |
ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'chip/stm32')
160 files changed, 0 insertions, 53417 deletions
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c deleted file mode 100644 index b0654132cd..0000000000 --- a/chip/stm32/adc-stm32f0.c +++ /dev/null @@ -1,346 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -struct mutex adc_lock; - -struct adc_profile_t { - /* Register values. */ - uint32_t cfgr1_reg; - uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ - uint32_t ier_reg; - /* DMA config. */ - const struct dma_option *dma_option; - /* Size of DMA buffer, in units of ADC_CH_COUNT. */ - int dma_buffer_size; -}; - -#ifdef CONFIG_ADC_PROFILE_SINGLE -static const struct dma_option dma_single = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, - STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT, -}; - -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_13_5_CY -#endif - -static const struct adc_profile_t profile = { - /* Sample all channels once using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - .ier_reg = 0, - .dma_option = &dma_single, - .dma_buffer_size = 1, -}; -#endif - -#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS - -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY -#endif - -static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, - STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, -}; - -static const struct adc_profile_t profile = { - /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | - STM32_ADC_CFGR1_DMACFG, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - /* Fire interrupt at end of sequence. */ - .ier_reg = STM32_ADC_IER_EOSEQIE, - .dma_option = &dma_continuous, - /* Double-buffer our samples. */ - .dma_buffer_size = 2, -}; -#endif - -static void adc_init(const struct adc_t *adc) -{ - /* - * If clock is already enabled, and ADC module is enabled - * then this is a warm reboot and ADC is already initialized. - */ - if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN)) - return; - - /* Enable ADC clock */ - clock_enable_module(MODULE_ADC, 1); - /* check HSI14 in RCC ? ON by default */ - - /* ADC calibration (done with ADEN = 0) */ - STM32_ADC_CR = STM32_ADC_CR_ADCAL; /* set ADCAL = 1, ADC off */ - /* wait for the end of calibration */ - while (STM32_ADC_CR & STM32_ADC_CR_ADCAL) - ; - - /* Single conversion, right aligned, 12-bit */ - STM32_ADC_CFGR1 = profile.cfgr1_reg; - /* clock is ADCCLK (ADEN must be off when writing this reg) */ - STM32_ADC_CFGR2 = profile.cfgr2_reg; - - /* - * ADC enable (note: takes 4 ADC clocks between end of calibration - * and setting ADEN). - */ - STM32_ADC_CR = STM32_ADC_CR_ADEN; - while (!(STM32_ADC_ISR & STM32_ADC_ISR_ADRDY)) - STM32_ADC_CR = STM32_ADC_CR_ADEN; -} - -static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate) -{ - /* Sampling time */ - if (sample_rate == STM32_ADC_SMPR_DEFAULT || - sample_rate >= STM32_ADC_SMPR_COUNT) - STM32_ADC_SMPR = profile.smpr_reg; - else - STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate); - - /* Select channel to convert */ - STM32_ADC_CHSELR = BIT(ain_id); - - /* Disable DMA */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN; -} - -#ifdef CONFIG_ADC_WATCHDOG - -static int watchdog_ain_id; -static int watchdog_delay_ms; - -static void adc_continuous_read(int ain_id) -{ - adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT); - - /* CONT=1 -> continuous mode on */ - STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT; - - /* Start continuous conversion */ - STM32_ADC_CR |= BIT(2); /* ADSTART */ -} - -static void adc_continuous_stop(void) -{ - /* Stop on-going conversion */ - STM32_ADC_CR |= BIT(4); /* ADSTP */ - - /* Wait for conversion to stop */ - while (STM32_ADC_CR & BIT(4)) - ; - - /* CONT=0 -> continuous mode off */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_CONT; -} - -static void adc_interval_read(int ain_id, int interval_ms) -{ - adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT); - - /* EXTEN=01 -> hardware trigger detection on rising edge */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) - | STM32_ADC_CFGR1_EXTEN_RISE; - - /* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) | - STM32_ADC_CFGR1_TRG3; - - __hw_timer_enable_clock(TIM_ADC, 1); - - /* Upcounter, counter disabled, update event only on underflow */ - STM32_TIM_CR1(TIM_ADC) = 0x0004; - - /* TRGO on update event */ - STM32_TIM_CR2(TIM_ADC) = 0x0020; - STM32_TIM_SMCR(TIM_ADC) = 0x0000; - - /* Auto-reload value */ - STM32_TIM_ARR(TIM_ADC) = interval_ms & 0xffff; - - /* Set prescaler to tick per millisecond */ - STM32_TIM_PSC(TIM_ADC) = (clock_get_freq() / MSEC) - 1; - - /* Start counting */ - STM32_TIM_CR1(TIM_ADC) |= 1; - - /* Start ADC conversion */ - STM32_ADC_CR |= BIT(2); /* ADSTART */ -} - -static void adc_interval_stop(void) -{ - /* EXTEN=00 -> hardware trigger detection disabled */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK; - - /* Set ADSTP to clear ADSTART */ - STM32_ADC_CR |= BIT(4); /* ADSTP */ - - /* Wait for conversion to stop */ - while (STM32_ADC_CR & BIT(4)) - ; - - /* Stop the timer */ - STM32_TIM_CR1(TIM_ADC) &= ~0x1; -} - -static int adc_watchdog_enabled(void) -{ - return STM32_ADC_CFGR1 & STM32_ADC_CFGR1_AWDEN; -} - -static int adc_enable_watchdog_no_lock(void) -{ - /* Select channel */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_AWDCH_MASK) | - (watchdog_ain_id << 26); - adc_configure(watchdog_ain_id, STM32_ADC_SMPR_DEFAULT); - - /* Clear AWD interrupt flag */ - STM32_ADC_ISR = 0x80; - /* Set Watchdog enable bit on a single channel */ - STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_AWDEN | STM32_ADC_CFGR1_AWDSGL; - /* Enable interrupt */ - STM32_ADC_IER |= STM32_ADC_IER_AWDIE; - - if (watchdog_delay_ms) - adc_interval_read(watchdog_ain_id, watchdog_delay_ms); - else - adc_continuous_read(watchdog_ain_id); - - return EC_SUCCESS; -} - -int adc_enable_watchdog(int ain_id, int high, int low) -{ - int ret; - - mutex_lock(&adc_lock); - - watchdog_ain_id = ain_id; - - /* Set thresholds */ - STM32_ADC_TR = ((high & 0xfff) << 16) | (low & 0xfff); - - ret = adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - return ret; -} - -static int adc_disable_watchdog_no_lock(void) -{ - if (watchdog_delay_ms) - adc_interval_stop(); - else - adc_continuous_stop(); - - /* Clear Watchdog enable bit */ - STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_AWDEN; - - return EC_SUCCESS; -} - -int adc_disable_watchdog(void) -{ - int ret; - - mutex_lock(&adc_lock); - ret = adc_disable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - - return ret; -} - -int adc_set_watchdog_delay(int delay_ms) -{ - int resume_watchdog = 0; - - mutex_lock(&adc_lock); - if (adc_watchdog_enabled()) { - resume_watchdog = 1; - adc_disable_watchdog_no_lock(); - } - - watchdog_delay_ms = delay_ms; - - if (resume_watchdog) - adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - - return EC_SUCCESS; -} - -#else /* CONFIG_ADC_WATCHDOG */ - -static int adc_watchdog_enabled(void) { return 0; } -static int adc_enable_watchdog_no_lock(void) { return 0; } -static int adc_disable_watchdog_no_lock(void) { return 0; } - -#endif /* CONFIG_ADC_WATCHDOG */ - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - int restore_watchdog = 0; - - mutex_lock(&adc_lock); - - adc_init(adc); - - if (adc_watchdog_enabled()) { - restore_watchdog = 1; - adc_disable_watchdog_no_lock(); - } - - adc_configure(adc->channel, adc->sample_rate); - - /* Clear flags */ - STM32_ADC_ISR = 0xe; - - /* Start conversion */ - STM32_ADC_CR |= BIT(2); /* ADSTART */ - - /* Wait for end of conversion */ - while (!(STM32_ADC_ISR & BIT(2))) - ; - /* read converted value */ - value = STM32_ADC_DR; - - if (restore_watchdog) - adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - - return value * adc->factor_mul / adc->factor_div + adc->shift; -} - -void adc_disable(void) -{ - STM32_ADC_CR |= STM32_ADC_CR_ADDIS; - /* - * Note that the ADC is not in OFF state immediately. - * Once the ADC is effectively put into OFF state, - * STM32_ADC_CR_ADDIS bit will be cleared by hardware. - */ -} diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c deleted file mode 100644 index 543a44ab1a..0000000000 --- a/chip/stm32/adc-stm32f3.c +++ /dev/null @@ -1,259 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ - -#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \ - ((v) << 12) | ((v) << 15) | ((v) << 18) | \ - ((v) << 21)) -#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27)) - -/* Default ADC sample time = 13.5 cycles */ -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME 2 -#endif - -struct mutex adc_lock; - -static int watchdog_ain_id; - -static inline void adc_set_channel(int sample_id, int channel) -{ - uint32_t mask, val; - volatile uint32_t *sqr_reg; - - if (sample_id < 6) { - mask = 0x1f << (sample_id * 5); - val = channel << (sample_id * 5); - sqr_reg = &STM32_ADC_SQR3; - } else if (sample_id < 12) { - mask = 0x1f << ((sample_id - 6) * 5); - val = channel << ((sample_id - 6) * 5); - sqr_reg = &STM32_ADC_SQR2; - } else { - mask = 0x1f << ((sample_id - 12) * 5); - val = channel << ((sample_id - 12) * 5); - sqr_reg = &STM32_ADC_SQR1; - } - - *sqr_reg = (*sqr_reg & ~mask) | val; -} - -static void adc_configure(int ain_id) -{ - /* Set ADC channel */ - adc_set_channel(0, ain_id); - - /* Disable DMA */ - STM32_ADC_CR2 &= ~BIT(8); - - /* Disable scan mode */ - STM32_ADC_CR1 &= ~BIT(8); -} - -static void __attribute__((unused)) adc_configure_all(void) -{ - int i; - - /* Set ADC channels */ - STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20; - for (i = 0; i < ADC_CH_COUNT; ++i) - adc_set_channel(i, adc_channels[i].channel); - - /* Enable DMA */ - STM32_ADC_CR2 |= BIT(8); - - /* Enable scan mode */ - STM32_ADC_CR1 |= BIT(8); -} - -static inline int adc_powered(void) -{ - return STM32_ADC_CR2 & BIT(0); -} - -static inline int adc_conversion_ended(void) -{ - return STM32_ADC_SR & BIT(1); -} - -static int adc_watchdog_enabled(void) -{ - return STM32_ADC_CR1 & BIT(23); -} - -static int adc_enable_watchdog_no_lock(void) -{ - /* Fail if watchdog already enabled */ - if (adc_watchdog_enabled()) - return EC_ERROR_UNKNOWN; - - /* Set channel */ - STM32_ADC_SQR3 = watchdog_ain_id; - STM32_ADC_SQR1 = 0; - STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id; - - /* Clear interrupt bit */ - STM32_ADC_SR &= ~0x1; - - /* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */ - STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23); - - /* Disable DMA */ - STM32_ADC_CR2 &= ~BIT(8); - - /* CONT=1 */ - STM32_ADC_CR2 |= BIT(1); - - /* Start conversion */ - STM32_ADC_CR2 |= BIT(0); - - return EC_SUCCESS; -} - -int adc_enable_watchdog(int ain_id, int high, int low) -{ - int ret; - - if (!adc_powered()) - return EC_ERROR_UNKNOWN; - - mutex_lock(&adc_lock); - - watchdog_ain_id = ain_id; - - /* Set thresholds */ - STM32_ADC_HTR = high & 0xfff; - STM32_ADC_LTR = low & 0xfff; - - ret = adc_enable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - return ret; -} - -static int adc_disable_watchdog_no_lock(void) -{ - /* Fail if watchdog not running */ - if (!adc_watchdog_enabled()) - return EC_ERROR_UNKNOWN; - - /* AWDEN=0, AWDIE=0 */ - STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6); - - /* CONT=0 */ - STM32_ADC_CR2 &= ~BIT(1); - - return EC_SUCCESS; -} - -int adc_disable_watchdog(void) -{ - int ret; - - if (!adc_powered()) - return EC_ERROR_UNKNOWN; - - mutex_lock(&adc_lock); - ret = adc_disable_watchdog_no_lock(); - mutex_unlock(&adc_lock); - return ret; -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - int restore_watchdog = 0; - timestamp_t deadline; - - if (!adc_powered()) - return EC_ERROR_UNKNOWN; - - mutex_lock(&adc_lock); - - if (adc_watchdog_enabled()) { - restore_watchdog = 1; - adc_disable_watchdog_no_lock(); - } - - adc_configure(adc->channel); - - /* Clear EOC bit */ - STM32_ADC_SR &= ~BIT(1); - - /* Start conversion (Note: For now only confirmed on F4) */ -#if defined(CHIP_FAMILY_STM32F4) - STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART; -#else - STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; -#endif - - /* Wait for EOC bit set */ - deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; - value = ADC_READ_ERROR; - do { - if (adc_conversion_ended()) { - value = STM32_ADC_DR & ADC_READ_MAX; - break; - } - } while (!timestamp_expired(deadline, NULL)); - - if (restore_watchdog) - adc_enable_watchdog_no_lock(); - - mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; -} - -static void adc_init(void) -{ - /* - * Enable ADC clock. - * APB2 clock is 16MHz. ADC clock prescaler is /2. - * So the ADC clock is 8MHz. - */ - clock_enable_module(MODULE_ADC, 1); - - /* - * ADC clock is divided with respect to AHB, so no delay needed - * here. If ADC clock is the same as AHB, a read on ADC - * register is needed here. - */ - - if (!adc_powered()) { - /* Power on ADC module */ - STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; - - /* Reset calibration */ - STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL; - while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL) - ; - - /* A/D Calibrate */ - STM32_ADC_CR2 |= STM32_ADC_CR2_CAL; - while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL) - ; - } - - /* Set right alignment */ - STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN; - - /* Set sample time of all channels */ - STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME); - STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME); -} -DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c deleted file mode 120000 index 5e375b9dbf..0000000000 --- a/chip/stm32/adc-stm32f4.c +++ /dev/null @@ -1 +0,0 @@ -adc-stm32f3.c
\ No newline at end of file diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c deleted file mode 100644 index c1f1cfae4a..0000000000 --- a/chip/stm32/adc-stm32l.c +++ /dev/null @@ -1,170 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "common.h" -#include "console.h" -#include "clock.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ - -struct mutex adc_lock; - -static int restore_clock; - -static inline void adc_set_channel(int sample_id, int channel) -{ - uint32_t mask, val; - volatile uint32_t *sqr_reg; - int reg_id; - - reg_id = 5 - sample_id / 6; - - mask = 0x1f << ((sample_id % 6) * 5); - val = channel << ((sample_id % 6) * 5); - sqr_reg = &STM32_ADC_SQR(reg_id); - - *sqr_reg = (*sqr_reg & ~mask) | val; -} - -static void adc_configure(int ain_id) -{ - /* Set ADC channel */ - adc_set_channel(0, ain_id); - - /* Disable DMA */ - STM32_ADC_CR2 &= ~BIT(8); - - /* Disable scan mode */ - STM32_ADC_CR1 &= ~BIT(8); -} - -static void adc_configure_all(void) -{ - int i; - - /* Set ADC channels */ - STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20; - for (i = 0; i < ADC_CH_COUNT; ++i) - adc_set_channel(i, adc_channels[i].channel); - - /* Enable DMA */ - STM32_ADC_CR2 |= BIT(8); - - /* Enable scan mode */ - STM32_ADC_CR1 |= BIT(8); -} - -static inline int adc_powered(void) -{ - return STM32_ADC_SR & BIT(6); /* ADONS */ -} - -static void adc_enable_clock(void) -{ - STM32_RCC_APB2ENR |= BIT(9); - /* ADCCLK = HSI / 2 = 8MHz*/ - STM32_ADC_CCR |= BIT(16); -} - -static void adc_init(void) -{ - /* - * For STM32L, ADC clock source is HSI/2 = 8 MHz. HSI must be enabled - * for ADC. - * - * Note that we are not powering on ADC on EC initialization because - * STM32L ADC module requires HSI clock. Instead, ADC module is powered - * on/off in adc_prepare()/adc_release(). - */ - - /* Enable ADC clock. */ - adc_enable_clock(); - - if (!adc_powered()) - /* Power on ADC module */ - STM32_ADC_CR2 |= BIT(0); /* ADON */ - - /* Set right alignment */ - STM32_ADC_CR2 &= ~BIT(11); - - /* - * Set sample time of all channels to 16 cycles. - * Conversion takes (12+16)/8M = 3.34 us. - */ - STM32_ADC_SMPR1 = 0x24924892; - STM32_ADC_SMPR2 = 0x24924892; - STM32_ADC_SMPR3 = 0x24924892; -} - -static void adc_prepare(void) -{ - if (!adc_powered()) { - clock_enable_module(MODULE_ADC, 1); - adc_init(); - restore_clock = 1; - } -} - -static void adc_release(void) -{ - if (restore_clock) { - clock_enable_module(MODULE_ADC, 0); - restore_clock = 0; - } - - /* - * Power down the ADC. The ADC consumes a non-trivial amount of power, - * so it's wasteful to leave it on. - */ - if (adc_powered()) - STM32_ADC_CR2 = 0; -} - -static inline int adc_conversion_ended(void) -{ - return STM32_ADC_SR & BIT(1); -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - int value; - timestamp_t deadline; - - mutex_lock(&adc_lock); - - adc_prepare(); - - adc_configure(adc->channel); - - /* Clear EOC bit */ - STM32_ADC_SR &= ~BIT(1); - - /* Start conversion */ - STM32_ADC_CR2 |= BIT(30); /* SWSTART */ - - /* Wait for EOC bit set */ - deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; - value = ADC_READ_ERROR; - do { - if (adc_conversion_ended()) { - value = STM32_ADC_DR & ADC_READ_MAX; - break; - } - } while (!timestamp_expired(deadline, NULL)); - - adc_release(); - - mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; -} diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c deleted file mode 100644 index 8609d44f5d..0000000000 --- a/chip/stm32/adc-stm32l4.c +++ /dev/null @@ -1,234 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -struct mutex adc_lock; - -struct adc_profile_t { - /* Register values. */ - uint32_t cfgr1_reg; - uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ - uint32_t ier_reg; - /* DMA config. */ - const struct dma_option *dma_option; - /* Size of DMA buffer, in units of ADC_CH_COUNT. */ - int dma_buffer_size; -}; - -#ifdef CONFIG_ADC_PROFILE_SINGLE -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_12_5_CY -#endif -#endif - -#if defined(CHIP_FAMILY_STM32L4) -#define ADC_CALIBRATION_TIMEOUT_US 100000U -#define ADC_ENABLE_TIMEOUT_US 200000U -#define ADC_CONVERSION_TIMEOUT_US 200000U - -#define NUMBER_OF_ADC_CHANNEL 2 -uint8_t adc1_initialized; -#endif - -#ifdef CONFIG_ADC_PROFILE_FAST_CONTINUOUS - -#ifndef CONFIG_ADC_SAMPLE_TIME -#define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_1_5_CY -#endif - -static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, - STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, -}; - -static const struct adc_profile_t profile = { - /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | - STM32_ADC_CFGR1_DMACFG, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - /* Fire interrupt at end of sequence. */ - .ier_reg = STM32_ADC_IER_EOSEQIE, - .dma_option = &dma_continuous, - /* Double-buffer our samples. */ - .dma_buffer_size = 2, -}; -#endif - -static void adc_init(const struct adc_t *adc) -{ - /* - * If clock is already enabled, and ADC module is enabled - * then this is a warm reboot and ADC is already initialized. - */ - - if (STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADCEN && - (STM32_ADC1_CR & STM32_ADC1_CR_ADEN)) - return; - - /* Enable ADC clock */ - clock_enable_module(MODULE_ADC, 1); - - /* set ADC clock to 20MHz */ - STM32_ADC1_CCR &= ~0x003C0000; - STM32_ADC1_CCR |= 0x00080000; - - STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA; - STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB; - - /* Set ADC data resolution */ - STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_CONT; - /* Set ADC conversion data alignment */ - STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_ALIGN; - /* Set ADC delayed conversion mode */ - STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_AUTDLY; -} - -static void adc_configure(int ain_id, int ain_rank, - enum stm32_adc_smpr sample_rate) -{ - /* Select Sampling time and channel to convert */ - if (ain_id <= 10) { - STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3)); - STM32_ADC1_SMPR1 |= (sample_rate << ((ain_id - 1) * 3)); - } else { - STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3)); - STM32_ADC1_SMPR2 |= (sample_rate << ((ain_id - 11) * 3)); - } - - /* Setup Rank */ - STM32_ADC1_JSQR &= ~(0x03); - STM32_ADC1_JSQR |= NUMBER_OF_ADC_CHANNEL - 1; - - STM32_ADC1_JSQR &= ~(0x1F << (((ain_rank - 1) * 6) + 8)); - STM32_ADC1_JSQR |= (ain_id << (((ain_rank - 1) * 6) + 8)); - - /* Disable DMA */ - STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_DMAEN; -} - -int adc_read_channel(enum adc_channel ch) -{ - const struct adc_t *adc = adc_channels + ch; - - int value = 0; - uint32_t wait_loop_index; - - mutex_lock(&adc_lock); - - if (adc1_initialized == 0) { - adc_init(adc); - - /* Configure Injected Channel N */ - for (uint8_t i = 0; i < NUMBER_OF_ADC_CHANNEL; i++) { - const struct adc_t *adc = adc_channels + i; - - adc_configure(adc->channel, adc->rank, - adc->sample_rate); - } - - if ((STM32_ADC1_CR & STM32_ADC1_CR_ADEN) != - STM32_ADC1_CR_ADEN) { - /* Disable ADC deep power down (enabled by default after - * reset state) - */ - STM32_ADC1_CR &= ~STM32_ADC1_CR_DEEPPWD; - /* Enable ADC internal voltage regulator */ - STM32_ADC1_CR |= STM32_ADC1_CR_ADVREGEN; - } - - /* - * Delay for ADC internal voltage regulator stabilization. - * Compute number of CPU cycles to wait for, from delay in us. - * - * Note: Variable divided by 2 to compensate partially - * CPU processing cycles (depends on compilation optimization). - * - * Note: If system core clock frequency is below 200kHz, wait - * time is only a few CPU processing cycles. - */ - wait_loop_index = ((20 * (80000000 / (100000 * 2))) / 10); - while (wait_loop_index-- != 0) - ; - - /* Run ADC self calibration */ - STM32_ADC1_CR |= STM32_ADC1_CR_ADCAL; - - /* wait for the end of calibration */ - wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); - while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) { - if (wait_loop_index-- == 0) - break; - } - - /* Enable ADC */ - STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY; - STM32_ADC1_CR |= STM32_ADC1_CR_ADEN; - wait_loop_index = ((ADC_ENABLE_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); - while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) { - wait_loop_index--; - if (wait_loop_index == 0) - break; - } - - adc1_initialized = 1; - } - - /* Start injected conversion */ - STM32_ADC1_CR |= BIT(3); /* JADSTART */ - - /* Wait for end of injected conversion */ - wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); - while (!(STM32_ADC1_ISR & BIT(6))) { - if (wait_loop_index-- == 0) - break; - } - - /* Clear JEOS bit */ - STM32_ADC1_ISR |= BIT(6); - - /* read converted value */ - if (adc->rank == 1) - value = STM32_ADC1_JDR1; - if (adc->rank == 2) - value = STM32_ADC1_JDR2; - - mutex_unlock(&adc_lock); - - return value * adc->factor_mul / adc->factor_div + adc->shift; -} - -void adc_disable(void) -{ - /* Disable ADC */ - /* Do not Set ADDIS when ADC is disabled */ - adc1_initialized = 0; - - if (STM32_ADC1_CR & STM32_ADC1_CR_ADEN) - STM32_ADC1_CR |= STM32_ADC1_CR_ADDIS; - - /* - * Note that the ADC is not in OFF state immediately. - * Once the ADC is effectively put into OFF state, - * STM32_ADC_CR_ADDIS bit will be cleared by hardware. - */ -} diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h deleted file mode 100644 index 7e3c688c14..0000000000 --- a/chip/stm32/adc_chip.h +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* STM32-specific ADC module for Chrome EC */ - -#ifndef __CROS_EC_ADC_CHIP_H -#define __CROS_EC_ADC_CHIP_H - -#ifdef CHIP_FAMILY_STM32L4 -enum stm32_adc_smpr { - STM32_ADC_SMPR_DEFAULT = 0, - STM32_ADC_SMPR_2_5_CY, - STM32_ADC_SMPR_6_5_CY, - STM32_ADC_SMPR_12_5_CY, - STM32_ADC_SMPR_24_5_CY, - STM32_ADC_SMPR_47_5_CY, - STM32_ADC_SMPR_92_5_CY, - STM32_ADC_SMPR_247_5_CY, - STM32_ADC_SMPR_640_5_CY, - STM32_ADC_SMPR_COUNT, -}; -#else -enum stm32_adc_smpr { - STM32_ADC_SMPR_DEFAULT = 0, - STM32_ADC_SMPR_1_5_CY, - STM32_ADC_SMPR_7_5_CY, - STM32_ADC_SMPR_13_5_CY, - STM32_ADC_SMPR_28_5_CY, - STM32_ADC_SMPR_41_5_CY, - STM32_ADC_SMPR_55_5_CY, - STM32_ADC_SMPR_71_5_CY, - STM32_ADC_SMPR_239_5_CY, - STM32_ADC_SMPR_COUNT, -}; -#endif - -/* Data structure to define ADC channels. */ -struct adc_t { - const char *name; - int factor_mul; - int factor_div; - int shift; - int channel; -#ifdef CHIP_FAMILY_STM32L4 - int rank; -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */ -#endif -}; - -/* Disable ADC module when we don't need it anymore. */ -void adc_disable(void); - -/* Minimum and maximum values returned by adc_read_channel(). */ -#define ADC_READ_MIN 0 -#define ADC_READ_MAX 4095 - -/* Just plain id mapping for code readability */ -#define STM32_AIN(x) (x) - -/* Add for ADCs with RANK */ -#define STM32_RANK(x) (x) - -#endif /* __CROS_EC_ADC_CHIP_H */ diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c deleted file mode 100644 index 8c85366857..0000000000 --- a/chip/stm32/bkpdata.c +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <assert.h> - -#include "bkpdata.h" -#include "registers.h" -#include "system.h" /* enum system_bbram_idx */ -#include "task.h" - -uint16_t bkpdata_read(enum bkpdata_index index) -{ - if (index < 0 || index >= STM32_BKP_ENTRIES) - return 0; - - if (index & 1) - return STM32_BKP_DATA(index >> 1) >> 16; - else - return STM32_BKP_DATA(index >> 1) & 0xFFFF; -} - -int bkpdata_write(enum bkpdata_index index, uint16_t value) -{ - static struct mutex bkpdata_write_mutex; - int use_mutex = !in_interrupt_context(); - - if (index < 0 || index >= STM32_BKP_ENTRIES) - return EC_ERROR_INVAL; - - /* - * Two entries share a single 32-bit register, lock mutex to prevent - * read/mask/write races. - */ - if (use_mutex) - mutex_lock(&bkpdata_write_mutex); - if (index & 1) { - uint32_t val = STM32_BKP_DATA(index >> 1); - val = (val & 0x0000FFFF) | (value << 16); - STM32_BKP_DATA(index >> 1) = val; - } else { - uint32_t val = STM32_BKP_DATA(index >> 1); - val = (val & 0xFFFF0000) | value; - STM32_BKP_DATA(index >> 1) = val; - } - if (use_mutex) - mutex_unlock(&bkpdata_write_mutex); - - return EC_SUCCESS; -} - -int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb) -{ - *msb = 0; - -#ifdef CONFIG_USB_PD_DUAL_ROLE - if (idx == SYSTEM_BBRAM_IDX_PD0) - return BKPDATA_INDEX_PD0; - if (idx == SYSTEM_BBRAM_IDX_PD1) - return BKPDATA_INDEX_PD1; - if (idx == SYSTEM_BBRAM_IDX_PD2) - return BKPDATA_INDEX_PD2; -#endif - return -1; -} - -uint32_t bkpdata_read_reset_flags() -{ - uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS); - - flags |= bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS_2) << 16; - - return flags; -} - -__overridable -void bkpdata_write_reset_flags(uint32_t save_flags) -{ - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff); - bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16); -} diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h deleted file mode 100644 index 14bd3517cc..0000000000 --- a/chip/stm32/bkpdata.h +++ /dev/null @@ -1,61 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Backup data functionality */ - -#ifndef __CROS_EC_BKPDATA_H -#define __CROS_EC_BKPDATA_H - -#include "common.h" -#include "registers.h" -#include "system.h" /* enum system_bbram_idx */ - -/* We use 16-bit BKP / BBRAM entries. */ -#define STM32_BKP_ENTRIES (STM32_BKP_BYTES / 2) - -enum bkpdata_index { - BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ - BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ - BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ -#ifdef CONFIG_SOFTWARE_PANIC - BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */ - BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */ - BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */ -#endif -#ifdef CONFIG_USB_PD_DUAL_ROLE - BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */ - BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */ - BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */ -#endif -#ifdef CONFIG_SOFTWARE_PANIC - /** - * Saving the panic flags in case that AP thinks the panic is new - * after a hard reset. - */ - BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */ -#endif - BKPDATA_COUNT -}; -BUILD_ASSERT(STM32_BKP_ENTRIES >= BKPDATA_COUNT); - -/** - * Read backup register at specified index. - * - * @return The value of the register or 0 if invalid index. - */ -uint16_t bkpdata_read(enum bkpdata_index index); - -/** - * Write hibernate register at specified index. - * - * @return nonzero if error. - */ -int bkpdata_write(enum bkpdata_index index, uint16_t value); - -int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb); -uint32_t bkpdata_read_reset_flags(void); -void bkpdata_write_reset_flags(uint32_t save_flags); - -#endif /* __CROS_EC_BKPDATA_H */ diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk deleted file mode 100644 index 6817a3647d..0000000000 --- a/chip/stm32/build.mk +++ /dev/null @@ -1,106 +0,0 @@ -# -*- makefile -*- -# Copyright 2013 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# STM32 chip specific files build -# - -ifeq ($(CHIP_FAMILY),stm32f0) -# STM32F0xx sub-family has a Cortex-M0 ARM core -CORE:=cortex-m0 -# Force ARMv6-M ISA used by the Cortex-M0 -# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M -# without "svc" instruction, but that was short-lived. ARMv6S-M was the option -# with "svc". GCC kept that naming scheme even though the distinction is long -# gone. -CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0 -else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \ -stm32g4)) -# STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 -else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7)) -# STM32FH7xx family has a Cortex-M7 ARM core -CORE:=cortex-m -# Allow the full Cortex-M4 instruction set (identical to M7) -CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 -else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5)) -# STM32FL5xx family has a Cortex-M33 ARM core -CORE:=cortex-m -# Allow the full Cortex-M33 instruction set -CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33 -else -# other STM32 SoCs have a Cortex-M3 ARM core -CORE:=cortex-m -# Force Cortex-M3 subset of instructions -CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3 -endif - -# Select between 16-bit and 32-bit timer for clock source -TIMER_TYPE=$(if $(CONFIG_STM_HWTIMER32),32,) -DMA_TYPE=$(if $(CHIP_FAMILY_STM32F4)$(CHIP_FAMILY_STM32H7),-stm32f4,) -SPI_TYPE=$(if $(CHIP_FAMILY_STM32H7),-stm32h7,) - -chip-$(CONFIG_DMA)+=dma$(DMA_TYPE).o -chip-$(CONFIG_COMMON_RUNTIME)+=bkpdata.o system.o -chip-y+=clock-$(CHIP_FAMILY).o -ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f0 stm32f3 stm32f4)) -chip-y+=clock-f.o -endif -chip-$(CONFIG_SPI)+=spi.o -chip-$(CONFIG_SPI_CONTROLLER)+=spi_master$(SPI_TYPE).o -chip-$(CONFIG_COMMON_GPIO)+=gpio.o gpio-$(CHIP_FAMILY).o -chip-$(CONFIG_COMMON_TIMER)+=hwtimer$(TIMER_TYPE).o -chip-$(CONFIG_I2C)+=i2c-$(CHIP_FAMILY).o -chip-$(CONFIG_ITE_FLASH_SUPPORT)+=i2c_ite_flash_support.o -chip-$(CONFIG_STREAM_USART)+=usart.o usart-$(CHIP_FAMILY).o -chip-$(CONFIG_STREAM_USART)+=usart_rx_interrupt-$(CHIP_FAMILY).o -chip-$(CONFIG_STREAM_USART)+=usart_tx_interrupt.o -chip-$(CONFIG_STREAM_USART)+=usart_rx_dma.o usart_tx_dma.o -chip-$(CONFIG_USART_HOST_COMMAND)+=usart_host_command.o -chip-$(CONFIG_CMD_USART_INFO)+=usart_info_command.o -chip-$(HAS_TASK_CONSOLE)+=host_command_common.o -chip-$(CONFIG_WATCHDOG)+=watchdog.o -chip-$(HAS_TASK_CONSOLE)+=uart.o -ifndef CONFIG_KEYBOARD_NOT_RAW -chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o -endif -chip-$(HAS_TASK_POWERLED)+=power_led.o -ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32g4 stm32l4 stm32l5)) -# STM32G4, STM32L4 and STM32L5 use the same flash IP block -chip-y+=flash-stm32g4-l4.o -else -chip-$(CONFIG_FLASH_PHYSICAL)+=flash-$(CHIP_FAMILY).o -endif -ifdef CONFIG_FLASH_PHYSICAL -chip-$(CHIP_FAMILY_STM32F0)+=flash-f.o -chip-$(CHIP_FAMILY_STM32F3)+=flash-f.o -chip-$(CHIP_FAMILY_STM32F4)+=flash-f.o -endif -chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o -chip-$(CONFIG_STM32_CHARGER_DETECT)+=charger_detect.o -chip-$(CONFIG_DEBUG_PRINTF)+=debug_printf.o -chip-$(CONFIG_OTP)+=otp-$(CHIP_FAMILY).o -chip-$(CONFIG_PWM)+=pwm.o -chip-$(CONFIG_RNG)+=trng.o - -ifeq ($(CHIP_FAMILY),stm32f4) -chip-$(CONFIG_USB)+=usb_dwc.o usb_endpoints.o -chip-$(CONFIG_USB_CONSOLE)+=usb_dwc_console.o -chip-$(CONFIG_USB_POWER)+=usb_power.o -chip-$(CONFIG_STREAM_USB)+=usb_dwc_stream.o -else -chip-$(CONFIG_STREAM_USB)+=usb-stream.o -chip-$(CONFIG_USB)+=usb.o usb-$(CHIP_FAMILY).o usb_endpoints.o -chip-$(CONFIG_USB_CONSOLE)+=usb_console.o -chip-$(CONFIG_USB_GPIO)+=usb_gpio.o -chip-$(CONFIG_USB_HID)+=usb_hid.o -chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o -chip-$(CONFIG_USB_HID_TOUCHPAD)+=usb_hid_touchpad.o -chip-$(CONFIG_USB_ISOCHRONOUS)+=usb_isochronous.o -chip-$(CONFIG_USB_PD_TCPC)+=usb_pd_phy.o -chip-$(CONFIG_USB_SPI)+=usb_spi.o -endif -chip-$(CONFIG_USB_PD_TCPM_STM32GX)+=ucpd-stm32gx.o diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c deleted file mode 100644 index b32b9f3ac0..0000000000 --- a/chip/stm32/charger_detect.c +++ /dev/null @@ -1,55 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Detect what adapter is connected */ - -#include "charge_manager.h" -#include "hooks.h" -#include "registers.h" -#include "timer.h" - -static void enable_usb(void) -{ - /* Enable USB device clock. */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; -} -DECLARE_HOOK(HOOK_INIT, enable_usb, HOOK_PRIO_DEFAULT); - -static void disable_usb(void) -{ - /* Disable USB device clock. */ - STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; -} -DECLARE_HOOK(HOOK_SYSJUMP, disable_usb, HOOK_PRIO_DEFAULT); - -static uint16_t detect_type(uint16_t det_type) -{ - STM32_USB_BCDR &= 0; - usleep(1); - STM32_USB_BCDR |= (STM32_USB_BCDR_BCDEN | det_type); - usleep(1); - STM32_USB_BCDR &= ~(STM32_USB_BCDR_BCDEN | det_type); - return STM32_USB_BCDR; -} - - -int charger_detect_get_device_type(void) -{ - uint16_t pdet_result; - - if (!(detect_type(STM32_USB_BCDR_DCDEN) & STM32_USB_BCDR_DCDET)) - return CHARGE_SUPPLIER_PD; - - pdet_result = detect_type(STM32_USB_BCDR_PDEN); - /* TODO: add support for detecting proprietary chargers. */ - if (pdet_result & STM32_USB_BCDR_PDET) { - if (detect_type(STM32_USB_BCDR_SDEN) & STM32_USB_BCDR_SDET) - return CHARGE_SUPPLIER_BC12_DCP; - else - return CHARGE_SUPPLIER_BC12_CDP; - } else if (pdet_result & STM32_USB_BCDR_PS2DET) - return CHARGE_SUPPLIER_PROPRIETARY; - else - return CHARGE_SUPPLIER_BC12_SDP; -} diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c deleted file mode 100644 index 1a77d8ad60..0000000000 --- a/chip/stm32/clock-f.c +++ /dev/null @@ -1,507 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "host_command.h" -#include "hwtimer.h" -#include "registers.h" -#include "rtc.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -/* Convert decimal to BCD */ -static uint8_t u8_to_bcd(uint8_t val) -{ - /* Fast division by 10 (when lacking HW div) */ - uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19; - uint32_t rem = val - quot * 10; - - return rem | (quot << 4); -} - -/* Convert between RTC regs in BCD and seconds */ -static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) -{ - uint32_t sec; - - /* convert the hours field */ - sec = (((rtc_tr & 0x300000) >> 20) * 10 + - ((rtc_tr & 0xf0000) >> 16)) * 3600; - /* convert the minutes field */ - sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60; - /* convert the seconds field */ - sec += ((rtc_tr & 0x70) >> 4) * 10 + (rtc_tr & 0xf); - return sec; -} - -static uint32_t sec_to_rtc_tr(uint32_t sec) -{ - uint32_t rtc_tr; - uint8_t hour; - uint8_t min; - - sec %= SECS_PER_DAY; - /* convert the hours field */ - hour = sec / 3600; - rtc_tr = u8_to_bcd(hour) << 16; - /* convert the minutes field */ - sec -= hour * 3600; - min = sec / 60; - rtc_tr |= u8_to_bcd(min) << 8; - /* convert the seconds field */ - sec -= min * 60; - rtc_tr |= u8_to_bcd(sec); - - return rtc_tr; -} - -/* Register setup before RTC alarm is allowed for update */ -static void pre_work_set_rtc_alarm(void) -{ - rtc_unlock_regs(); - - /* Make sure alarm is disabled */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF)) - ; - STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; -} - -/* Register setup after RTC alarm is updated */ -static void post_work_set_rtc_alarm(void) -{ - STM32_EXTI_PR = EXTI_RTC_ALR_EVENT; - - /* Enable alarm and alarm interrupt */ - STM32_EXTI_IMR |= EXTI_RTC_ALR_EVENT; - STM32_RTC_CR |= STM32_RTC_CR_ALRAE; - - rtc_lock_regs(); -} - -#ifdef CONFIG_HOSTCMD_RTC -static struct wake_time host_wake_time; - -int is_host_wake_alarm_expired(timestamp_t ts) -{ - return host_wake_time.ts.val && - timestamp_expired(host_wake_time.ts, &ts); -} - -void restore_host_wake_alarm(void) -{ - if (!host_wake_time.ts.val) - return; - - pre_work_set_rtc_alarm(); - - /* Set alarm time */ - STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar; - - post_work_set_rtc_alarm(); -} - -static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) -{ - struct calendar_date time; - uint32_t sec; - - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); - time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); - - sec = date_to_sec(time); - - return sec; -} - -static uint32_t sec_to_rtc_dr(uint32_t sec) -{ - struct calendar_date time; - uint32_t rtc_dr; - - time = sec_to_date(sec); - - rtc_dr = u8_to_bcd(time.year) << 16; - rtc_dr |= u8_to_bcd(time.month) << 8; - rtc_dr |= u8_to_bcd(time.day); - - return rtc_dr; -} -#endif - -uint32_t rtc_to_sec(const struct rtc_time_reg *rtc) -{ - uint32_t sec = 0; -#ifdef CONFIG_HOSTCMD_RTC - sec = rtc_dr_to_sec(rtc->rtc_dr); -#endif - return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) + - rtc_tr_to_sec(rtc->rtc_tr); -} - -void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc) -{ - rtc->rtc_dr = 0; -#ifdef CONFIG_HOSTCMD_RTC - rtc->rtc_dr = sec_to_rtc_dr(sec); -#endif - rtc->rtc_tr = sec_to_rtc_tr(sec); - rtc->rtc_ssr = 0; -} - -/* Return sub-10-sec time diff between two rtc readings - * - * Note: this function assumes rtc0 was sampled before rtc1. - * Additionally, this function only looks at the difference mod 10 - * seconds. - */ -uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, - const struct rtc_time_reg *rtc1) -{ - uint32_t rtc0_val, rtc1_val, diff; - - rtc0_val = (rtc0->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc0->rtc_ssr); - rtc1_val = (rtc1->rtc_tr & 0xF) * SECOND + rtcss_to_us(rtc1->rtc_ssr); - diff = rtc1_val; - if (rtc1_val < rtc0_val) { - /* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add - * 10 seconds to get the correct value - */ - diff += 10 * SECOND; - } - diff -= rtc0_val; - return diff; -} - -void rtc_read(struct rtc_time_reg *rtc) -{ - /* - * Read current time synchronously. Each register must be read - * twice with identical values because glitches may occur for reads - * close to the RTCCLK edge. - */ - do { - rtc->rtc_dr = STM32_RTC_DR; - - do { - rtc->rtc_tr = STM32_RTC_TR; - - do { - rtc->rtc_ssr = STM32_RTC_SSR; - } while (rtc->rtc_ssr != STM32_RTC_SSR); - - } while (rtc->rtc_tr != STM32_RTC_TR); - - } while (rtc->rtc_dr != STM32_RTC_DR); -} - -void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, - struct rtc_time_reg *rtc, uint8_t save_alarm) -{ - uint32_t alarm_sec = 0; - uint32_t alarm_us = 0; - - if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) { - reset_rtc_alarm(rtc); - return; - } - - /* Alarm timeout must be within 1 day (86400 seconds) */ - ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY); - - pre_work_set_rtc_alarm(); - rtc_read(rtc); - - /* Calculate alarm time */ - alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s; - - if (delay_us) { - alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us; - alarm_sec = alarm_sec + alarm_us / SECOND; - alarm_us = alarm_us % SECOND; - } - - /* - * If seconds is greater than 1 day, subtract by 1 day to deal with - * 24-hour rollover. - */ - if (alarm_sec >= SECS_PER_DAY) - alarm_sec -= SECS_PER_DAY; - - /* - * Set alarm time in seconds and check for match on - * hours, minutes, and seconds. - */ - STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000; - - /* - * Set alarm time in subseconds and check for match on subseconds. - * If the caller doesn't specify subsecond delay (e.g. host command), - * just align the alarm time to second. - */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; - -#ifdef CONFIG_HOSTCMD_RTC - /* - * If alarm is set by the host, preserve the wake time timestamp - * and alarm registers. - */ - if (save_alarm) { - host_wake_time.ts.val = delay_s * SECOND + get_time().val; - host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR; - } -#endif - post_work_set_rtc_alarm(); -} - -uint32_t get_rtc_alarm(void) -{ - struct rtc_time_reg now; - uint32_t now_sec; - uint32_t alarm_sec; - - if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE)) - return 0; - - rtc_read(&now); - - now_sec = rtc_tr_to_sec(now.rtc_tr); - alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff); - - return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) + - (alarm_sec - now_sec); -} - -void reset_rtc_alarm(struct rtc_time_reg *rtc) -{ - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; - - /* Disable RTC alarm interrupt */ - STM32_EXTI_IMR &= ~EXTI_RTC_ALR_EVENT; - STM32_EXTI_PR = EXTI_RTC_ALR_EVENT; - - /* Clear the pending RTC alarm IRQ in NVIC */ - task_clear_pending_irq(STM32_IRQ_RTC_ALARM); - - /* Read current time */ - rtc_read(rtc); - - rtc_lock_regs(); -} - -#ifdef CONFIG_HOSTCMD_RTC -static void set_rtc_host_event(void) -{ - host_set_single_event(EC_HOST_EVENT_RTC); -} -DECLARE_DEFERRED(set_rtc_host_event); -#endif - -test_mockable -void __rtc_alarm_irq(void) -{ - struct rtc_time_reg rtc; - reset_rtc_alarm(&rtc); - -#ifdef CONFIG_HOSTCMD_RTC - /* Wake up the host if there is a saved rtc wake alarm. */ - if (host_wake_time.ts.val) { - host_wake_time.ts.val = 0; - hook_call_deferred(&set_rtc_host_event_data, 0); - } -#endif -} -DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); - -__attribute__((weak)) -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_init(void) -{ - /* - * The initial state : - * SYSCLK from HSI (=8MHz), no divider on AHB, APB1, APB2 - * PLL unlocked, RTC enabled on LSE - */ - - /* - * put 1 Wait-State for flash access to ensure proper reads at 48Mhz - * and enable prefetch buffer. - */ - STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; - -#ifdef CHIP_FAMILY_STM32F4 - /* Enable data and instruction cache. */ - STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN; -#endif - - config_hispeed_clock(); - - rtc_init(); -} - -#ifdef CHIP_FAMILY_STM32F4 -void reset_flash_cache(void) -{ - /* Disable data and instruction cache. */ - STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN); - - /* Reset data and instruction cache */ - STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST; -} -DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT); -#endif - -/*****************************************************************************/ -/* Console commands */ - -void print_system_rtc(enum console_channel ch) -{ - uint32_t sec; - struct rtc_time_reg rtc; - - rtc_read(&rtc); - sec = rtc_to_sec(&rtc); - - cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec); -} - -#ifdef CONFIG_CMD_RTC -static int command_system_rtc(int argc, char **argv) -{ - char *e; - uint32_t t; - - if (argc == 3 && !strcasecmp(argv[1], "set")) { - t = strtoi(argv[2], &e, 0); - if (*e) - return EC_ERROR_PARAM2; - rtc_set(t); - } else if (argc > 1) - return EC_ERROR_INVAL; - - print_system_rtc(CC_COMMAND); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, - "[set <seconds>]", - "Get/set real-time clock"); - -#ifdef CONFIG_CMD_RTC_ALARM -static int command_rtc_alarm_test(int argc, char **argv) -{ - int s = 1, us = 0; - struct rtc_time_reg rtc; - char *e; - - ccprintf("Setting RTC alarm\n"); - - if (argc > 1) { - s = strtoi(argv[1], &e, 10); - if (*e) - return EC_ERROR_PARAM1; - - } - if (argc > 2) { - us = strtoi(argv[2], &e, 10); - if (*e) - return EC_ERROR_PARAM2; - } - - set_rtc_alarm(s, us, &rtc, 0); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test, - "[seconds [microseconds]]", - "Test alarm"); -#endif /* CONFIG_CMD_RTC_ALARM */ -#endif /* CONFIG_CMD_RTC */ - -/*****************************************************************************/ -/* Host commands */ - -#ifdef CONFIG_HOSTCMD_RTC -static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args) -{ - struct ec_response_rtc *r = args->response; - struct rtc_time_reg rtc; - - rtc_read(&rtc); - r->time = rtc_to_sec(&rtc); - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, - system_rtc_get_value, - EC_VER_MASK(0)); - -static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) -{ - const struct ec_params_rtc *p = args->params; - - rtc_set(p->time); - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, - system_rtc_set_value, - EC_VER_MASK(0)); - -static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) -{ - struct rtc_time_reg rtc; - const struct ec_params_rtc *p = args->params; - - /* Alarm timeout must be within 1 day (86400 seconds) */ - if (p->time >= SECS_PER_DAY) - return EC_RES_INVALID_PARAM; - - set_rtc_alarm(p->time, 0, &rtc, 1); - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, - system_rtc_set_alarm, - EC_VER_MASK(0)); - -static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) -{ - struct ec_response_rtc *r = args->response; - - r->time = get_rtc_alarm(); - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, - system_rtc_get_alarm, - EC_VER_MASK(0)); - -#endif /* CONFIG_HOSTCMD_RTC */ diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h deleted file mode 100644 index 4662b043cb..0000000000 --- a/chip/stm32/clock-f.h +++ /dev/null @@ -1,103 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#ifndef __CROS_EC_CLOCK_F_H -#define __CROS_EC_CLOCK_F_H - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Lock and unlock RTC write access */ -static inline void rtc_lock_regs(void) -{ - STM32_RTC_WPR = 0xff; -} -static inline void rtc_unlock_regs(void) -{ - STM32_RTC_WPR = 0xca; - STM32_RTC_WPR = 0x53; -} - -struct rtc_time_reg { - uint32_t rtc_ssr; /* subseconds */ - uint32_t rtc_tr; /* hours, minutes, seconds */ - uint32_t rtc_dr; /* years, months, dates, week days */ -}; - -/* Save the RTC alarm wake time */ -struct wake_time { - timestamp_t ts; - uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */ -}; - -/* Convert between RTC regs in BCD and seconds */ -uint32_t rtc_to_sec(const struct rtc_time_reg *rtc); - -/* Convert between seconds and RTC regs */ -void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc); - -/* Calculate microseconds from rtc sub-second register. */ -int32_t rtcss_to_us(uint32_t rtcss); - -/* Calculate rtc sub-second register value from microseconds. */ -uint32_t us_to_rtcss(int32_t us); - -/* Return sub-10-sec time diff between two rtc readings */ -uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, - const struct rtc_time_reg *rtc1); - -/* Read RTC values */ -void rtc_read(struct rtc_time_reg *rtc); - -/* Set RTC value */ -void rtc_set(uint32_t sec); - -/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */ -void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, - struct rtc_time_reg *rtc, uint8_t save_alarm); - -/* Clear RTC wakeup */ -void reset_rtc_alarm(struct rtc_time_reg *rtc); - -/* - * Return the remaining seconds before the RTC alarm goes off. - * Sub-seconds are ignored. Returns 0 if alarm is not set. - */ -uint32_t get_rtc_alarm(void); - -/* RTC init */ -void rtc_init(void); - -/* Init clock blocks and functionality */ -void clock_init(void); - -/* Init high speed clock config */ -void config_hispeed_clock(void); - -/* Get timer clock frequency (for STM32 only) */ -int clock_get_timer_freq(void); - -/* - * Return 1 if host_wake_time is nonzero and the saved host_wake_time - * is expired at a given time, ts. - */ -int is_host_wake_alarm_expired(timestamp_t ts); - -/* Set RTC wakeup based on the value saved in host_wake_time */ -void restore_host_wake_alarm(void); - -#endif /* __CROS_EC_CLOCK_F_H */ diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h deleted file mode 100644 index d237b84580..0000000000 --- a/chip/stm32/clock-l4.h +++ /dev/null @@ -1,110 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#ifndef __CROS_EC_CLOCK_L4_H -#define __CROS_EC_CLOCK_L4_H - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define STM32L4_RTC_REQ 1000000 -#define STM32L4_LSI_CLOCK 32000 - -/* Lock and unlock RTC write access */ -static inline void rtc_lock_regs(void) -{ - STM32_RTC_WPR = 0xff; -} -static inline void rtc_unlock_regs(void) -{ - STM32_RTC_WPR = 0xca; - STM32_RTC_WPR = 0x53; -} - -struct rtc_time_reg { - uint32_t rtc_ssr; /* subseconds */ - uint32_t rtc_tr; /* hours, minutes, seconds */ - uint32_t rtc_dr; /* years, months, dates, week days */ -}; - -/* Save the RTC alarm wake time */ -struct wake_time { - timestamp_t ts; - uint32_t rtc_alrmar; /* the value of register STM32_RTC_ALRMAR */ -}; - -/* Convert between RTC regs in BCD and seconds */ -uint32_t rtc_to_sec(const struct rtc_time_reg *rtc); - -/* Convert between seconds and RTC regs */ -void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc); - -/* Calculate microseconds from rtc sub-second register. */ -uint32_t rtcss_to_us(uint32_t rtcss); - -/* Calculate rtc sub-second register value from microseconds. */ -uint32_t us_to_rtcss(uint32_t us); - -/* Return sub-10-sec time diff between two rtc readings */ -uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, - const struct rtc_time_reg *rtc1); - -/* Read RTC values */ -void rtc_read(struct rtc_time_reg *rtc); - -/* Set RTC value */ -void rtc_set(uint32_t sec); - -/* Set RTC wakeup, save alarm wakeup time when save_alarm != 0 */ -void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, - struct rtc_time_reg *rtc, uint8_t save_alarm); - -/* Clear RTC wakeup */ -void reset_rtc_alarm(struct rtc_time_reg *rtc); - -/* - * Return the remaining seconds before the RTC alarm goes off. - * Sub-seconds are ignored. Returns 0 if alarm is not set. - */ -uint32_t get_rtc_alarm(void); - -/* RTC init */ -void rtc_init(void); - -/* Init clock blocks and functionality */ -void clock_init(void); - -/* Init high speed clock config */ -void config_hispeed_clock(void); - -/* Get timer clock frequency (for STM32 only) */ -int clock_get_timer_freq(void); - -/* - * Return 1 if host_wake_time is nonzero and the saved host_wake_time - * is expired at a given time, ts. - */ -bool is_host_wake_alarm_expired(timestamp_t ts); - -/* Set RTC wakeup based on the value saved in host_wake_time */ -void restore_host_wake_alarm(void); - -#ifdef CONFIG_LOW_POWER_IDLE -void low_power_init(void); -#endif - -#endif /* __CROS_EC_CLOCK_L4_H */ diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c deleted file mode 100644 index 0f63bdd394..0000000000 --- a/chip/stm32/clock-stm32f0.c +++ /dev/null @@ -1,503 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "uart.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -/* use 48Mhz USB-synchronized High-speed oscillator */ -#define HSI48_CLOCK 48000000 - -/* use PLL at 38.4MHz as system clock. */ -#define PLL_CLOCK 38400000 - -/* Low power idle statistics */ -#ifdef CONFIG_LOW_POWER_IDLE -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t idle_dsleep_time_us; -static int dsleep_recovery_margin_us = 1000000; - -/* - * minimum delay to enter stop mode - * - * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low - * power mode is 5 us + PLL locking time is 200us. - * - * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm - * in the past, it will never wake up and cause a watchdog. - * For STM32F3, we are using HSE, which requires additional time to start up. - * Therefore, the latency for STM32F3 is set longer. - * - * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is - * called and the host alarm is actually restored. In practice, the max latency - * is measured as ~600us. 1000us should be conservative enough to guarantee - * we won't miss the host alarm. - */ -#ifdef CHIP_VARIANT_STM32F373 -#define STOP_MODE_LATENCY 500 /* us */ -#elif defined(CHIP_VARIANT_STM32F05X) -#define STOP_MODE_LATENCY 300 /* us */ -#elif (CPU_CLOCK == PLL_CLOCK) -#define STOP_MODE_LATENCY 300 /* us */ -#else -#define STOP_MODE_LATENCY 50 /* us */ -#endif -#define SET_RTC_MATCH_DELAY 200 /* us */ - -#ifdef CONFIG_HOSTCMD_RTC -#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */ -#endif - -#endif /* CONFIG_LOW_POWER_IDLE */ - -/* - * RTC clock frequency (By default connected to LSI clock) - * - * The LSI on any given chip can be between 30 kHz to 60 kHz. - * Without calibration, LSI frequency may be off by as much as 50%. - * - * Set synchronous clock freq to (RTC clock source / 2) to maximize - * subsecond resolution. Set asynchronous clock to 1 Hz. - */ - -#define RTC_PREDIV_A 1 -#ifdef CONFIG_STM32_CLOCK_LSE -#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */ -/* GCD(RTC_FREQ, 1000000) */ -#define RTC_GCD 64 -#else /* LSI clock, 40kHz-ish */ -#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */ -/* GCD(RTC_FREQ, 1000000) */ -#define RTC_GCD 20000 -#endif -#define RTC_PREDIV_S (RTC_FREQ - 1) - -/* - * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms - * for conversion calculations to fit in 32 bits. - */ -#define US_GCD (1000000 / RTC_GCD) -#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD) - -int32_t rtcss_to_us(uint32_t rtcss) -{ - return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD; -} - -uint32_t us_to_rtcss(int32_t us) -{ - return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD; -} - -void config_hispeed_clock(void) -{ -#ifdef CHIP_FAMILY_STM32F3 - /* Ensure that HSE is ON */ - wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17)); - - /* - * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK - * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz - * ADCCLK = PCLK / 6 = 4MHz - * USB uses SYSCLK = 48MHz - */ - STM32_RCC_CFGR = 0x0041a400; - - /* Enable the PLL */ - STM32_RCC_CR |= 0x01000000; - - /* Wait until the PLL is ready */ - while (!(STM32_RCC_CR & 0x02000000)) - ; - - /* Switch SYSCLK to PLL */ - STM32_RCC_CFGR |= 0x2; - - /* Wait until the PLL is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0x8) - ; -/* F03X and F05X and F070 don't have HSI48 */ -#elif defined(CHIP_VARIANT_STM32F03X) || \ -defined(CHIP_VARIANT_STM32F05X) || \ -defined(CHIP_VARIANT_STM32F070) - /* If PLL is the clock source, PLL has already been set up. */ - if ((STM32_RCC_CFGR & 0xc) == 0x8) - return; - - /* Ensure that HSI is ON */ - wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1)); - - /* - * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz - * therefore PCLK = FCLK = SYSCLK = 48MHz - */ - /* Switch the PLL source to HSI/2 */ - STM32_RCC_CFGR &= ~(0x00018000); - - /* - * Specify HSI/2 clock as input clock to PLL and set PLL (*12). - */ - STM32_RCC_CFGR |= 0x00280000; - - /* Enable the PLL. */ - STM32_RCC_CR |= 0x01000000; - - /* Wait until PLL is ready. */ - while (!(STM32_RCC_CR & 0x02000000)) - ; - - /* Switch SYSCLK to PLL. */ - STM32_RCC_CFGR |= 0x2; - - /* wait until the PLL is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0x8) - ; -#else - /* Ensure that HSI48 is ON */ - wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17)); - -#if (CPU_CLOCK == HSI48_CLOCK) - /* - * HSI48 = 48MHz, no prescaler, no MCO, no PLL - * therefore PCLK = FCLK = SYSCLK = 48MHz - * USB uses HSI48 = 48MHz - */ - -#ifdef CONFIG_USB - /* - * Configure and enable Clock Recovery System - * - * Since we are running from the internal RC HSI48 clock, the CSR - * is needed to guarantee an accurate 48MHz clock for USB. - * - * The default values configure the CRS to use the periodic USB SOF - * as the SYNC signal for calibrating the HSI48. - * - */ - - /* Enable Clock Recovery System */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS; - - /* Enable automatic trimming */ - STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN; - - /* Enable oscillator clock for the frequency error counter */ - STM32_CRS_CR |= STM32_CRS_CR_CEN; -#endif - - /* switch SYSCLK to HSI48 */ - STM32_RCC_CFGR = 0x00000003; - - /* wait until the HSI48 is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0xc) - ; - -#elif (CPU_CLOCK == PLL_CLOCK) - /* - * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK - * therefore PCLK = FCLK = SYSCLK = 38.4MHz - * USB uses HSI48 = 48MHz - */ - - /* If PLL is the clock source, PLL has already been set up. */ - if ((STM32_RCC_CFGR & 0xc) == 0x8) - return; - - /* - * Specify HSI48 clock as input clock to PLL and set PLL multiplier - * and divider. - */ - STM32_RCC_CFGR = 0x00098000; - STM32_RCC_CFGR2 = 0x4; - - /* Enable the PLL. */ - STM32_RCC_CR |= 0x01000000; - - /* Wait until PLL is ready. */ - while (!(STM32_RCC_CR & 0x02000000)) - ; - - /* Switch SYSCLK to PLL. */ - STM32_RCC_CFGR |= 0x2; - - /* wait until the PLL is the clock source */ - while ((STM32_RCC_CFGR & 0xc) != 0x8) - ; - -#else -#error "CPU_CLOCK must be either 48MHz or 38.4MHz" -#endif -#endif -} - -#ifdef CONFIG_HIBERNATE -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) -{ - struct rtc_time_reg rtc; - - if (seconds || microseconds) - set_rtc_alarm(seconds, microseconds, &rtc, 0); - - /* interrupts off now */ - asm volatile("cpsid i"); - -#ifdef CONFIG_HIBERNATE_WAKEUP_PINS - /* enable the wake up pins */ - STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS; -#endif - STM32_PWR_CR |= 0xe; - CPU_SCB_SYSCTRL |= 0x4; - /* go to Standby mode */ - asm("wfi"); - - /* we should never reach that point */ - while (1) - ; -} -#endif - -#ifdef CONFIG_HOSTCMD_RTC -static void restore_host_wake_alarm_deferred(void) -{ - restore_host_wake_alarm(); -} -DECLARE_DEFERRED(restore_host_wake_alarm_deferred); -#endif - -#ifdef CONFIG_LOW_POWER_IDLE - -void clock_refresh_console_in_use(void) -{ -} - -void __idle(void) -{ - timestamp_t t0; - uint32_t rtc_diff; - int next_delay, margin_us; - struct rtc_time_reg rtc0, rtc1; - - while (1) { - asm volatile("cpsid i"); - - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - -#ifdef CONFIG_LOW_POWER_IDLE_LIMITED - if (idle_is_disabled()) - goto en_int; -#endif - - if (DEEP_SLEEP_ALLOWED && -#ifdef CONFIG_HOSTCMD_RTC - /* - * Don't go to deep sleep mode if we might miss the - * wake alarm that the host requested. Note that the - * host alarm always aligns to second. Considering the - * worst case, we have to ensure alarm won't go off - * within RESTORE_HOST_ALARM_LATENCY + 1 second after - * EC exits deep sleep mode. - */ - !is_host_wake_alarm_expired( - (timestamp_t)(next_delay + t0.val + SECOND + - RESTORE_HOST_ALARM_LATENCY)) && -#endif - (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) { - /* Deep-sleep in STOP mode */ - idle_dsleep_cnt++; - - uart_enable_wakeup(1); - - /* Set deep sleep bit */ - CPU_SCB_SYSCTRL |= 0x4; - - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, - &rtc0, 0); - asm("wfi"); - - CPU_SCB_SYSCTRL &= ~0x4; - - uart_enable_wakeup(0); - - /* - * By default only HSI 8MHz is enabled here. Re-enable - * high-speed clock if in use. - */ - config_hispeed_clock(); - - /* Fast forward timer according to RTC counter */ - reset_rtc_alarm(&rtc1); - rtc_diff = get_rtc_diff(&rtc0, &rtc1); - t0.val = t0.val + rtc_diff; - force_time(t0); - -#ifdef CONFIG_HOSTCMD_RTC - hook_call_deferred( - &restore_host_wake_alarm_deferred_data, 0); -#endif - /* Record time spent in deep sleep. */ - idle_dsleep_time_us += rtc_diff; - - /* Calculate how close we were to missing deadline */ - margin_us = next_delay - rtc_diff; - if (margin_us < 0) - /* Use CPUTS to save stack space */ - CPUTS("Idle overslept!\n"); - - /* Record the closest to missing a deadline. */ - if (margin_us < dsleep_recovery_margin_us) - dsleep_recovery_margin_us = margin_us; - } else { - idle_sleep_cnt++; - - /* Normal idle : only CPU clock stopped */ - asm("wfi"); - } -#ifdef CONFIG_LOW_POWER_IDLE_LIMITED -en_int: -#endif - asm volatile("cpsie i"); - } -} -#endif /* CONFIG_LOW_POWER_IDLE */ - -int clock_get_freq(void) -{ - return CPU_CLOCK; -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t unused __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - unused = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - unused = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - if (module == MODULE_ADC) { - if (enable) - STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN; - else - STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN; - return; - } else if (module == MODULE_USB) { - if (enable) - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; - else - STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; - } -} - -int clock_is_module_enabled(enum module_id module) -{ - if (module == MODULE_ADC) - return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN); - else if (module == MODULE_USB) - return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB); - return 0; -} - -void rtc_init(void) -{ - rtc_unlock_regs(); - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) - ; - - /* Enable RTC alarm interrupt */ - STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; - STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; - task_enable_irq(STM32_IRQ_RTC_ALARM); - - rtc_lock_regs(); -} - -#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) -void rtc_set(uint32_t sec) -{ - struct rtc_time_reg rtc; - - sec_to_rtc(sec, &rtc); - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - STM32_RTC_TR = rtc.rtc_tr; - STM32_RTC_DR = rtc.rtc_dr; - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - - rtc_lock_regs(); -} -#endif - -#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME) -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n", ts.val); - ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* CONFIG_CMD_IDLE_STATS */ -#endif diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c deleted file mode 120000 index be91154e52..0000000000 --- a/chip/stm32/clock-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -clock-stm32f0.c
\ No newline at end of file diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c deleted file mode 100644 index a50f5f51dd..0000000000 --- a/chip/stm32/clock-stm32f4.c +++ /dev/null @@ -1,553 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_HSE, /* High-speed external oscillator */ - OSC_PLL, /* PLL */ -}; - -/* - * NOTE: Sweetberry requires MCO2 <- HSE @ 24MHz - * MCO outputs are selected here but are not changeable later. - * A CONFIG may be needed if other boards have different MCO - * requirements. - */ -#define RCC_CFGR_MCO_CONFIG ((2 << 30) | /* MCO2 <- HSE */ \ - (0 << 27) | /* MCO2 div / 4 */ \ - (6 << 24) | /* MCO1 div / 4 */ \ - (3 << 21)) /* MCO1 <- PLL */ - -#ifdef CONFIG_STM32_CLOCK_HSE_HZ -/* RTC clock must 1 Mhz when derived from HSE */ -#define RTC_DIV DIV_ROUND_NEAREST(CONFIG_STM32_CLOCK_HSE_HZ, STM32F4_RTC_REQ) -#else /* !CONFIG_STM32_CLOCK_HSE_HZ */ -/* RTC clock not derived from HSE, turn it off */ -#define RTC_DIV 0 -#endif /* CONFIG_STM32_CLOCK_HSE_HZ */ - - -/* Bus clocks dividers depending on the configuration */ -/* - * max speed configuration with the PLL ON - * as defined in the registers file. - * For STM32F446: max 45 MHz - * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz - */ -#define RCC_CFGR_DIVIDERS_WITH_PLL (RCC_CFGR_MCO_CONFIG | \ - CFGR_RTCPRE(RTC_DIV) | \ - CFGR_PPRE2(STM32F4_APB2_PRE) | \ - CFGR_PPRE1(STM32F4_APB1_PRE) | \ - CFGR_HPRE(STM32F4_AHB_PRE)) -/* - * lower power configuration without the PLL - * the frequency will be low (8-24Mhz), we don't want dividers to the - * peripheral clocks, put /1 everywhere. - */ -#define RCC_CFGR_DIVIDERS_NO_PLL (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | \ - CFGR_PPRE2(0) | CFGR_PPRE1(0) | CFGR_HPRE(0)) - -/* PLL output frequency */ -#define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV) - -/* current clock settings (PLL is initialized at startup) */ -static int current_osc = OSC_PLL; -static int current_io_freq = STM32F4_IO_CLOCK; -static int current_timer_freq = STM32F4_TIMER_CLOCK; - -/* the EC code expects to get the USART/I2C clock frequency here (APB clock) */ -int clock_get_freq(void) -{ - return current_io_freq; -} - -int clock_get_timer_freq(void) -{ - return current_timer_freq; -} - -static void clock_enable_osc(enum clock_osc osc, bool enabled) -{ - uint32_t ready; - uint32_t on; - - switch (osc) { - case OSC_HSI: - ready = STM32_RCC_CR_HSIRDY; - on = STM32_RCC_CR_HSION; - break; - case OSC_HSE: - ready = STM32_RCC_CR_HSERDY; - on = STM32_RCC_CR_HSEON; - break; - case OSC_PLL: - ready = STM32_RCC_CR_PLLRDY; - on = STM32_RCC_CR_PLLON; - break; - default: - ASSERT(0); - return; - } - - /* Turn off the oscillator, but don't wait for shutdown */ - if (!enabled) { - STM32_RCC_CR &= ~on; - return; - } - - /* Turn on the oscillator if not already on */ - wait_for_ready(&STM32_RCC_CR, on, ready); -} - -static void clock_switch_osc(enum clock_osc osc) -{ - uint32_t sw; - uint32_t sws; - - switch (osc) { - case OSC_HSI: - sw = STM32_RCC_CFGR_SW_HSI | RCC_CFGR_DIVIDERS_NO_PLL; - sws = STM32_RCC_CFGR_SWS_HSI; - break; - case OSC_HSE: - sw = STM32_RCC_CFGR_SW_HSE | RCC_CFGR_DIVIDERS_NO_PLL; - sws = STM32_RCC_CFGR_SWS_HSE; - break; - case OSC_PLL: - sw = STM32_RCC_CFGR_SW_PLL | RCC_CFGR_DIVIDERS_WITH_PLL; - sws = STM32_RCC_CFGR_SWS_PLL; - break; - default: - return; - } - - STM32_RCC_CFGR = sw; - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws) - ; -} - -void clock_set_osc(enum clock_osc osc) -{ - volatile uint32_t unused __attribute__((unused)); - - if (osc == current_osc) - return; - - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - default: - case OSC_HSI: - /* new clock settings: no dividers */ - current_io_freq = STM32F4_HSI_CLOCK; - current_timer_freq = STM32F4_HSI_CLOCK; - /* Switch to HSI */ - clock_switch_osc(OSC_HSI); - /* optimized flash latency settings for <30Mhz clock (0-WS) */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY_SLOW; - /* read-back the latency as advised by the Reference Manual */ - unused = STM32_FLASH_ACR; - /* Turn off the PLL1 to save power */ - clock_enable_osc(OSC_PLL, false); - break; - -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - case OSC_HSE: - /* new clock settings: no dividers */ - current_io_freq = CONFIG_STM32_CLOCK_HSE_HZ; - current_timer_freq = CONFIG_STM32_CLOCK_HSE_HZ; - /* Switch to HSE */ - clock_switch_osc(OSC_HSE); - /* optimized flash latency settings for <30Mhz clock (0-WS) */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY_SLOW; - /* read-back the latency as advised by the Reference Manual */ - unused = STM32_FLASH_ACR; - /* Turn off the PLL1 to save power */ - clock_enable_osc(OSC_PLL, false); - break; -#endif /* CONFIG_STM32_CLOCK_HSE_HZ */ - - case OSC_PLL: - /* new clock settings */ - current_io_freq = STM32F4_IO_CLOCK; - current_timer_freq = STM32F4_TIMER_CLOCK; - /* turn on PLL and wait until it's ready */ - clock_enable_osc(OSC_PLL, true); - /* - * Increase flash latency before transition the clock - * Use the minimum Wait States value optimized for the platform. - */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY; - /* read-back the latency as advised by the Reference Manual */ - unused = STM32_FLASH_ACR; - /* Switch to PLL */ - clock_switch_osc(OSC_PLL); - - break; - } - - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); -} - -static void clock_pll_configure(void) -{ -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - int srcclock = CONFIG_STM32_CLOCK_HSE_HZ; -#else - int srcclock = STM32F4_HSI_CLOCK; -#endif - int plldiv, pllinputclock; - int pllmult, vcoclock; - int systemclock; - int usbdiv; - int i2sdiv; - - /* PLL input must be between 1-2MHz, near 2 */ - /* Valid values 2-63 */ - plldiv = (srcclock + STM32F4_PLL_REQ - 1) / STM32F4_PLL_REQ; - pllinputclock = srcclock / plldiv; - - /* PLL output clock: Must be 100-432MHz */ - pllmult = (STM32F4_VCO_CLOCK + (pllinputclock / 2)) / pllinputclock; - vcoclock = pllinputclock * pllmult; - - /* CPU/System clock */ - systemclock = vcoclock / STM32F4_PLLP_DIV; - /* USB clock = 48MHz exactly */ - usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ; - assert(vcoclock / usbdiv == STM32F4_USB_REQ); - - /* SYSTEM/I2S: same system clock */ - i2sdiv = (vcoclock + (systemclock / 2)) / systemclock; - - /* Set up PLL */ - STM32_RCC_PLLCFGR = - PLLCFGR_PLLM(plldiv) | - PLLCFGR_PLLN(pllmult) | - PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) | -#if defined(CONFIG_STM32_CLOCK_HSE_HZ) - PLLCFGR_PLLSRC_HSE | -#else - PLLCFGR_PLLSRC_HSI | -#endif - PLLCFGR_PLLQ(usbdiv) | - PLLCFGR_PLLR(i2sdiv); -} - -void low_power_init(void); - -void config_hispeed_clock(void) -{ -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - /* Ensure that HSE is ON */ - clock_enable_osc(OSC_HSE, true); -#endif - - /* Put the PLL settings, they are never changing */ - clock_pll_configure(); - clock_enable_osc(OSC_PLL, true); - - /* Switch SYSCLK to PLL, setup bus prescalers. */ - clock_switch_osc(OSC_PLL); - -#ifdef CONFIG_LOW_POWER_IDLE - low_power_init(); -#endif -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t unused __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - unused = STM32_DMA_GET_ISR(0); - } else { /* APB */ - while (cycles--) - unused = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - if (module == MODULE_USB) { - if (enable) { - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN; - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN | - STM32_RCC_AHB1ENR_OTGHSULPIEN; - } else { - STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN; - STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN & - ~STM32_RCC_AHB1ENR_OTGHSULPIEN; - } - return; - } else if (module == MODULE_I2C) { - if (enable) { - /* Enable clocks to I2C modules if necessary */ - STM32_RCC_APB1ENR |= - STM32_RCC_I2C1EN | STM32_RCC_I2C2EN - | STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN; - STM32_RCC_DCKCFGR2 = - (STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK) - | DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB); - } else { - STM32_RCC_APB1ENR &= - ~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN | - STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN); - } - return; - } else if (module == MODULE_ADC) { - if (enable) - STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADC1EN; - else - STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADC1EN; - return; - } -} - -/* Real Time Clock (RTC) */ - -#ifdef CONFIG_STM32_CLOCK_HSE_HZ -#define RTC_PREDIV_A 39 -#define RTC_FREQ ((STM32F4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */ -#else /* from LSI clock */ -#define RTC_PREDIV_A 1 -#define RTC_FREQ (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */ -#endif -#define RTC_PREDIV_S (RTC_FREQ - 1) -/* - * Scaling factor to ensure that the intermediate values computed from/to the - * RTC frequency are fitting in a 32-bit integer. - */ -#define SCALING 1000 - -int32_t rtcss_to_us(uint32_t rtcss) -{ - return ((RTC_PREDIV_S - rtcss) * (SECOND/SCALING) / (RTC_FREQ/SCALING)); -} - -uint32_t us_to_rtcss(int32_t us) -{ - return (RTC_PREDIV_S - (us * (RTC_FREQ/SCALING) / (SECOND/SCALING))); -} - -void rtc_init(void) -{ - /* Setup RTC Clock input */ -#ifdef CONFIG_STM32_CLOCK_HSE_HZ - /* RTC clocked from the HSE */ - STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE); -#else - /* RTC clocked from the LSI, ensure first it is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); - - STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI); -#endif - - rtc_unlock_regs(); - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars: Needs two separate writes. */ - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S; - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) - | (RTC_PREDIV_A << 16); - - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) - ; - - /* Enable RTC alarm interrupt */ - STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; - STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; - task_enable_irq(STM32_IRQ_RTC_ALARM); - - rtc_lock_regs(); -} - -#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) -void rtc_set(uint32_t sec) -{ - struct rtc_time_reg rtc; - - sec_to_rtc(sec, &rtc); - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - STM32_RTC_TR = rtc.rtc_tr; - STM32_RTC_DR = rtc.rtc_dr; - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - - rtc_lock_regs(); -} -#endif - -#ifdef CONFIG_LOW_POWER_IDLE -/* Low power idle statistics */ -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t idle_dsleep_time_us; -static int dsleep_recovery_margin_us = 1000000; - -/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */ -#define STOP_MODE_LATENCY 50 /* us */ -/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */ -#define PLL_LOCK_LATENCY 150 /* us */ -/* - * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm - * in the past, it will never wake up and cause a watchdog. - */ -#define SET_RTC_MATCH_DELAY 120 /* us */ - - -void low_power_init(void) -{ - /* Turn off the main regulator during stop mode */ - STM32_PWR_CR |= STM32_PWR_CR_LPSDSR /* aka LPDS */; -} - -void clock_refresh_console_in_use(void) -{ -} - -void __idle(void) -{ - timestamp_t t0; - uint32_t rtc_diff; - int next_delay, margin_us; - struct rtc_time_reg rtc0, rtc1; - - while (1) { - asm volatile("cpsid i"); - - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - - if (DEEP_SLEEP_ALLOWED && - (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY + - SET_RTC_MATCH_DELAY))) { - /* Deep-sleep in STOP mode */ - idle_dsleep_cnt++; - - /* - * TODO(b/174337385) no support for wake-up on USART - * uart_enable_wakeup(1); - */ - - /* Set deep sleep bit */ - CPU_SCB_SYSCTRL |= 0x4; - - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY - - PLL_LOCK_LATENCY, - &rtc0, 0); - - /* Switch to HSI */ - clock_switch_osc(OSC_HSI); - /* Turn off the PLL1 to save power */ - clock_enable_osc(OSC_PLL, false); - - /* ensure outstanding memory transactions complete */ - asm volatile("dsb"); - - asm("wfi"); - - CPU_SCB_SYSCTRL &= ~0x4; - - /* turn on PLL and wait until it's ready */ - clock_enable_osc(OSC_PLL, true); - /* Switch to PLL */ - clock_switch_osc(OSC_PLL); - - /*uart_enable_wakeup(0);*/ - - /* Fast forward timer according to RTC counter */ - reset_rtc_alarm(&rtc1); - rtc_diff = get_rtc_diff(&rtc0, &rtc1); - t0.val = t0.val + rtc_diff; - force_time(t0); - - /* Record time spent in deep sleep. */ - idle_dsleep_time_us += rtc_diff; - - /* Calculate how close we were to missing deadline */ - margin_us = next_delay - rtc_diff; - if (margin_us < 0) - /* Use CPUTS to save stack space */ - CPUTS("Idle overslept!\n"); - - /* Record the closest to missing a deadline. */ - if (margin_us < dsleep_recovery_margin_us) - dsleep_recovery_margin_us = margin_us; - } else { - idle_sleep_cnt++; - - /* Normal idle : only CPU clock stopped */ - asm("wfi"); - } - asm volatile("cpsie i"); - } -} - -/* Print low power idle statistics. */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n", ts.val); - ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c deleted file mode 100644 index 42a00a0f6a..0000000000 --- a/chip/stm32/clock-stm32g4.c +++ /dev/null @@ -1,294 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks configuration routines */ - -#include "chipset.h" -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -#define MHZ(x) ((x) * 1000000) -#define WAIT_STATE_FREQ_STEP_HZ MHZ(20) -/* PLL configuration constants */ -#define STM32G4_SYSCLK_MAX_HZ MHZ(170) -#define STM32G4_HSI_CLK_HZ MHZ(16) -#define STM32G4_PLL_IN_FREQ_HZ MHZ(4) -#define STM32G4_PLL_R 2 -#define STM32G4_AHB_PRE 1 -#define STM32G4_APB1_PRE 1 -#define STM32G4_APB2_PRE 1 - -enum rcc_clksrc { - sysclk_rsvd, - sysclk_hsi, - sysclk_hse, - sysclk_pll, -}; - -static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, - uint32_t pll_clk_in_hz) -{ - /* - * The pll output frequency (Fhclkc) is determined by: - * Fvco = Fosc_in * (PLL_N / PLL_M) - * Fsysclk = Fvco / PLL_R - * Fhclk = Fsysclk / AHBpre = (Fosc * N) /(M * R * AHBpre) - * - * PLL_N: 8 <= N <= 127 - * PLL_M: 1 <= M <= 16 - * PLL_R: 2, 4, 6, or 8 - * - * PLL_input freq (4 - 16 MHz) - * Fvco: 2.66 MHz <= Fvco_in <= 8 MHz - * 64 MHz <= Fvco_out <= 344 MHz - * Fhclk <= 170 MHz - * - * PLL config parameters are selected given the following assumptions: - * - PLL input freq = 4 MHz - * - PLL_R divider = 2 - * With these assumptions the value N can be calculated by: - * N = (Fhclk * M * R * AHBpre) / Fosc - * where M = Fosc / F_pllin - * Replacing M gives: - * N = (Fhclk * R * AHBpre) / Fpll_in - */ - uint32_t pll_n; - uint32_t pll_m; - uint32_t hclk_freq; - - /* Pll input divider = input freq / desired_input_freq */ - pll_m = pll_clk_in_hz / STM32G4_PLL_IN_FREQ_HZ; - pll_n = (hclk_hz * STM32G4_PLL_R * STM32G4_AHB_PRE) / - STM32G4_PLL_IN_FREQ_HZ; - - /* validity checks */ - ASSERT(pll_m && (pll_m <= 16)); - ASSERT((pll_n >= 8) && (pll_n <= 127)); - - hclk_freq = pll_clk_in_hz * pll_n / (pll_m * - STM32G4_PLL_R * STM32G4_AHB_PRE); - /* Ensure that there aren't any integer rounding errors */ - ASSERT(hclk_freq == hclk_hz); - - /* Program PLL config register */ - STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) | - PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) | - PLLCFGR_PLLR_EN | - PLLCFGR_PLLQ(0) | - PLLCFGR_PLLQ_EN | - PLLCFGR_PLLN(pll_n) | - PLLCFGR_PLLM(pll_m - 1) | - pll_src; - - /* Wait until PLL is locked */ - wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON, - STM32_RCC_CR_PLLRDY); - - /* - * Program prescalers and set system clock source as PLL - * Assuming AHB, APB1, and APB2 prescalers are 1, and no clock output - * desired so MCO fields are left at reset value. - */ - STM32_RCC_CFGR = STM32_RCC_CFGR_SW_PLL; - - /* Wait until the PLL is the system clock source */ - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_PLL) - ; -} - -static void stm32g4_config_low_speed_clock(void) -{ - /* Ensure that LSI is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); - - /* Setup RTC Clock input */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; - STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI); -} - -static void stm32g4_config_high_speed_clock(uint32_t hclk_hz, - enum rcc_clksrc sysclk_src, - uint32_t pll_clksrc) -{ - /* TODO(b/161502871): PLL is currently only supported clock source */ - ASSERT(sysclk_src == sysclk_pll); - - /* Ensure that HSI is ON */ - wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_HSION, - STM32_RCC_CR_HSIRDY); - - if (sysclk_src == sysclk_pll) { - /* - * If PLL_R is the desired clock source, then need to calculate - * PLL multilier/diviber parameters. Once the PLL output is - * stable, then the PLL must be selected as the clock - * source. Note, that if the current clock source selection is - * the PLL and sysclk frequency == hclk_hz, there is nothing - * that needs to be done here. - */ - /* If PLL is the clock source, PLL has already been set up. */ - if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) == - STM32_RCC_CFGR_SWS_PLL) - return; - stm32g4_config_pll(hclk_hz, pll_clksrc, STM32G4_HSI_CLK_HZ); - } -} - -void stm32g4_set_flash_ws(uint32_t freq_hz) -{ - int ws; - - ASSERT(freq_hz <= STM32G4_SYSCLK_MAX_HZ); - /* - * Need to calculate and then set number of wait states (in CPU cycles) - * required for access to internal flash. The required values can be - * found in Table 9 of RM0440 - STM32G4 technical reference manual. A - * table lookup is not required though as WS = HCLK (MHz) / 20 - */ - ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ; - /* Enable data and instruction cache */ - STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN | - STM32_FLASH_ACR_PRFTEN | ws; -} - -void clock_init(void) -{ - /* - * The STM32G4 has 3 potential sysclk sources: - * 1. HSE -> external cyrstal oscillator circuit - * 2. HSI -> Internal RC oscillator (16 MHz output) - * 3. PLL -> input from either HSI or HSI - * - * SYSCLK is routed to AHB via the AHB prescaler. The AHB clock is fed - * directly to AHB bus, core, memory, DMA, and cortex FCLK. The AHB bus - * clock is then fed to both APB1 and APB2 buses via the APB1 and APB2 - * prescalers. - * - * CrosEC doesn't support having multiple clocks of different - * frequencies and therefore f(AHB) = f(APB1) = f(APB2) must be - * enforced. The max frequency of all these clocks is 170 MHz. Max input - * frequency to the PLL is 48 MHz. The M divider can be used to lower - * the PLL input frequency if necessary. The PLL has 3 different output - * clocks, PLL_P, PLL_Q, and PLL_R. PLL_R is the clock which can be used - * as SYSCLK. - * - * The STM32G4 has an additional 48 MHz internal oscillator that is fed - * directly to the USB and RNG blocks. - * - * The STM32G4 also has a low speed clock which feeds the RTC and IWDG - * blocks and as a low power clock source that can be kept running - * during stop and standby modes. The low speed clock is generated from: - * 1. LSE -> external crystal oscillator (max = 1 MHz) - * 2. LSI -> internal fixed 32 kHz - * - * The initial state following system reset: - * SYSCLK from HSI, AHB, APB1, and APB2 presecaler = 1 - * PLL unlocked, RTC enabled on LSE - */ - - /* Configure flash wait state and enable I/D cache */ - stm32g4_set_flash_ws(CPU_CLOCK); - /* Set up high speed clock and enable PLL */ - stm32g4_config_high_speed_clock(CPU_CLOCK, sysclk_pll, - PLLCFGR_PLLSRC_HSI); - /* Set up low speed clock */ - stm32g4_config_low_speed_clock(); -} - -int clock_get_timer_freq(void) -{ - /* - * STM32G4 timer clocks (TCLK) are either at the same frequency as - * PCLK_N when the APB prescaler is 1, and TLCK = 2 * PCLK if - * APBn_pre > 1. It's expected that PCLK1 == PCLK2, so only have to - * check either of the apb prescalar settings. - */ - return (STM32G4_APB1_PRE > 1 ? CPU_CLOCK * 2 : CPU_CLOCK); -} - -int clock_get_freq(void) -{ - return CPU_CLOCK; -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t unused __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - unused = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - unused = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -void clock_enable_module(enum module_id module, int enable) -{ - if (module == MODULE_USB) { - if (enable) { - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; - STM32_RCC_CRRCR |= RCC_CRRCR_HSI48O; - } else { - STM32_RCC_CRRCR &= ~RCC_CRRCR_HSI48O; - STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; - } - } else if (module == MODULE_I2C) { - if (enable) { - /* Enable clocks to I2C modules if necessary */ - STM32_RCC_APB1ENR1 |= - STM32_RCC_APB1ENR1_I2C1EN | - STM32_RCC_APB1ENR1_I2C2EN | - STM32_RCC_APB1ENR1_I2C3EN; - STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN; - } else { - STM32_RCC_APB1ENR1 &= - ~(STM32_RCC_APB1ENR1_I2C1EN | - STM32_RCC_APB1ENR1_I2C2EN | - STM32_RCC_APB1ENR1_I2C3EN); - STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN; - } - } else if (module == MODULE_ADC) { - /* TODO does clock select need to be set here too? */ - if (enable) - STM32_RCC_AHB2ENR |= (STM32_RCC_AHB2ENR_ADC12EN | - STM32_RCC_APB2ENR_ADC345EN); - else - STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN | - STM32_RCC_APB2ENR_ADC345EN); - } else { - CPRINTS("stm32g4: enable clock module %d not supported", - module); - } -} - -int clock_is_module_enabled(enum module_id module) -{ - if (module == MODULE_USB) - return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB); - else if (module == MODULE_I2C) - return !!(STM32_RCC_APB1ENR1 & STM32_RCC_APB1ENR1_I2C1EN); - else if (module == MODULE_ADC) - return !!(STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_ADC12EN); - return 0; -} - diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c deleted file mode 100644 index ba233dbd76..0000000000 --- a/chip/stm32/clock-stm32h7.c +++ /dev/null @@ -1,620 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Clocks and power management settings - * - * Error Handling and Unimplemented Features: - * Since we are dealing with code critical to the runtime of the CPU, - * our strategy for unimplemented functionality is to ASSERT, but fallback - * to doing nothing if ASSERT is not enabled. This is not a perfect solution, - * but at least yields predictable behavior. - */ - - -#include <stdbool.h> - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" - -/* Check chip family and variant for compatibility */ -#ifndef CHIP_FAMILY_STM32H7 -#error Source clock-stm32h7.c does not support this chip family. -#endif -#ifndef CHIP_VARIANT_STM32H7X3 -#error Unsupported chip variant. -#endif - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) - -enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */ - OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */ - OSC_PLL, /* PLL */ -}; - -enum voltage_scale { - VOLTAGE_SCALE0 = 0, - VOLTAGE_SCALE1, - VOLTAGE_SCALE2, - VOLTAGE_SCALE3, - VOLTAGE_SCALE_COUNT, -}; - -enum freq { - FREQ_1KHZ = 1000, - FREQ_32KHZ = 32 * FREQ_1KHZ, - FREQ_1MHZ = 1000000, - FREQ_2MHZ = 2 * FREQ_1MHZ, - FREQ_16MHZ = 16 * FREQ_1MHZ, - FREQ_64MHZ = 64 * FREQ_1MHZ, - FREQ_140MHZ = 140 * FREQ_1MHZ, - FREQ_200MHZ = 200 * FREQ_1MHZ, - FREQ_280MHZ = 280 * FREQ_1MHZ, - FREQ_400MHZ = 400 * FREQ_1MHZ, - FREQ_480MHZ = 480 * FREQ_1MHZ, -}; - -/* High-speed oscillator default is 64 MHz */ -#define STM32_HSI_CLOCK FREQ_64MHZ -/* Low-speed oscillator is 32-Khz */ -#define STM32_LSI_CLOCK FREQ_32KHZ - -/* - * LPTIM is a 16-bit counter clocked by LSI - * with /4 prescaler (2^2): period 125 us, full range ~8s - */ -#define LPTIM_PRESCALER_LOG2 2 -/* - * LPTIM_PRESCALER and LPTIM_PERIOD_US have to be signed, because they - * determine the signedness of the comparison with |next_delay| in - * __idle(), where |next_delay| is negative if no next event. - */ -#define LPTIM_PRESCALER ((int)BIT(LPTIM_PRESCALER_LOG2)) -#define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER)) - -/* This is not the core frequency */ -static enum freq current_bus_freq = STM32_HSI_CLOCK; -static int current_osc = OSC_HSI; - -int clock_get_freq(void) -{ - return current_bus_freq; -} - -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t unused __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - unused = STM32_GPIO_IDR(GPIO_A); - } else { /* APB */ - while (cycles--) - unused = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -/* Flash latency values are dependent on peripheral speed and voltage scale */ -static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos) -{ - uint32_t target_acr; - - if (axi_freq == FREQ_64MHZ && vos == VOLTAGE_SCALE3) { - target_acr = STM32_FLASH_ACR_WRHIGHFREQ_85MHZ | - (0 << STM32_FLASH_ACR_LATENCY_SHIFT); - } else if (axi_freq == FREQ_200MHZ && vos == VOLTAGE_SCALE1) { - target_acr = STM32_FLASH_ACR_WRHIGHFREQ_285MHZ | - (2 << STM32_FLASH_ACR_LATENCY_SHIFT); - } else { - ASSERT(0); - return; - } - - STM32_FLASH_ACR(0) = target_acr; - while (STM32_FLASH_ACR(0) != target_acr) - ; -} - -/** - * @brief Configure PLL1 to output the specified frequency. - * - * The input frequency to PLL1 is assumed to be the HSI, which - * is 64MHz. - * - * @param output_freq The target output frequency. - */ -static void clock_pll1_configure(enum freq output_freq) { - uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16) - uint32_t divn; // Pll multiplier - uint32_t divp; // Output 1 prescaler - - switch (output_freq) - { - case FREQ_400MHZ: - /* - * PLL1 configuration: - * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP - * = 64MHz/4 * 50 / 2 - * = 16MHz * 50 / 2 - * = 400 Mhz - */ - divn = 50; - divp = 2; - break; - case FREQ_200MHZ: - /* - * PLL1 configuration: - * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP - * = 64 / 4 * 25 / 2 - * = 16MHz * 25 / 2 - * = 200 Mhz - */ - divn = 25; - divp = 2; - break; - case FREQ_280MHZ: - divn = 35; - divp = 2; - break; - case FREQ_480MHZ: - divn = 60; - divp = 2; - break; - default: - ASSERT(0); - return; - } - - /* - * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE, - * requires input frequency to be between 2MHz and 16MHz. - */ - ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm)); - ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ); - - /* - * Ensure that we actually reach the target frequency. - */ - ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq); - - /* Configure PLL1 using 64 Mhz HSI as input */ - STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI - | STM32_RCC_PLLCKSEL_DIVM1(divm); - /* in integer mode, wide range VCO with 16Mhz input, use divP */ - STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE - | STM32_RCC_PLLCFG_PLL1RGE_8M_16M - | STM32_RCC_PLLCFG_DIVP1EN; - STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) - | STM32_RCC_PLLDIV_DIVN(divn); -} - -/** - * Configure peripheral domain prescalers to allow a given sysclk frequency. - * - * @param sysclk The input system clock, after the system clock prescaler. - * @return The bus clock speed selected and configured - */ -static enum freq clock_peripheral_configure(enum freq sysclk) { - switch (sysclk) - { - case FREQ_64MHZ: - /* Restore /1 HPRE (AHB prescaler) */ - /* Disable downstream prescalers */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; - /* TODO(b/149512910): Adjust more peripheral prescalers */ - return FREQ_64MHZ; - case FREQ_400MHZ: - /* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; - /* TODO(b/149512910): Adjust more peripheral prescalers */ - return FREQ_200MHZ; - default: - ASSERT(0); - return 0; - } -} - -static void clock_enable_osc(enum clock_osc osc, bool enabled) -{ - uint32_t ready; - uint32_t on; - - switch (osc) { - case OSC_HSI: - ready = STM32_RCC_CR_HSIRDY; - on = STM32_RCC_CR_HSION; - break; - case OSC_PLL: - ready = STM32_RCC_CR_PLL1RDY; - on = STM32_RCC_CR_PLL1ON; - break; - default: - ASSERT(0); - return; - } - - /* Turn off the oscillator, but don't wait for shutdown */ - if (!enabled) { - STM32_RCC_CR &= ~on; - return; - } - - /* Turn on the oscillator if not already on */ - wait_for_ready(&STM32_RCC_CR, on, ready); -} - -static void clock_switch_osc(enum clock_osc osc) -{ - uint32_t sw; - uint32_t sws; - - switch (osc) { - case OSC_HSI: - sw = STM32_RCC_CFGR_SW_HSI; - sws = STM32_RCC_CFGR_SWS_HSI; - break; - case OSC_PLL: - sw = STM32_RCC_CFGR_SW_PLL1; - sws = STM32_RCC_CFGR_SWS_PLL1; - break; - default: - return; - } - - STM32_RCC_CFGR = sw; - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != sws) - ; -} - -static void switch_voltage_scale(enum voltage_scale vos) -{ - volatile uint32_t *const vos_reg = &STM32_PWR_D3CR; - const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY; - const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK; - const uint32_t vos_values[] = { - /* See note below about VOS0. */ - STM32_PWR_D3CR_VOS1, - STM32_PWR_D3CR_VOS1, - STM32_PWR_D3CR_VOS2, - STM32_PWR_D3CR_VOS3, - }; - BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT); - - /* - * Real VOS0 on the H743 requires entering VOS1 and setting an extra - * SYS boost register. We currently do not implement this functionality. - */ - if (vos == VOLTAGE_SCALE0) { - ASSERT(0); - return; - } - - *vos_reg &= ~vos_mask; - *vos_reg |= vos_values[vos]; - while (!(*vos_reg & vos_ready)) - ; -} - -static void clock_set_osc(enum clock_osc osc) -{ - enum freq target_sysclk_freq = FREQ_64MHZ; - enum voltage_scale target_voltage_scale = VOLTAGE_SCALE3; - - if (osc == current_osc) - return; - - switch (osc) { - case OSC_HSI: - case OSC_PLL: - break; - default: - ASSERT(0); - return; - } - - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - default: - case OSC_HSI: - /* Switch to HSI */ - clock_switch_osc(osc); - current_bus_freq = clock_peripheral_configure(target_sysclk_freq); - /* Use more optimized flash latency settings for 64-MHz ACLK */ - clock_flash_latency(current_bus_freq, target_voltage_scale); - /* Turn off the PLL1 to save power */ - clock_enable_osc(OSC_PLL, false); - switch_voltage_scale(target_voltage_scale); - break; - - case OSC_PLL: - /* - * PLL1 configuration: - * CPU freq = VCO / DIVP = HSI / DIVM * DIVN / DIVP - * = 64 / 4 * 50 / 2 - * = 400 Mhz - * System clock = 400 Mhz - * HPRE = /2 => AHB/Timer clock = 200 Mhz - */ - target_sysclk_freq = FREQ_400MHZ; - target_voltage_scale = VOLTAGE_SCALE1; - - switch_voltage_scale(target_voltage_scale); - clock_pll1_configure(target_sysclk_freq); - /* turn on PLL1 and wait until it's ready */ - clock_enable_osc(OSC_PLL, true); - current_bus_freq = clock_peripheral_configure(target_sysclk_freq); - /* Increase flash latency before transition the clock */ - clock_flash_latency(current_bus_freq, target_voltage_scale); - - /* Switch to PLL */ - clock_switch_osc(OSC_PLL); - break; - } - - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); -} - -void clock_enable_module(enum module_id module, int enable) -{ - /* Assume we have a single task using MODULE_FAST_CPU */ - if (module == MODULE_FAST_CPU) { - /* the PLL would be off in low power mode, disable it */ - if (enable) - disable_sleep(SLEEP_MASK_PLL); - else - enable_sleep(SLEEP_MASK_PLL); - clock_set_osc(enable ? OSC_PLL : OSC_HSI); - } -} - -#ifdef CONFIG_LOW_POWER_IDLE -/* Low power idle statistics */ -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t idle_dsleep_time_us; -static int dsleep_recovery_margin_us = 1000000; - -/* STOP_MODE_LATENCY: delay to wake up from STOP mode with flash off in SVOS5 */ -#define STOP_MODE_LATENCY 50 /* us */ - -static void low_power_init(void) -{ - /* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */ - STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R & - ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) - | STM32_RCC_D2CCIP2_LPTIM1SEL_LSI; - - /* configure LPTIM1 as our 1-Khz low power timer in STOP mode */ - STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1; - STM32_LPTIM_CR(1) = 0; /* ensure it's disabled before configuring */ - STM32_LPTIM_CFGR(1) = LPTIM_PRESCALER_LOG2 << 9; /* Prescaler /4 */ - STM32_LPTIM_IER(1) = STM32_LPTIM_INT_CMPM; /* Compare int for wake-up */ - /* Start the 16-bit free-running counter */ - STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE; - STM32_LPTIM_ARR(1) = 0xFFFF; - STM32_LPTIM_CR(1) = STM32_LPTIM_CR_ENABLE | STM32_LPTIM_CR_CNTSTRT; - task_enable_irq(STM32_IRQ_LPTIM1); - - /* Wake-up interrupts from EXTI for USART and LPTIM */ - STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */ - STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */ - - /* optimize power vs latency in STOP mode */ - STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) - | STM32_PWR_CR_SVOS5 - | STM32_PWR_CR_FLPS; -} - -void clock_refresh_console_in_use(void) -{ -} - -void lptim_interrupt(void) -{ - STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM; -} -DECLARE_IRQ(STM32_IRQ_LPTIM1, lptim_interrupt, 2); - -static uint16_t lptim_read(void) -{ - uint16_t cnt; - - do { - cnt = STM32_LPTIM_CNT(1); - } while (cnt != STM32_LPTIM_CNT(1)); - - return cnt; -} - -static void set_lptim_event(int delay_us, uint16_t *lptim_cnt) -{ - uint16_t cnt = lptim_read(); - - STM32_LPTIM_CMP(1) = cnt + MIN(delay_us / LPTIM_PERIOD_US - 1, 0xffff); - /* clean-up previous event */ - STM32_LPTIM_ICR(1) = STM32_LPTIM_INT_CMPM; - *lptim_cnt = cnt; -} - -void __idle(void) -{ - timestamp_t t0; - int next_delay; - int margin_us, t_diff; - uint16_t lptim0; - - while (1) { - asm volatile("cpsid i"); - - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - - if (DEEP_SLEEP_ALLOWED && - next_delay > LPTIM_PERIOD_US + STOP_MODE_LATENCY) { - /* deep-sleep in STOP mode */ - idle_dsleep_cnt++; - - uart_enable_wakeup(1); - - /* set deep sleep bit */ - CPU_SCB_SYSCTRL |= 0x4; - - set_lptim_event(next_delay - STOP_MODE_LATENCY, - &lptim0); - - /* ensure outstanding memory transactions complete */ - asm volatile("dsb"); - - asm("wfi"); - - CPU_SCB_SYSCTRL &= ~0x4; - - /* fast forward timer according to low power counter */ - if (STM32_PWR_CPUCR & STM32_PWR_CPUCR_STOPF) { - uint16_t lptim_dt = lptim_read() - lptim0; - - t_diff = (int)lptim_dt * LPTIM_PERIOD_US; - t0.val = t0.val + t_diff; - force_time(t0); - /* clear STOPF flag */ - STM32_PWR_CPUCR |= STM32_PWR_CPUCR_CSSF; - } else { /* STOP entry was aborted, no fixup */ - t_diff = 0; - } - - uart_enable_wakeup(0); - - /* Record time spent in deep sleep. */ - idle_dsleep_time_us += t_diff; - - /* Calculate how close we were to missing deadline */ - margin_us = next_delay - t_diff; - if (margin_us < 0) - /* Use CPUTS to save stack space */ - CPUTS("Overslept!\n"); - - /* Record the closest to missing a deadline. */ - if (margin_us < dsleep_recovery_margin_us) - dsleep_recovery_margin_us = margin_us; - } else { - idle_sleep_cnt++; - - /* normal idle : only CPU clock stopped */ - asm("wfi"); - } - asm volatile("cpsie i"); - } -} - -#ifdef CONFIG_CMD_IDLE_STATS -/** - * Print low power idle statistics - */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n", ts.val); - ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* CONFIG_CMD_IDLE_STATS */ -#endif /* CONFIG_LOW_POWER_IDLE */ - -void clock_init(void) -{ - /* - * STM32H743 Errata 2.2.15: - * 'Reading from AXI SRAM might lead to data read corruption' - * - * limit concurrent read access on AXI master to 1. - */ - STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE; - - /* - * Lock (SCUEN=0) power configuration with the LDO enabled. - * - * The STM32H7 Reference Manual says: - * The lower byte of this register is written once after POR and shall - * be written before changing VOS level or ck_sys clock frequency. - * - * The interesting side-effect of this that while the LDO is enabled by - * default at startup, if we enter STOP mode without locking it the MCU - * seems to freeze forever. - */ - STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN; - /* - * Ensure the SPI is always clocked at the same frequency - * by putting it on the fixed 64-Mhz HSI clock. - * per_ck is clocked directly by the HSI (as per the default settings). - */ - STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R & - ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK | - STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) - | STM32_RCC_D2CCIP1R_SPI123SEL_PERCK - | STM32_RCC_D2CCIP1R_SPI45SEL_HSI; - - /* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */ - clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3); - - /* Ensure that LSI is ON to clock LPTIM1 and IWDG */ - STM32_RCC_CSR |= STM32_RCC_CSR_LSION; - while (!(STM32_RCC_CSR & STM32_RCC_CSR_LSIRDY)) - ; - -#ifdef CONFIG_LOW_POWER_IDLE - low_power_init(); -#endif -} - -static int command_clock(int argc, char **argv) -{ - if (argc >= 2) { - if (!strcasecmp(argv[1], "hsi")) - clock_set_osc(OSC_HSI); - else if (!strcasecmp(argv[1], "pll")) - clock_set_osc(OSC_PLL); - else - return EC_ERROR_PARAM1; - } - ccprintf("Clock frequency is now %d Hz\n", clock_get_freq()); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | pll", "Set clock frequency"); diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c deleted file mode 100644 index bb0da42d14..0000000000 --- a/chip/stm32/clock-stm32l.c +++ /dev/null @@ -1,384 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "registers.h" -#include "util.h" - -#ifdef CONFIG_STM32L_FAKE_HIBERNATE -#include "extpower.h" -#include "keyboard_config.h" -#include "lid_switch.h" -#include "power.h" -#include "power_button.h" -#include "system.h" -#include "task.h" - -static int fake_hibernate; -#endif - -/* High-speed oscillator is 16 MHz */ -#define HSI_CLOCK 16000000 -/* - * MSI is 2 MHz (default) 1 MHz, depending on ICSCR setting. We use 1 MHz - * because it's the lowest clock rate we can still run 115200 baud serial - * for the debug console. - */ -#define MSI_2MHZ_CLOCK BIT(21) -#define MSI_1MHZ_CLOCK BIT(20) - -enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed oscillator */ - OSC_MSI, /* Med-speed oscillator @ 1 MHz */ -}; - -static int freq; -static int current_osc; - -int clock_get_freq(void) -{ - return freq; -} - -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t unused __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - unused = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - unused = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -/** - * Set which oscillator is used for the clock - * - * @param osc Oscillator to use - */ -static void clock_set_osc(enum clock_osc osc) -{ - uint32_t tmp_acr; - - if (osc == current_osc) - return; - - if (current_osc != OSC_INIT) - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - case OSC_HSI: - /* Ensure that HSI is ON */ - wait_for_ready(&STM32_RCC_CR, - STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY); - - /* Disable LPSDSR */ - STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR; - - /* - * Set the recommended flash settings for 16MHz clock. - * - * The 3 bits must be programmed strictly sequentially. - * Also, follow the RM to check 64-bit access and latency bit - * after writing those bits to the FLASH_ACR register. - */ - tmp_acr = STM32_FLASH_ACR; - /* Enable 64-bit access */ - tmp_acr |= STM32_FLASH_ACR_ACC64; - STM32_FLASH_ACR = tmp_acr; - /* Check ACC64 bit == 1 */ - while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64)) - ; - - /* Enable Prefetch Buffer */ - tmp_acr |= STM32_FLASH_ACR_PRFTEN; - STM32_FLASH_ACR = tmp_acr; - - /* Flash 1 wait state */ - tmp_acr |= STM32_FLASH_ACR_LATENCY; - STM32_FLASH_ACR = tmp_acr; - /* Check LATENCY bit == 1 */ - while (!(STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY)) - ; - - /* Switch to HSI */ - STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI; - /* RM says to check SWS bits to make sure HSI is the sysclock */ - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_HSI) - ; - - /* Disable MSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_MSION; - - freq = HSI_CLOCK; - break; - - case OSC_MSI: - /* Switch to MSI @ 1MHz */ - STM32_RCC_ICSCR = - (STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | - STM32_RCC_ICSCR_MSIRANGE_1MHZ; - /* Ensure that MSI is ON */ - wait_for_ready(&STM32_RCC_CR, - STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY); - - /* Switch to MSI */ - STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI; - /* RM says to check SWS bits to make sure MSI is the sysclock */ - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_MSI) - ; - - /* - * Set the recommended flash settings for <= 2MHz clock. - * - * The 3 bits must be programmed strictly sequentially. - * Also, follow the RM to check 64-bit access and latency bit - * after writing those bits to the FLASH_ACR register. - */ - tmp_acr = STM32_FLASH_ACR; - /* Flash 0 wait state */ - tmp_acr &= ~STM32_FLASH_ACR_LATENCY; - STM32_FLASH_ACR = tmp_acr; - /* Check LATENCY bit == 0 */ - while (STM32_FLASH_ACR & STM32_FLASH_ACR_LATENCY) - ; - - /* Disable prefetch Buffer */ - tmp_acr &= ~STM32_FLASH_ACR_PRFTEN; - STM32_FLASH_ACR = tmp_acr; - - /* Disable 64-bit access */ - tmp_acr &= ~STM32_FLASH_ACR_ACC64; - STM32_FLASH_ACR = tmp_acr; - /* Check ACC64 bit == 0 */ - while (STM32_FLASH_ACR & STM32_FLASH_ACR_ACC64) - ; - - /* Disable HSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_HSION; - - /* Enable LPSDSR */ - STM32_PWR_CR |= STM32_PWR_CR_LPSDSR; - - freq = MSI_1MHZ_CLOCK; - break; - - default: - break; - } - - /* Notify modules of frequency change unless we're initializing */ - if (current_osc != OSC_INIT) { - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); - } else { - current_osc = osc; - } -} - -static uint64_t clock_mask; - -void clock_enable_module(enum module_id module, int enable) -{ - uint64_t new_mask; - - if (enable) - new_mask = clock_mask | BIT_ULL(module); - else - new_mask = clock_mask & ~BIT_ULL(module); - - /* Only change clock if needed */ - if ((!!new_mask) != (!!clock_mask)) { - - /* Flush UART before switching clock speed */ - cflush(); - - clock_set_osc(new_mask ? OSC_HSI : OSC_MSI); - } - - if (module == MODULE_USB) { - if (enable) - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; - else - STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; - } - - clock_mask = new_mask; -} - -int clock_is_module_enabled(enum module_id module) -{ - return !!(clock_mask & BIT_ULL(module)); -} - -#ifdef CONFIG_STM32L_FAKE_HIBERNATE -/* - * This is for NOT having enough hibernate (more precisely, the stand-by mode) - * wake-up source pin. STM32L100 supports 3 wake-up source pins: - * - * WKUP1 (PA0) -- used for ACOK_PMU - * WKUP2 (PC13) -- used for LID_OPEN - * WKUP3 (PE6) -- cannot be used due to IC package. - * - * However, we need the power button as a wake-up source as well and there is - * no available pin for us (we don't want to move the ACOK_PMU pin). - * - * Fortunately, the STM32L is low-power enough so that we don't need the - * super-low-power mode. So, we fake this hibernate mode and accept the - * following wake-up source. - * - * RTC alarm (faked as well). - * Power button - * Lid open - * AC detected - * - * The original issue is here: crosbug.com/p/25435. - */ -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) -{ - int i; - fake_hibernate = 1; - -#ifdef CONFIG_POWER_COMMON - /* - * A quick hack to stop annoying messages from charger task. - * - * When the battery is under 3%, the power task would call - * power_off() to shutdown AP. However, the power_off() would - * notify the HOOK_CHIPSET_SHUTDOWN, where the last hook is - * charge_shutdown() and it hibernates the power task (infinite - * loop -- not real CPU hibernate mode). Unfortunately, the - * charger task is still running. It keeps generating annoying - * log message. - * - * Thus, the hack is to set the power state machine (before we - * enter infinite loop) so that the charger task thinks the AP - * is off and stops generating messages. - */ - power_set_state(POWER_G3); -#endif - - /* - * Change keyboard outputs to high-Z to reduce power draw. - * We don't need corresponding code to change them back, - * because fake hibernate is always exited with a reboot. - * - * A little hacky to do this here. - */ - for (i = GPIO_KB_OUT00; i < GPIO_KB_OUT00 + KEYBOARD_COLS_MAX; i++) - gpio_set_flags(i, GPIO_INPUT); - - ccprints("fake hibernate. waits for power button/lid/RTC/AC"); - cflush(); - - if (seconds || microseconds) { - if (seconds) - sleep(seconds); - if (microseconds) - usleep(microseconds); - } else { - while (1) - task_wait_event(-1); - } - - ccprints("fake RTC alarm fires. resets EC"); - cflush(); - system_reset(SYSTEM_RESET_HARD); -} - -static void fake_hibernate_power_button_hook(void) -{ - if (fake_hibernate && lid_is_open() && !power_button_is_pressed()) { - ccprints("%s() resets EC", __func__); - cflush(); - system_reset(SYSTEM_RESET_HARD); - } -} -DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook, - HOOK_PRIO_DEFAULT); - -static void fake_hibernate_lid_hook(void) -{ - if (fake_hibernate && lid_is_open()) { - ccprints("%s() resets EC", __func__); - cflush(); - system_reset(SYSTEM_RESET_HARD); - } -} -DECLARE_HOOK(HOOK_LID_CHANGE, fake_hibernate_lid_hook, HOOK_PRIO_DEFAULT); - -static void fake_hibernate_ac_hook(void) -{ - if (fake_hibernate && extpower_is_present()) { - ccprints("%s() resets EC", __func__); - cflush(); - system_reset(SYSTEM_RESET_HARD); - } -} -DECLARE_HOOK(HOOK_AC_CHANGE, fake_hibernate_ac_hook, HOOK_PRIO_DEFAULT); -#endif - -void clock_init(void) -{ - /* - * The initial state : - * SYSCLK from MSI (=2MHz), no divider on AHB, APB1, APB2 - * PLL unlocked, RTC enabled on LSE - */ - - /* Switch to high-speed oscillator */ - clock_set_osc(1); -} - -static void clock_chipset_startup(void) -{ - /* Return to full speed */ - clock_enable_module(MODULE_CHIPSET, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT); - -static void clock_chipset_shutdown(void) -{ - /* Drop to lower clock speed if no other module requires full speed */ - clock_enable_module(MODULE_CHIPSET, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); - -static int command_clock(int argc, char **argv) -{ - if (argc >= 2) { - if (!strcasecmp(argv[1], "hsi")) - clock_set_osc(OSC_HSI); - else if (!strcasecmp(argv[1], "msi")) - clock_set_osc(OSC_MSI); - else - return EC_ERROR_PARAM1; - } - - ccprintf("Clock frequency is now %d Hz\n", freq); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | msi", - "Set clock frequency"); diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c deleted file mode 100644 index 2094751aab..0000000000 --- a/chip/stm32/clock-stm32l4.c +++ /dev/null @@ -1,1110 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Clocks and power management settings for STM32L4xx as well as STM32L5xx. */ - -#include "chipset.h" -#include "clock.h" -#include "clock-l4.h" -#include "common.h" -#include "console.h" -#include "cpu.h" -#include "hooks.h" -#include "host_command.h" -#include "registers.h" -#include "rtc.h" -#include "timer.h" -#include "uart.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - -/* High-speed oscillator is 16 MHz */ -#define STM32_HSI_CLOCK 16000000 -/* Multi-speed oscillator is 4 MHz by default */ -#define STM32_MSI_CLOCK 4000000 - -/* Real Time Clock (RTC) */ - -#ifdef CONFIG_STM32_CLOCK_HSE_HZ -#define RTC_PREDIV_A 39 -#define RTC_FREQ ((STM32L4_RTC_REQ) / (RTC_PREDIV_A + 1)) /* Hz */ -#else /* from LSI clock */ -#define RTC_PREDIV_A 1 -#define RTC_FREQ (STM32L4_LSI_CLOCK / (RTC_PREDIV_A + 1)) /* Hz */ -#endif -#define RTC_PREDIV_S (RTC_FREQ - 1) -/* - * Scaling factor to ensure that the intermediate values computed from/to the - * RTC frequency are fitting in a 32-bit integer. - */ -#define SCALING 1000 - -enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed internal oscillator */ - OSC_MSI, /* Multi-speed internal oscillator */ -#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */ - OSC_HSE, /* High-speed external oscillator */ -#endif - OSC_PLL, /* PLL */ -}; - -static int freq = STM32_MSI_CLOCK; -static int current_osc; - -int clock_get_freq(void) -{ - return freq; -} - -int clock_get_timer_freq(void) -{ - return clock_get_freq(); -} - -void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) -{ - volatile uint32_t unused __attribute__((unused)); - - if (bus == BUS_AHB) { - while (cycles--) - unused = STM32_DMA1_REGS->isr; - } else { /* APB */ - while (cycles--) - unused = STM32_USART_BRR(STM32_USART1_BASE); - } -} - -static void clock_enable_osc(enum clock_osc osc) -{ - uint32_t ready; - uint32_t on; - - switch (osc) { - case OSC_HSI: - ready = STM32_RCC_CR_HSIRDY; - on = STM32_RCC_CR_HSION; - break; - case OSC_MSI: - ready = STM32_RCC_CR_MSIRDY; - on = STM32_RCC_CR_MSION; - break; -#ifdef STM32_HSE_CLOCK - case OSC_HSE: -#ifdef STM32_HSE_BYP - STM32_RCC_CR |= STM32_RCC_CR_HSEBYP; -#endif - ready = STM32_RCC_CR_HSERDY; - on = STM32_RCC_CR_HSEON; - break; -#endif - case OSC_PLL: - ready = STM32_RCC_CR_PLLRDY; - on = STM32_RCC_CR_PLLON; - break; - default: - return; - } - - /* Enable HSI and wait for HSI to be ready */ - wait_for_ready(&STM32_RCC_CR, on, ready); -} - -/* Switch system clock oscillator */ -static void clock_switch_osc(enum clock_osc osc) -{ - uint32_t sw; - uint32_t sws; - uint32_t val; - - switch (osc) { - case OSC_HSI: - sw = STM32_RCC_CFGR_SW_HSI; - sws = STM32_RCC_CFGR_SWS_HSI; - break; - case OSC_MSI: - sw = STM32_RCC_CFGR_SW_MSI; - sws = STM32_RCC_CFGR_SWS_MSI; - break; -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - sw = STM32_RCC_CFGR_SW_HSE; - sws = STM32_RCC_CFGR_SWS_HSE; - break; -#endif - case OSC_PLL: - sw = STM32_RCC_CFGR_SW_PLL; - sws = STM32_RCC_CFGR_SWS_PLL; - break; - default: - return; - } - val = STM32_RCC_CFGR; - val &= ~STM32_RCC_CFGR_SW; - val |= sw; - STM32_RCC_CFGR = val; - while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != sws) - ; -} - -/* - * Configure PLL for HSE - * - * 1. Disable the PLL by setting PLLON to 0 in RCC_CR. - * 2. Wait until PLLRDY is cleared. The PLL is now fully stopped. - * 3. Change the desired parameter. - * 4. Enable the PLL again by setting PLLON to 1. - * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN - * in RCC_PLLCFGR. - */ -static int stm32_configure_pll(enum clock_osc osc, - uint8_t m, uint8_t n, uint8_t r) -{ - uint32_t val; - bool pll_unchanged; - int f; - - val = STM32_RCC_PLLCFGR; - pll_unchanged = true; - - if (osc == OSC_HSI) - if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) != - STM32_RCC_PLLCFGR_PLLSRC_HSI) - pll_unchanged = false; - - if (osc == OSC_MSI) - if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) != - STM32_RCC_PLLCFGR_PLLSRC_MSI) - pll_unchanged = false; - -#ifdef STM32_HSE_CLOCK - if (osc == OSC_HSE) - if ((val & STM32_RCC_PLLCFGR_PLLSRC_MSK) != - STM32_RCC_PLLCFGR_PLLSRC_HSE) - pll_unchanged = false; -#endif - - if ((val & STM32_RCC_PLLCFGR_PLLM_MSK) != - ((m - 1) << STM32_RCC_PLLCFGR_PLLM_POS)) - pll_unchanged = false; - - if ((val & STM32_RCC_PLLCFGR_PLLN_MSK) != - (n << STM32_RCC_PLLCFGR_PLLN_POS)) - pll_unchanged = false; - - if ((val & STM32_RCC_PLLCFGR_PLLR_MSK) != - (((r >> 1) - 1) << STM32_RCC_PLLCFGR_PLLR_POS)) - pll_unchanged = false; - - if (pll_unchanged == true) { - if (osc == OSC_HSI) - f = STM32_HSI_CLOCK; - else - f = STM32_MSI_CLOCK; - - if (!(STM32_RCC_CR & STM32_RCC_CR_PLLRDY)) { - STM32_RCC_CR |= STM32_RCC_CR_PLLON; - STM32_RCC_PLLCFGR |= STM32_RCC_PLLCFGR_PLLREN; - - while ((STM32_RCC_CR & STM32_RCC_CR_PLLRDY) == 0) - ; - } - /* (f * n) shouldn't overflow based on their max values */ - return (f * n / m / r); - } - /* 1 */ - STM32_RCC_CR &= ~STM32_RCC_CR_PLLON; - - /* 2 */ - while (STM32_RCC_CR & STM32_RCC_CR_PLLRDY) - ; - - /* 3 */ - val = STM32_RCC_PLLCFGR; - - val &= ~STM32_RCC_PLLCFGR_PLLSRC_MSK; - switch (osc) { - case OSC_HSI: - val |= STM32_RCC_PLLCFGR_PLLSRC_HSI; - f = STM32_HSI_CLOCK; - break; - case OSC_MSI: - val |= STM32_RCC_PLLCFGR_PLLSRC_MSI; - f = STM32_MSI_CLOCK; - break; -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - val |= STM32_RCC_PLLCFGR_PLLSRC_HSE; - f = STM32_HSE_CLOCK; - break; -#endif - default: - return -1; - } - - ASSERT(m > 0 && m < 9); - val &= ~STM32_RCC_PLLCFGR_PLLM_MSK; - val |= (m - 1) << STM32_RCC_PLLCFGR_PLLM_POS; - - /* Max and min values are from TRM */ - ASSERT(n > 7 && n < 87); - val &= ~STM32_RCC_PLLCFGR_PLLN_MSK; - val |= n << STM32_RCC_PLLCFGR_PLLN_POS; - - val &= ~STM32_RCC_PLLCFGR_PLLR_MSK; - switch (r) { - case 2: - val |= 0 << STM32_RCC_PLLCFGR_PLLR_POS; - break; - case 4: - val |= 1 << STM32_RCC_PLLCFGR_PLLR_POS; - break; - case 6: - val |= 2 << STM32_RCC_PLLCFGR_PLLR_POS; - break; - case 8: - val |= 3 << STM32_RCC_PLLCFGR_PLLR_POS; - break; - default: - return -1; - } - - STM32_RCC_PLLCFGR = val; - - /* 4 */ - clock_enable_osc(OSC_PLL); - - /* 5 */ - val = STM32_RCC_PLLCFGR; - val |= 1 << STM32_RCC_PLLCFGR_PLLREN_POS; - STM32_RCC_PLLCFGR = val; - - /* (f * n) shouldn't overflow based on their max values */ - return (f * n / m / r); -} - -/** - * Set system clock oscillator - * - * @param osc Oscillator to use - * @param pll_osc Source oscillator for PLL. Ignored if osc is not PLL. - */ -static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) -{ - uint32_t val; - - if (osc == current_osc) - return; - - if (current_osc != OSC_INIT) - hook_notify(HOOK_PRE_FREQ_CHANGE); - - switch (osc) { - case OSC_HSI: - /* Ensure that HSI is ON */ - clock_enable_osc(osc); - - /* Set HSI as system clock after exiting stop mode */ - STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK; - - /* Switch to HSI */ - clock_switch_osc(osc); - - /* Disable MSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_MSION; - - freq = STM32_HSI_CLOCK; - break; - - case OSC_MSI: - /* Switch to MSI @ 1MHz */ - STM32_RCC_CR = - (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | - STM32_RCC_ICSCR_MSIRANGE_1MHZ; - /* Ensure that MSI is ON */ - clock_enable_osc(osc); - - /* - * Set MSI as system clock after exiting stop mode - */ - STM32_RCC_CFGR &= ~STM32_RCC_CFGR_STOPWUCK; - - /* Switch to MSI */ - clock_switch_osc(osc); - - /* Disable HSI */ - STM32_RCC_CR &= ~STM32_RCC_CR_HSION; - - freq = STM32_MSI_CLOCK; - break; - -#ifdef STM32_HSE_CLOCK - case OSC_HSE: - /* Ensure that HSE is stable */ - clock_enable_osc(osc); - - /* Switch to HSE */ - clock_switch_osc(osc); - - /* Disable other clock sources */ - STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION | - STM32_RCC_CR_PLLON); - - freq = STM32_HSE_CLOCK; - - break; -#endif - case OSC_PLL: - /* Ensure that source clock is stable */ - if (pll_osc == OSC_INIT) { - if ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MSK) != - STM32_RCC_CFGR_SWS_PLL) { - STM32_RCC_CFGR |= STM32_RCC_CFGR_STOPWUCK; - clock_enable_osc(OSC_HSI); - freq = stm32_configure_pll(OSC_HSI, STM32_PLLM, - STM32_PLLN, - STM32_PLLR); - } else { - /* already set PLL, skip */ - freq = STM32_HSI_CLOCK * STM32_PLLN / - STM32_PLLM / STM32_PLLR; - break; - } - } else { - clock_enable_osc(pll_osc); - /* Configure PLLCFGR */ - freq = stm32_configure_pll(pll_osc, STM32_PLLM, - STM32_PLLN, STM32_PLLR); - } - ASSERT(freq > 0); - - /* Change to Range 1 if Freq > 26MHz */ - if (freq > 26000000U) { - /* Set VCO range 1 */ - val = STM32_RCC_CR; - val &= ~PWR_CR1_VOS_MSK; - val |= PWR_CR1_VOS_0; - STM32_RCC_CR = val; - - /* - * Set Flash latency according to frequency - */ - val = STM32_FLASH_ACR; - val &= ~STM32_FLASH_ACR_LATENCY_MASK; - if (freq <= 16000000U) { - val = val; - } else if (freq <= 32000000U) { - val |= 1; - } else if (freq <= 48000000U) { - val |= 2; - } else if (freq <= 64000000U) { - val |= 3; - } else if (freq <= 80000000U) { - val |= 4; - } else { - val |= 4; - CPUTS("Incorrect Frequency setting in VOS1!\n"); - } - STM32_FLASH_ACR = val; - } else { - val = STM32_FLASH_ACR; - val &= ~STM32_FLASH_ACR_LATENCY_MASK; - - if (freq <= 6000000U) { - val = val; - } else if (freq <= 12000000U) { - val |= 1; - } else if (freq <= 18000000U) { - val |= 2; - } else if (freq <= 26000000U) { - val |= 3; - } else { - val |= 4; - CPUTS("Incorrect Frequency setting in VOS2!\n"); - } - STM32_FLASH_ACR = val; - } - - while (val != STM32_FLASH_ACR) - ; - - /* Switch to PLL */ - clock_switch_osc(osc); - - /* TODO: Disable other sources */ - break; - default: - break; - } - - /* Notify modules of frequency change unless we're initializing */ - if (current_osc != OSC_INIT) { - current_osc = osc; - hook_notify(HOOK_FREQ_CHANGE); - } else { - current_osc = osc; - } -} - -static uint64_t clock_mask; - -void clock_enable_module(enum module_id module, int enable) -{ - uint64_t new_mask; - - if (enable) - new_mask = clock_mask | BIT_ULL(module); - else - new_mask = clock_mask & ~BIT_ULL(module); - - /* Only change clock if needed */ - if (new_mask != clock_mask) { - if (module == MODULE_ADC) { - STM32_RCC_APB2ENR |= STM32_RCC_PB2_SYSCFGEN; - STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_PWREN; - - /* ADC select bit 28/29 */ - STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK; - STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 | - STM32_RCC_CCIPR_ADCSEL_1); - /* ADC clock enable */ - if (enable) - STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1; - else - STM32_RCC_AHB2ENR &= ~STM32_RCC_HB2_ADC1; - } else if (module == MODULE_SPI_FLASH) { - if (enable) - STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; - else - STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2; - } else if (module == MODULE_SPI || - module == MODULE_SPI_CONTROLLER) { - if (enable) - STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN; - else if ((new_mask & (BIT(MODULE_SPI) | - BIT(MODULE_SPI_CONTROLLER))) == 0) - STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN; - } else if (module == MODULE_USB) { -#if defined(STM32_RCC_APB1ENR2_USBFSEN) - if (enable) - STM32_RCC_APB1ENR2 |= - STM32_RCC_APB1ENR2_USBFSEN; - else - STM32_RCC_APB1ENR2 &= - ~STM32_RCC_APB1ENR2_USBFSEN; -#endif - } - } - - clock_mask = new_mask; -} - -int clock_is_module_enabled(enum module_id module) -{ - return !!(clock_mask & BIT_ULL(module)); -} - -void rtc_init(void) -{ - /* Enable RTC Alarm in EXTI */ - STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; - task_enable_irq(STM32_IRQ_RTC_ALARM); - - /* RTC was initilized, avoid initialization again */ - if (STM32_RTC_ISR & STM32_RTC_ISR_INITS) - return; - - rtc_unlock_regs(); - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) - ; - - /* Enable RTC alarm interrupt */ - STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; - - rtc_lock_regs(); -} - -#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) -void rtc_set(uint32_t sec) -{ - struct rtc_time_reg rtc; - - sec_to_rtc(sec, &rtc); - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - - /* Enter RTC initialize mode */ - STM32_RTC_ISR |= STM32_RTC_ISR_INIT; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) - ; - - /* Set clock prescalars */ - STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; - - STM32_RTC_TR = rtc.rtc_tr; - STM32_RTC_DR = rtc.rtc_dr; - /* Start RTC timer */ - STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; - - rtc_lock_regs(); -} -#endif - - -void clock_init(void) -{ -#ifdef STM32_HSE_CLOCK - clock_set_osc(OSC_PLL, OSC_HSE); -#else -#ifdef STM32_USE_PLL - clock_set_osc(OSC_PLL, OSC_INIT); -#else - clock_set_osc(OSC_HSI, OSC_INIT); -#endif -#endif - -#ifdef CONFIG_LOW_POWER_IDLE - low_power_init(); - rtc_init(); -#endif -} - -static void clock_chipset_startup(void) -{ - /* Return to full speed */ - clock_enable_module(MODULE_CHIPSET, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, clock_chipset_startup, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_RESUME, clock_chipset_startup, HOOK_PRIO_DEFAULT); - -static void clock_chipset_shutdown(void) -{ - /* Drop to lower clock speed if no other module requires full speed */ - clock_enable_module(MODULE_CHIPSET, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT); - -static int command_clock(int argc, char **argv) -{ - if (argc >= 2) { - if (!strcasecmp(argv[1], "hsi")) - clock_set_osc(OSC_HSI, OSC_INIT); - else if (!strcasecmp(argv[1], "msi")) - clock_set_osc(OSC_MSI, OSC_INIT); -#ifdef STM32_HSE_CLOCK - else if (!strcasecmp(argv[1], "hse")) - clock_set_osc(OSC_HSE, OSC_INIT); - else if (!strcasecmp(argv[1], "pll")) - clock_set_osc(OSC_PLL, OSC_HSE); -#else - else if (!strcasecmp(argv[1], "pll")) - clock_set_osc(OSC_PLL, OSC_HSI); -#endif - else - return EC_ERROR_PARAM1; - } - - ccprintf("Clock frequency is now %d Hz\n", freq); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | msi" -#ifdef STM32_HSE_CLOCK - " | hse | pll" -#endif - , - "Set clock frequency"); - -uint32_t rtcss_to_us(uint32_t rtcss) -{ - return ((RTC_PREDIV_S - (rtcss & 0x7FFF)) * (SECOND / SCALING) / - (RTC_FREQ / SCALING)); -} - -uint32_t us_to_rtcss(uint32_t us) -{ - return (RTC_PREDIV_S - - (us * (RTC_FREQ / SCALING) / (SECOND / SCALING))); -} - - -/* Convert decimal to BCD */ -static uint8_t u8_to_bcd(uint8_t val) -{ - /* Fast division by 10 (when lacking HW div) */ - uint32_t quot = ((uint32_t)val * 0xCCCD) >> 19; - uint32_t rem = val - quot * 10; - - return rem | (quot << 4); -} - -/* Convert between RTC regs in BCD and seconds */ -static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) -{ - uint32_t sec; - - /* convert the hours field */ - sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 + - ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600; - /* convert the minutes field */ - sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 + - ((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60; - /* convert the seconds field */ - sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 + - (rtc_tr & RTC_TR_SU); - return sec; -} - -static uint32_t sec_to_rtc_tr(uint32_t sec) -{ - uint32_t rtc_tr; - uint8_t hour; - uint8_t min; - - sec %= SECS_PER_DAY; - /* convert the hours field */ - hour = sec / 3600; - rtc_tr = u8_to_bcd(hour) << 16; - /* convert the minutes field */ - sec -= hour * 3600; - min = sec / 60; - rtc_tr |= u8_to_bcd(min) << 8; - /* convert the seconds field */ - sec -= min * 60; - rtc_tr |= u8_to_bcd(sec); - - return rtc_tr; -} - -/* Register setup before RTC alarm is allowed for update */ -static void pre_work_set_rtc_alarm(void) -{ - rtc_unlock_regs(); - - /* Make sure alarm is disabled */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF)) - ; - STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; - STM32_EXTI_PR = BIT(18); -} - -/* Register setup after RTC alarm is updated */ -static void post_work_set_rtc_alarm(void) -{ - /* Enable alarm and alarm interrupt */ - STM32_EXTI_IMR |= BIT(18); - STM32_EXTI_RTSR |= BIT(18); - STM32_RTC_CR |= (STM32_RTC_CR_ALRAE); - - rtc_lock_regs(); -} - -#ifdef CONFIG_HOSTCMD_RTC -static struct wake_time host_wake_time; - -bool is_host_wake_alarm_expired(timestamp_t ts) -{ - return host_wake_time.ts.val && - timestamp_expired(host_wake_time.ts, &ts); -} - -void restore_host_wake_alarm(void) -{ - if (!host_wake_time.ts.val) - return; - - pre_work_set_rtc_alarm(); - - /* Set alarm time */ - STM32_RTC_ALRMAR = host_wake_time.rtc_alrmar; - - post_work_set_rtc_alarm(); -} - -static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) -{ - struct calendar_date time; - uint32_t sec; - - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); - time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); - - sec = date_to_sec(time); - - return sec; -} - -static uint32_t sec_to_rtc_dr(uint32_t sec) -{ - struct calendar_date time; - uint32_t rtc_dr; - - time = sec_to_date(sec); - - rtc_dr = u8_to_bcd(time.year) << 16; - rtc_dr |= u8_to_bcd(time.month) << 8; - rtc_dr |= u8_to_bcd(time.day); - - return rtc_dr; -} -#endif - -uint32_t rtc_to_sec(const struct rtc_time_reg *rtc) -{ - uint32_t sec = 0; - -#ifdef CONFIG_HOSTCMD_RTC - sec = rtc_dr_to_sec(rtc->rtc_dr); -#endif - return sec + (rtcss_to_us(rtc->rtc_ssr) / SECOND) + - rtc_tr_to_sec(rtc->rtc_tr); -} - -void sec_to_rtc(uint32_t sec, struct rtc_time_reg *rtc) -{ - rtc->rtc_dr = 0; -#ifdef CONFIG_HOSTCMD_RTC - rtc->rtc_dr = sec_to_rtc_dr(sec); -#endif - rtc->rtc_tr = sec_to_rtc_tr(sec); - rtc->rtc_ssr = 0; -} - -/* Return sub-10-sec time diff between two rtc readings - * - * Note: this function assumes rtc0 was sampled before rtc1. - * Additionally, this function only looks at the difference mod 10 - * seconds. - */ -uint32_t get_rtc_diff(const struct rtc_time_reg *rtc0, - const struct rtc_time_reg *rtc1) -{ - uint32_t rtc0_val, rtc1_val, diff; - - rtc0_val = (rtc0->rtc_tr & RTC_TR_SU) * SECOND + - rtcss_to_us(rtc0->rtc_ssr); - rtc1_val = (rtc1->rtc_tr & RTC_TR_SU) * SECOND + - rtcss_to_us(rtc1->rtc_ssr); - diff = rtc1_val; - if (rtc1_val < rtc0_val) { - /* rtc_ssr has wrapped, since we assume rtc0 < rtc1, add - * 10 seconds to get the correct value - */ - diff += 10 * SECOND; - } - diff -= rtc0_val; - return diff; -} - -void rtc_read(struct rtc_time_reg *rtc) -{ - /* - * Read current time synchronously. Each register must be read - * twice with identical values because glitches may occur for reads - * close to the RTCCLK edge. - */ - do { - rtc->rtc_dr = STM32_RTC_DR; - - do { - rtc->rtc_tr = STM32_RTC_TR; - - do { - rtc->rtc_ssr = STM32_RTC_SSR; - } while (rtc->rtc_ssr != STM32_RTC_SSR); - - } while (rtc->rtc_tr != STM32_RTC_TR); - - } while (rtc->rtc_dr != STM32_RTC_DR); -} - -void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, - struct rtc_time_reg *rtc, uint8_t save_alarm) -{ - uint32_t alarm_sec = 0; - uint32_t alarm_us = 0; - - if (delay_s == EC_RTC_ALARM_CLEAR && !delay_us) { - reset_rtc_alarm(rtc); - return; - } - - /* Alarm timeout must be within 1 day (86400 seconds) */ - ASSERT((delay_s + delay_us / SECOND) < SECS_PER_DAY); - - pre_work_set_rtc_alarm(); - rtc_read(rtc); - - /* Calculate alarm time */ - alarm_sec = rtc_tr_to_sec(rtc->rtc_tr) + delay_s; - - if (delay_us) { - alarm_us = rtcss_to_us(rtc->rtc_ssr) + delay_us; - alarm_sec = alarm_sec + alarm_us / SECOND; - alarm_us = alarm_us % SECOND; - } - - /* - * If seconds is greater than 1 day, subtract by 1 day to deal with - * 24-hour rollover. - */ - if (alarm_sec >= SECS_PER_DAY) - alarm_sec -= SECS_PER_DAY; - - /* - * Set alarm time in seconds and check for match on - * hours, minutes, and seconds. - */ - STM32_RTC_ALRMAR = sec_to_rtc_tr(alarm_sec) | 0xc0000000; - - /* - * Set alarm time in subseconds and check for match on subseconds. - * If the caller doesn't specify subsecond delay (e.g. host command), - * just align the alarm time to second. - */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; - -#ifdef CONFIG_HOSTCMD_RTC - /* - * If alarm is set by the host, preserve the wake time timestamp - * and alarm registers. - */ - if (save_alarm) { - host_wake_time.ts.val = delay_s * SECOND + get_time().val; - host_wake_time.rtc_alrmar = STM32_RTC_ALRMAR; - } -#endif - post_work_set_rtc_alarm(); -} - -uint32_t get_rtc_alarm(void) -{ - struct rtc_time_reg now; - uint32_t now_sec; - uint32_t alarm_sec; - - if (!(STM32_RTC_CR & STM32_RTC_CR_ALRAE)) - return 0; - - rtc_read(&now); - - now_sec = rtc_tr_to_sec(now.rtc_tr); - alarm_sec = rtc_tr_to_sec(STM32_RTC_ALRMAR & 0x3fffff); - - return ((alarm_sec < now_sec) ? SECS_PER_DAY : 0) + - (alarm_sec - now_sec); -} - -void reset_rtc_alarm(struct rtc_time_reg *rtc) -{ - rtc_unlock_regs(); - - /* Disable alarm */ - STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; - STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; - - /* Disable RTC alarm interrupt */ - STM32_EXTI_IMR &= ~BIT(18); - STM32_EXTI_PR = BIT(18); - - /* Clear the pending RTC alarm IRQ in NVIC */ - task_clear_pending_irq(STM32_IRQ_RTC_ALARM); - - /* Read current time */ - rtc_read(rtc); - - rtc_lock_regs(); -} - -#ifdef CONFIG_HOSTCMD_RTC -static void set_rtc_host_event(void) -{ - host_set_single_event(EC_HOST_EVENT_RTC); -} -DECLARE_DEFERRED(set_rtc_host_event); -#endif - -test_mockable -void __rtc_alarm_irq(void) -{ - struct rtc_time_reg rtc; - - reset_rtc_alarm(&rtc); - -#ifdef CONFIG_HOSTCMD_RTC - /* Wake up the host if there is a saved rtc wake alarm. */ - if (host_wake_time.ts.val) { - host_wake_time.ts.val = 0; - hook_call_deferred(&set_rtc_host_event_data, 0); - } -#endif -} -DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); - - -void print_system_rtc(enum console_channel ch) -{ - uint32_t sec; - struct rtc_time_reg rtc; - - rtc_read(&rtc); - sec = rtc_to_sec(&rtc); - - cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec); -} - - -#ifdef CONFIG_LOW_POWER_IDLE -/* Low power idle statistics */ -static int idle_sleep_cnt; -static int idle_dsleep_cnt; -static uint64_t idle_dsleep_time_us; -static int dsleep_recovery_margin_us = 1000000; - -/* STOP_MODE_LATENCY: delay to wake up from STOP mode with main regulator off */ -#define STOP_MODE_LATENCY 50 /* us */ -/* PLL_LOCK_LATENCY: delay to switch from HSI to PLL */ -#define PLL_LOCK_LATENCY 150 /* us */ -/* - * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm - * in the past, it will never wake up and cause a watchdog. - */ -#define SET_RTC_MATCH_DELAY 120 /* us */ - - -void low_power_init(void) -{ - /* Enter stop1 mode */ - uint32_t val; - - val = STM32_PWR_CR1; - val &= ~PWR_CR1_LPMS_MSK; - val |= PWR_CR1_LPMS_STOP1; - STM32_PWR_CR1 = val; -} - -void clock_refresh_console_in_use(void) -{ -} - -void __idle(void) -{ - timestamp_t t0; - uint32_t rtc_diff; - int next_delay, margin_us; - struct rtc_time_reg rtc0, rtc1; - - while (1) { - asm volatile("cpsid i"); - - t0 = get_time(); - next_delay = __hw_clock_event_get() - t0.le.lo; - - if (DEEP_SLEEP_ALLOWED && - (next_delay > (STOP_MODE_LATENCY + PLL_LOCK_LATENCY + - SET_RTC_MATCH_DELAY))) { - /* Deep-sleep in STOP mode */ - idle_dsleep_cnt++; - - uart_enable_wakeup(1); - - /* Set deep sleep bit */ - CPU_SCB_SYSCTRL |= 0x4; - - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY - - PLL_LOCK_LATENCY, - &rtc0, 0); - - - /* ensure outstanding memory transactions complete */ - asm volatile("dsb"); - - asm("wfi"); - - CPU_SCB_SYSCTRL &= ~0x4; - - /* turn on PLL and wait until it's ready */ - STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN; - clock_wait_bus_cycles(BUS_APB, 2); - - stm32_configure_pll(OSC_HSI, STM32_PLLM, - STM32_PLLN, STM32_PLLR); - - /* Switch to PLL */ - clock_switch_osc(OSC_PLL); - - uart_enable_wakeup(0); - - /* Fast forward timer according to RTC counter */ - reset_rtc_alarm(&rtc1); - rtc_diff = get_rtc_diff(&rtc0, &rtc1); - t0.val = t0.val + rtc_diff; - force_time(t0); - - /* Record time spent in deep sleep. */ - idle_dsleep_time_us += rtc_diff; - - /* Calculate how close we were to missing deadline */ - margin_us = next_delay - rtc_diff; - if (margin_us < 0) - /* Use CPUTS to save stack space */ - CPUTS("Idle overslept!\n"); - - /* Record the closest to missing a deadline. */ - if (margin_us < dsleep_recovery_margin_us) - dsleep_recovery_margin_us = margin_us; - } else { - idle_sleep_cnt++; - - /* Normal idle : only CPU clock stopped */ - asm("wfi"); - } - asm volatile("cpsie i"); - } -} - -/*****************************************************************************/ -/* Console commands */ -/* Print low power idle statistics. */ -static int command_idle_stats(int argc, char **argv) -{ - timestamp_t ts = get_time(); - - ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); - ccprintf("Time spent in deep-sleep: %.6llus\n", - idle_dsleep_time_us); - ccprintf("Total time on: %.6llus\n", ts.val); - ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); -#endif /* CONFIG_LOW_POWER_IDLE */ diff --git a/chip/stm32/clock-stm32l5.c b/chip/stm32/clock-stm32l5.c deleted file mode 100644 index 63f5b874bc..0000000000 --- a/chip/stm32/clock-stm32l5.c +++ /dev/null @@ -1,6 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock-stm32l4.c" diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h deleted file mode 100644 index 3c51086c26..0000000000 --- a/chip/stm32/config-stm32f03x.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifdef CHIP_VARIANT_STM32F03X8 -#define CONFIG_FLASH_SIZE_BYTES 0x00010000 -#define CONFIG_RAM_SIZE 0x00002000 -#else -#define CONFIG_FLASH_SIZE_BYTES 0x00008000 -#define CONFIG_RAM_SIZE 0x00001000 -#endif - -/* Memory mapping */ -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h deleted file mode 100644 index 00bf45fde5..0000000000 --- a/chip/stm32/config-stm32f05x.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (64 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h deleted file mode 100644 index 918a117a22..0000000000 --- a/chip/stm32/config-stm32f07x.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* Reduced history because of limited RAM */ -#undef CONFIG_CONSOLE_HISTORY -#define CONFIG_CONSOLE_HISTORY 3 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 -#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t -#define CONFIG_USB_RAM_ACCESS_SIZE 2 diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h deleted file mode 100644 index 9dc27a1fb2..0000000000 --- a/chip/stm32/config-stm32f09x.h +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -/* - * Flash physical size: 256KB - * Write protect sectors: 31 4KB sectors, one 132KB sector - */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 32 - -/* - * STM32F09x flash layout: - * - RO image starts at the beginning of flash: sector 0 ~ 29 - * - PSTATE immediately follows the RO image: sector 30 - * - RW image starts at 0x1f00: sector 31 - * - Protected region consists of the RO image + PSTATE: sector 0 ~ 30 - * - Unprotected region consists of second half of RW image - * - * PSTATE(4KB) - * | - * (124KB) v (132KB) - * |<-----Protected Region------>|<------Unprotected Region----->| - * |<--------RO image--------->| |<----------RW image----------->| - * 0 (120KB) ^ ^ - * | | - * | 31(132KB sector) - * | - * 30 - * - */ - -#define _SECTOR_4KB (4 * 1024) -#define _SECTOR_132KB (132 * 1024) - -/* The EC uses one sector to emulate persistent state */ -#define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB -#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE _SECTOR_132KB - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 32 -#define WP_BANK_COUNT 31 -#define PSTATE_BANK 30 -#define PSTATE_BANK_COUNT 1 - diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h deleted file mode 100644 index 3df5bfce67..0000000000 --- a/chip/stm32/config-stm32f373.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x2000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 81 - -/* STM32F3 uses the older 4 byte aligned access mechanism */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h deleted file mode 100644 index 73c9a3694f..0000000000 --- a/chip/stm32/config-stm32f4.h +++ /dev/null @@ -1,72 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) -#else -# define CONFIG_FLASH_SIZE_BYTES (512 * 1024) -#endif - -/* 3 regions type: 16K, 64K and 128K */ -#define SIZE_16KB (16 * 1024) -#define SIZE_64KB (64 * 1024) -#define SIZE_128KB (128 * 1024) -#define CONFIG_FLASH_REGION_TYPE_COUNT 3 -#define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB) - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* minimum write size for 3.3V. 1 for 1.8V */ -#define STM32_FLASH_WRITE_SIZE_1800 1 -#define STM32_FLASH_WS_DIV_1800 16000000 -#define STM32_FLASH_WRITE_SIZE_3300 4 -#define STM32_FLASH_WS_DIV_3300 30000000 - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE - -#ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ -#else -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ -#endif - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (256 * 1024) -#define CONFIG_RW_MEM_OFF (256 * 1024) -#define CONFIG_RW_SIZE (256 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Use OTP regions */ -#define CONFIG_OTP - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 97 - -#undef CONFIG_CMD_CHARGEN diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h deleted file mode 100644 index d027ad62fb..0000000000 --- a/chip/stm32/config-stm32f76x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) - -/* 3 regions type: 32K, 128K and 256K */ -#define SIZE_32KB (32 * 1024) -#define SIZE_128KB (128 * 1024) -#define SIZE_256KB (256 * 1024) -#define CONFIG_FLASH_REGION_TYPE_COUNT 3 -#define CONFIG_FLASH_MULTIPLE_REGION \ - (5 + (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB) - -/* Erasing 256K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* minimum write size for 3.3V. 1 for 1.8V */ -#define STM32_FLASH_WRITE_SIZE_1800 1 -#define STM32_FLASH_WS_DIV_1800 16000000 -#define STM32_FLASH_WRITE_SIZE_3300 4 -#define STM32_FLASH_WS_DIV_3300 30000000 - -/* No page mode on STM32F, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE - -/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/ -/* SRAM1: 368kB 0x20020000 - 0x2007BFFF */ -/* SRAM2: 16kB 0x2007C000 - 0x2007FFFF */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00080000 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (1024 * 1024) -#define CONFIG_RW_MEM_OFF (1024 * 1024) -#define CONFIG_RW_SIZE (1024 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 109 diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h deleted file mode 100644 index 4f1ed96871..0000000000 --- a/chip/stm32/config-stm32g41xb.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Memory mapping for STM32G431xb. The STM32G431xb is a category 2 device within - * the STM32G4 chip family. Category 2 devices have either 32, 64, or 128 kB of - * internal flash. The 'xB' indicates 128 kB of internal flash. - * - * STM32G431x is a single bank only device consisting of 64 pages of 2 kB - * each. It supports both a mass erase or page erase feature. Note that - * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM - * for the STM32G4 chip family. The minimum erase size is 1 page. - * - * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support - * PSTATE in single bank memories with a write size > 4 bytes. - */ - -#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) -#define CONFIG_FLASH_WRITE_SIZE 0x0004 -#define CONFIG_FLASH_BANK_SIZE (2 * 1024) -#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE - - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* No page mode on STM32G4, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE - -/* - * STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM - * is split into three blocks: - * • 16 Kbytes mapped at address 0x2000 0000 (SRAM1). - * • 6 Kbytes mapped at address 0x2000 4000 (SRAM2). - * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased - * at 0x2000 5800 address to be accessed by all bus controllers. - */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 3 - -/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ -#define DMAC_COUNT 12 - -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 -#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t -#define CONFIG_USB_RAM_ACCESS_SIZE 2 diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h deleted file mode 100644 index 1cb5133121..0000000000 --- a/chip/stm32/config-stm32g473xc.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Memory mapping for STM32G473xc. The STM32G473xc is a category 1 device within - * the STM32G4 chip family. Category 1 devices have either 128, 256, or 512 kB - * of internal flash. 'xc' indicates 256 kB of internal flash. - * - * STM32G473xc can be configured via option bytes as either a single bank or - * dual bank device. Dual bank is the default selection. - * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM - * for the STM32G4 chip family. In dual bank mode, the flash is organized in 2 - * kB pages, with 64 pages per bank for this variant. - * - * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support - * PSTATE in single bank memories with a write size > 4 bytes. - * - * TODO(b/181874494): Verify that dual bank mode should be used, or add support - * for enabling single bank mode on STM32G473xc. - */ -#define CONFIG_FLASH_SIZE_BYTES (256 * 1024) -#define CONFIG_FLASH_WRITE_SIZE 0x0004 -#define CONFIG_FLASH_BANK_SIZE (2 * 1024) -#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE - -/* Dual-bank (DBANK) mode is enabled by default for this chip */ -#define STM32_FLASH_DBANK_MODE - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* No page mode on STM32G4, so no benefit to larger write sizes */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE - -/* - * STM32G473xc is a category 3 SRAM device featuring 128 Kbytes of embedded - * SRAM. This SRAM is split into three blocks: - * • 80 Kbytes mapped at address 0x2000 0000 (SRAM1). - * • 16 Kbytes mapped at address 0x2001 4000 (SRAM2). - * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased - * at 0x2001 8000 address to be accessed by all bus controllers. - */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00020000 - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ -#define DMAC_COUNT 12 - -/* Use PSTATE embedded in the RO image, not in its own erase block */ -#define CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 -#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t -#define CONFIG_USB_RAM_ACCESS_SIZE 2 diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h deleted file mode 100644 index da94b09069..0000000000 --- a/chip/stm32/config-stm32h7x3.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) -#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ -/* always use 256-bit writes due to ECC */ -#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 - -/* - * What the code is calling 'bank' is really the size of the block used for - * write-protected, here it's 128KB sector (same as erase size). - */ -#define CONFIG_FLASH_BANK_SIZE (128 * 1024) - -/* Erasing 128K can take up to 2s, need to defer erase. */ -#define CONFIG_FLASH_DEFERRED_ERASE - -/* ITCM-RAM: 64kB 0x00000000 - 0x0000FFFF (CPU and MDMA) */ -/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF (CPU and MDMA) */ -/* (D1) AXI-SRAM : 512kB 0x24000000 - 0x2407FFFF (no BDMA) */ -/* (D2) AHB-SRAM1: 128kB 0x30000000 - 0x3001FFFF */ -/* (D2) AHB-SRAM2: 128kB 0x30020000 - 0x3003FFFF */ -/* (D2) AHB-SRAM3: 32kB 0x30040000 - 0x30047FFF */ -/* (D3) AHB-SRAM4: 64kB 0x38000000 - 0x3800FFFF */ -/* (D3) backup RAM: 4kB 0x38800000 - 0x38800FFF */ -#define CONFIG_RAM_BASE 0x24000000 -#define CONFIG_RAM_SIZE 0x00080000 - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (512 * 1024) - -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* - * Cannot use PSTATE: - * 128kB blocks are too large and ECC prevents re-writing PSTATE word. - */ -#undef CONFIG_FLASH_PSTATE -#undef CONFIG_FLASH_PSTATE_BANK - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 150 - -/* the Cortex-M7 core has 'standard' ARMv7-M caches */ -#define CONFIG_ARMV7M_CACHE -/* Use the MPU to configure cacheability */ -#define CONFIG_MPU -/* Store in uncached buffers for DMA transfers in ahb4 region */ -#define CONFIG_CHIP_UNCACHED_REGION ahb4 -/* Override MPU attribute settings to match the chip requirements */ -/* Code is Normal memory type / non-shareable / write-through */ -#define MPU_ATTR_FLASH_MEMORY 0x02 -/* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */ -#define MPU_ATTR_INTERNAL_SRAM 0x0B diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h deleted file mode 100644 index 2c4efcc6df..0000000000 --- a/chip/stm32/config-stm32l100.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ - -/* - * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at - * a time), but that's really slow, and older host interfaces which can't ask - * about the ideal size would then end up writing in that mode instead of the - * faster page mode. So lie about the write size for now. Once all software - * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1 - * of EC_CMD_GET_FLASH_INFO, we can remove this workaround. - */ -#define CONFIG_FLASH_WRITE_SIZE 0x0080 - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002800 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 45 - -/* Flash erases to 0, not 1 */ -#define CONFIG_FLASH_ERASED_VALUE32 0 - -/* Use DMA for UART receive */ -#define CONFIG_UART_RX_DMA - -/* Fake hibernate mode */ -#define CONFIG_STM32L_FAKE_HIBERNATE - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h deleted file mode 100644 index 0b32f95572..0000000000 --- a/chip/stm32/config-stm32l15x.h +++ /dev/null @@ -1,44 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ - -/* - * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at - * a time), but that's really slow, and older host interfaces which can't ask - * about the ideal size would then end up writing in that mode instead of the - * faster page mode. So lie about the write size for now. Once all software - * (flashrom, u-boot, ectool) which cares has been updated to know about ver.1 - * of EC_CMD_GET_FLASH_INFO, we can remove this workaround. - */ -#define CONFIG_FLASH_WRITE_SIZE 0x0080 - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 - -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 45 - -/* Lots of RAM, so use bigger UART buffer */ -#undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 - -/* Use DMA for UART receive */ -#define CONFIG_UART_RX_DMA - -/* Flash erases to 0, not 1 */ -#define CONFIG_FLASH_ERASED_VALUE32 0 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h deleted file mode 100644 index 7021bc2ce8..0000000000 --- a/chip/stm32/config-stm32l431.h +++ /dev/null @@ -1,77 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ -#define CONFIG_FLASH_BANK_SIZE \ - 0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ - -/* - * SRAM1 (48kB) at 0x20000000 - * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) - * so they are contiguous. - */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 82 - -/* - * STM32L431 flash layout: - * - RO image starts at the beginning of flash: sector 0 ~ 61 - * - PSTATE immediately follows the RO image: sector 62 - * - RW image starts at 0x1f800: sector 63 - * - Protected region consists of the RO image + PSTATE: sector 0 ~ 62 - * - Unprotected region consists of second half of RW image - * - * PSTATE(2KB) - * | - * (126KB) v (130KB) - * |<-----Protected Region------>|<------Unprotected Region----->| - * |<--------RO image--------->| |<----------RW image----------->| - * 0 (124KB) ^ ^ - * | | - * | 63(2KB sector) - * | - * 62 - * - */ - - - -/* The EC uses one sector to emulate persistent state */ -#define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE) - -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \ - CONFIG_RW_STORAGE_OFF) - -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE - -/* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 128 -#define WP_BANK_COUNT 63 -#define PSTATE_BANK 62 -#define PSTATE_BANK_COUNT 1 diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h deleted file mode 100644 index 54ba9bac8d..0000000000 --- a/chip/stm32/config-stm32l442.h +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ - -/* - * SRAM1 (48kB) at 0x20000000 - * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) - * so they are contiguous. - */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 82 diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h deleted file mode 100644 index 2e0084fd94..0000000000 --- a/chip/stm32/config-stm32l476.h +++ /dev/null @@ -1,20 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ - -#define CONFIG_RAM_BASE 0x20000000 -/* Only using SRAM1. SRAM2 (32 KB) is ignored. */ -#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */ - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 82 diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h deleted file mode 100644 index 6953df3950..0000000000 --- a/chip/stm32/config-stm32l552xe.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ - -/* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ - -/* - * SRAM1 (48kB) at 0x20000000 - * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) - * so they are contiguous. - */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ - -/* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 109 - -/* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x4000D800 -#define CONFIG_USB_RAM_SIZE 1024 -#define CONFIG_USB_RAM_ACCESS_TYPE uint32_t -#define CONFIG_USB_RAM_ACCESS_SIZE 4 - -#undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 - -/* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */ -#define DMAC_COUNT 16 diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h deleted file mode 100644 index 4d630909e1..0000000000 --- a/chip/stm32/config_chip.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CONFIG_CHIP_H -#define __CROS_EC_CONFIG_CHIP_H - -#ifdef CHIP_FAMILY_STM32F0 -/* CPU core BFD configuration */ -#include "core/cortex-m0/config_core.h" -/* IRQ priorities */ -#define STM32_IRQ_EXT0_1_PRIORITY 1 -#define STM32_IRQ_EXT2_3_PRIORITY 1 -#define STM32_IRQ_EXTI4_15_PRIORITY 1 -#else -/* CPU core BFD configuration */ -#include "core/cortex-m/config_core.h" -#define STM32_IRQ_EXTI0_PRIORITY 1 -#define STM32_IRQ_EXTI1_PRIORITY 1 -#define STM32_IRQ_EXTI2_PRIORITY 1 -#define STM32_IRQ_EXTI3_PRIORITY 1 -#define STM32_IRQ_EXTI4_PRIORITY 1 -#define STM32_IRQ_EXTI9_5_PRIORITY 1 -#define STM32_IRQ_EXTI15_10_PRIORITY 1 -#endif - -/* Default to UART 1 for EC console */ -#define CONFIG_UART_CONSOLE 1 - -/* Use variant specific configuration for flash / UART / IRQ */ -/* STM32F03X8 it itself a variant of STM32F03X with non-default flash sizes */ -#ifdef CHIP_VARIANT_STM32F03X8 -#define CHIP_VARIANT_STM32F03X -#endif - -/* Number of I2C ports, can be overridden in variant */ -#define I2C_PORT_COUNT 2 - -#if defined(CHIP_VARIANT_STM32L476) -#include "config-stm32l476.h" -#elif defined(CHIP_VARIANT_STM32L15X) -#include "config-stm32l15x.h" -#elif defined(CHIP_VARIANT_STM32L100) -#include "config-stm32l100.h" -#elif defined(CHIP_VARIANT_STM32L442) -#include "config-stm32l442.h" -#elif defined(CHIP_VARIANT_STM32L552XE) -#include "config-stm32l552xe.h" -#elif defined(CHIP_VARIANT_STM32F76X) -#include "config-stm32f76x.h" -#elif defined(CHIP_FAMILY_STM32F4) -/* STM32F4 family */ -#include "config-stm32f4.h" -#elif defined(CHIP_VARIANT_STM32F373) -#include "config-stm32f373.h" -#elif defined(CHIP_VARIANT_STM32F09X) -/* STM32F09xx */ -#include "config-stm32f09x.h" -#elif defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F070) -/* STM32F07xx */ -#include "config-stm32f07x.h" -#elif defined(CHIP_VARIANT_STM32F05X) -/* STM32F05xx */ -#include "config-stm32f05x.h" -#elif defined(CHIP_VARIANT_STM32F03X) -/* STM32F03x */ -#include "config-stm32f03x.h" -#elif defined(CHIP_VARIANT_STM32H7X3) -#include "config-stm32h7x3.h" -#elif defined(CHIP_VARIANT_STM32G431XB) -#include "config-stm32g41xb.h" -#elif defined(CHIP_VARIANT_STM32G473XC) -#include "config-stm32g473xc.h" -#elif defined(CHIP_VARIANT_STM32L431X) -#include "config-stm32l431.h" -#else -#error "Unsupported chip variant" -#endif - -#define CONFIG_PROGRAM_MEMORY_BASE 0x08000000 - -/* Memory-mapped internal flash */ -#define CONFIG_INTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE - -/* Program is run directly from storage */ -#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE - -#if !defined(CHIP_FAMILY_STM32F4) && \ - !defined(CHIP_FAMILY_STM32F7) && \ - !defined(CHIP_FAMILY_STM32H7) && \ - !defined(CHIP_VARIANT_STM32F09X) && \ - !defined(CHIP_VARIANT_STM32L431X) -/* Compute the rest of the flash params from these */ -#include "config_std_internal_flash.h" -#endif - -/* Additional special purpose regions (USB RAM and other special SRAMs) */ -#define CONFIG_CHIP_MEMORY_REGIONS - -/* System stack size */ -#if defined(CHIP_VARIANT_STM32F05X) -#define CONFIG_STACK_SIZE 768 -#else -#define CONFIG_STACK_SIZE 1024 -#endif - -/* Idle task stack size */ -#define IDLE_TASK_STACK_SIZE 256 - -/* Smaller task stack size */ -#define SMALLER_TASK_STACK_SIZE 384 - -/* Default task stack size */ -#define TASK_STACK_SIZE 512 - -/* Larger task stack size, for hook task */ -#define LARGER_TASK_STACK_SIZE 640 - -/* Even bigger */ -#define VENTI_TASK_STACK_SIZE 768 -#define ULTRA_TASK_STACK_SIZE 1056 -#define TRENTA_TASK_STACK_SIZE 1184 - -/* - * Console stack size. For test builds, the console is used to interact with - * the test, and insufficient stack size causes console stack overflow after - * running the on-device tests. - */ -#define CONSOLE_TASK_STACK_SIZE 4096 - -/* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) - -/* - * Use a timer to print a watchdog warning event before the actual watchdog - * timer fires. This is needed on STM32, where the independent watchdog has no - * early warning feature and the windowed watchdog has a very short period. - */ -#define CONFIG_WATCHDOG_HELP - -/* Use DMA */ -#define CONFIG_DMA - -/* STM32 features RTC (optional feature) */ -#define CONFIG_RTC - -/* Number of peripheral request signals per DMA channel */ -#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4 - -/* - * Use DMA for UART transmit for all platforms. DMA for UART receive is - * enabled on a per-chip basis because it doesn't seem to work reliably on - * STM32F (see crosbug.com/p/24141). - */ -#define CONFIG_UART_TX_DMA - -#ifndef CHIP_FAMILY_STM32H7 -/* Flash protection applies to the next boot, not the current one */ -#define CONFIG_FLASH_PROTECT_NEXT_BOOT -#endif /* !CHIP_FAMILY_STM32H7 */ - -/* Chip needs to do custom pre-init */ -#define CONFIG_CHIP_PRE_INIT - -#define GPIO_NAME_BY_PIN(port, index) #port#index -#define GPIO_PIN(port, index) GPIO_##port, BIT(index) -#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) - -/* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */ -#define STM32_PLLM 1 -#define STM32_PLLN 1 -#define STM32_PLLR 1 - -#endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h deleted file mode 100644 index 2a50d5760e..0000000000 --- a/chip/stm32/crc_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CRC_HW_H -#define __CROS_EC_CRC_HW_H -/* CRC-32 hardware implementation with USB constants */ - -#include "clock.h" -#include "registers.h" - -static inline void crc32_init(void) -{ - /* switch on CRC controller */ - STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */ - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); - /* reset CRC state */ - STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT - | STM32_CRC_CR_REV_IN_WORD; - while (STM32_CRC_CR & 1) - ; -} - -static inline void crc32_hash32(uint32_t val) -{ - STM32_CRC_DR = val; -} - -static inline void crc32_hash16(uint16_t val) -{ - STM32_CRC_DR16 = val; -} - -static inline uint32_t crc32_result(void) -{ - return STM32_CRC_DR ^ 0xFFFFFFFF; -} - -#endif /* __CROS_EC_CRC_HW_H */ diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c deleted file mode 100644 index c4e151692c..0000000000 --- a/chip/stm32/debug_printf.c +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Synchronous UART debug printf */ - -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "printf.h" -#include "registers.h" -#include "util.h" - -static int debug_txchar(void *context, int c) -{ - if (c == '\n') { - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE)) - ; - STM32_USART_TDR(UARTN_BASE) = '\r'; - } - - /* Wait for space to transmit */ - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE)) - ; - STM32_USART_TDR(UARTN_BASE) = c; - - return 0; -} - - - -void debug_printf(const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); -} - -#ifdef CONFIG_COMMON_RUNTIME -void cflush(void) -{ - /* Wait for transmit complete */ - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC)) - ; -} - -int cputs(enum console_channel channel, const char *outstr) -{ - debug_printf(outstr); - - return 0; -} - -void panic_puts(const char *outstr) -{ - debug_printf(outstr); - cflush(); -} - -int cprintf(enum console_channel channel, const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); - - return 0; -} - -void panic_printf(const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); - - cflush(); -} - -int cprints(enum console_channel channel, const char *format, ...) -{ - va_list args; - - va_start(args, format); - vfnprintf(debug_txchar, NULL, format, args); - va_end(args); - - debug_printf("\n"); - - return 0; -} - -void uart_init(void) -{ - /* Enable USART1 clock */ - STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1; - /* set baudrate */ - STM32_USART_BRR(UARTN_BASE) = - DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE); - /* UART enabled, 8 Data bits, oversampling x16, no parity */ - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; - /* 1 stop bit, no fancy stuff */ - STM32_USART_CR2(UARTN_BASE) = 0x0000; - /* DMA disabled, special modes disabled, error interrupt disabled */ - STM32_USART_CR3(UARTN_BASE) = 0x0000; - - /* Configure GPIOs */ - gpio_config_module(MODULE_UART, 1); -} -#endif diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h deleted file mode 100644 index 6091cfc7fc..0000000000 --- a/chip/stm32/debug_printf.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Synchronous UART debug printf */ - -#ifndef __CROS_EC_DEBUG_H -#define __CROS_EC_DEBUG_H - -#ifdef CONFIG_DEBUG_PRINTF -__attribute__((__format__(__printf__, 1, 2))) -void debug_printf(const char *format, ...); -#else -#define debug_printf(...) -#endif - -#endif /* __CROS_EC_DEBUG_H */ diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c deleted file mode 100644 index 860874de8c..0000000000 --- a/chip/stm32/dma-stm32f4.c +++ /dev/null @@ -1,334 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) - -stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS }; - -/* Callback data to use when IRQ fires */ -static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ -} dma_irq[STM32_DMAS_TOTAL_COUNT]; - -/** - * Return the IRQ for the DMA stream - * - * @param stream stream number - * @return IRQ for the stream - */ -static int dma_get_irq(enum dma_channel stream) -{ - if (stream < STM32_DMA1_STREAM6) - return STM32_IRQ_DMA1_STREAM0 + stream; - if (stream == STM32_DMA1_STREAM7) - return STM32_IRQ_DMA1_STREAM7; - if (stream < STM32_DMA2_STREAM5) - return STM32_IRQ_DMA2_STREAM0 + stream - STM32_DMA2_STREAM0; - else - return STM32_IRQ_DMA2_STREAM5 + stream - STM32_DMA2_STREAM5; -} - -stm32_dma_regs_t *dma_get_ctrl(enum dma_channel stream) -{ - return STM32_DMA_REGS[stream / STM32_DMAS_COUNT]; -} - -stm32_dma_stream_t *dma_get_channel(enum dma_channel stream) -{ - stm32_dma_regs_t *dma = dma_get_ctrl(stream); - - return &dma->stream[stream % STM32_DMAS_COUNT]; -} - -#ifdef CHIP_FAMILY_STM32H7 -void dma_select_channel(enum dma_channel channel, uint8_t req) -{ - STM2_DMAMUX_CxCR(DMAMUX1, channel) = req; -} -#endif - -void dma_disable(enum dma_channel ch) -{ - stm32_dma_stream_t *stream = dma_get_channel(ch); - - if (stream->scr & STM32_DMA_CCR_EN) { - stream->scr &= ~STM32_DMA_CCR_EN; - while (stream->scr & STM32_DMA_CCR_EN) - ; - } -} - -void dma_disable_all(void) -{ - int ch; - - for (ch = 0; ch < STM32_DMAS_TOTAL_COUNT; ch++) - dma_disable(ch); -} - -/** - * Prepare a stream for use and start it - * - * @param stream stream to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register. - */ -static void prepare_stream(enum dma_channel stream, unsigned count, - void *periph, void *memory, unsigned flags) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; - - dma_disable(stream); - dma_clear_isr(stream); - - /* Following the order in DocID026448 Rev 1 (RM0383) p181 */ - dma_stream->spar = (uint32_t)periph; - dma_stream->sm0ar = (uint32_t)memory; - dma_stream->sndtr = count; - dma_stream->scr = ccr; - ccr |= flags & STM32_DMA_CCR_CHANNEL_MASK; - dma_stream->scr = ccr; - dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; - ccr |= flags; - dma_stream->scr = ccr; -} - -void dma_go(stm32_dma_stream_t *stream) -{ - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dsb;"); - - /* Fire it up */ - stream->scr |= STM32_DMA_CCR_EN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned count, - const void *memory) -{ - /* - * Cast away const for memory pointer; this is ok because we know - * we're preparing the stream for transmit. - */ - prepare_stream(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P | - option->flags); -} - -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) -{ - stm32_dma_stream_t *stream = dma_get_channel(option->channel); - - prepare_stream(option->channel, count, option->periph, memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M | - option->flags); - dma_go(stream); -} - -int dma_bytes_done(stm32_dma_stream_t *stream, int orig_count) -{ - /* - * Note that we're intentionally not checking that DMA is enabled here - * because there is a race when the hardware stops the transfer: - * - * From Section 9.3.14 DMA transfer completion in RM0402 Rev 5 - * https://www.st.com/resource/en/reference_manual/dm00180369.pdf: - * If the stream is configured in non-circular mode, after the end of - * the transfer (that is when the number of data to be transferred - * reaches zero), the DMA is stopped (EN bit in DMA_SxCR register is - * cleared by Hardware) and no DMA request is served unless the software - * reprograms the stream and re-enables it (by setting the EN bit in the - * DMA_SxCR register). - * - * See http://b/132444384 for full details. - */ - return orig_count - stream->sndtr; -} - -bool dma_is_enabled(stm32_dma_stream_t *stream) -{ - return (stream->scr & STM32_DMA_CCR_EN); -} - -#ifdef CONFIG_DMA_HELP -void dma_dump(enum dma_channel stream) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - - CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n", - dma_stream->scr, dma_stream->sndtr, dma_stream->spar, - dma_stream->sm0ar, dma_stream->sfcr); - CPRINTF("stream %d, isr=%x, ifcr=%x\n", - stream, - STM32_DMA_GET_ISR(stream), - STM32_DMA_GET_IFCR(stream)); -} - -void dma_check(enum dma_channel stream, char *buf) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - int count; - int i; - - count = dma_stream->sndtr; - CPRINTF("c=%d\n", count); - udelay(100 * MSEC); - CPRINTF("c=%d\n", dma_stream->sndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); - udelay(100 * MSEC); - CPRINTF("c=%d\n", dma_stream->sndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); -} - -/* Run a check of memory-to-memory DMA */ -void dma_test(enum dma_channel stream) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - uint32_t ctrl; - char periph[32], memory[32]; - unsigned count = sizeof(periph); - int i; - - memset(memory, '\0', sizeof(memory)); - for (i = 0; i < count; i++) - periph[i] = 10 + i; - - dma_clear_isr(stream); - /* Following the order in Doc ID 15965 Rev 5 p194 */ - dma_stream->spar = (uint32_t)periph; - dma_stream->sm0ar = (uint32_t)memory; - dma_stream->sndtr = count; - dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; - ctrl = STM32_DMA_CCR_PL_MEDIUM; - dma_stream->scr = ctrl; - - ctrl |= STM32_DMA_CCR_MINC; - ctrl |= STM32_DMA_CCR_DIR_M2M; - ctrl |= STM32_DMA_CCR_PINC; - - dma_stream->scr = ctrl; - dma_dump(stream); - dma_stream->scr = ctrl | STM32_DMA_CCR_EN; - - for (i = 0; i < count; i++) - CPRINTF("%d/%d ", periph[i], memory[i]); - CPRINTF("\ncount=%d\n", dma_stream->sndtr); - dma_dump(stream); -} -#endif /* CONFIG_DMA_HELP */ - -void dma_init(void) -{ - STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1 | STM32_RCC_HB1_DMA2; -} - -int dma_wait(enum dma_channel stream) -{ - timestamp_t deadline; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while ((STM32_DMA_GET_ISR(stream) & STM32_DMA_TCIF) == 0) { - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; -} - -static inline void _dma_wake_callback(void *cb_data) -{ - task_id_t id = (task_id_t)(int)cb_data; - - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_DMA_TC); -} - -void dma_enable_tc_interrupt(enum dma_channel stream) -{ - dma_enable_tc_interrupt_callback(stream, _dma_wake_callback, - (void *)(int)task_get_current()); -} - -void dma_enable_tc_interrupt_callback(enum dma_channel stream, - void (*callback)(void *), - void *callback_data) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - - dma_irq[stream].cb = callback; - dma_irq[stream].cb_data = callback_data; - - dma_stream->scr |= STM32_DMA_CCR_TCIE; - task_enable_irq(dma_get_irq(stream)); -} - -void dma_disable_tc_interrupt(enum dma_channel stream) -{ - stm32_dma_stream_t *dma_stream = dma_get_channel(stream); - - dma_stream->scr &= ~STM32_DMA_CCR_TCIE; - task_disable_irq(dma_get_irq(stream)); - - dma_irq[stream].cb = NULL; - dma_irq[stream].cb_data = NULL; -} - -void dma_clear_isr(enum dma_channel stream) -{ - STM32_DMA_SET_IFCR(stream, STM32_DMA_ALL); -} - -#ifdef CONFIG_DMA_DEFAULT_HANDLERS -#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x) -#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x) -#define DECLARE_DMA_IRQ(dma, x) \ - void STM32_DMA_FCT(dma, x)(void) \ - { \ - dma_clear_isr(STM32_DMA_IDX(dma, x)); \ - if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \ - (*dma_irq[STM32_DMA_IDX(dma, x)].cb) \ - (dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \ - STM32_DMA_FCT(dma, x), 1); - -DECLARE_DMA_IRQ(1, 0); -DECLARE_DMA_IRQ(1, 1); -DECLARE_DMA_IRQ(1, 2); -DECLARE_DMA_IRQ(1, 3); -DECLARE_DMA_IRQ(1, 4); -DECLARE_DMA_IRQ(1, 5); -DECLARE_DMA_IRQ(1, 6); -DECLARE_DMA_IRQ(1, 7); -DECLARE_DMA_IRQ(2, 0); -DECLARE_DMA_IRQ(2, 1); -DECLARE_DMA_IRQ(2, 2); -DECLARE_DMA_IRQ(2, 3); -DECLARE_DMA_IRQ(2, 4); -DECLARE_DMA_IRQ(2, 5); -DECLARE_DMA_IRQ(2, 6); -DECLARE_DMA_IRQ(2, 7); - -#endif /* CONFIG_DMA_DEFAULT_HANDLERS */ - diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c deleted file mode 100644 index 55317ba003..0000000000 --- a/chip/stm32/dma.c +++ /dev/null @@ -1,410 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) - -/* Callback data to use when IRQ fires */ -static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ -} dma_irq[STM32_DMAC_COUNT]; - - -/** - * Return the IRQ for the DMA channel - * - * @param channel Channel number - * @return IRQ for the channel - */ -static int dma_get_irq(enum dma_channel channel) -{ -#ifdef CHIP_FAMILY_STM32F0 - if (channel == STM32_DMAC_CH1) - return STM32_IRQ_DMA_CHANNEL_1; - - return channel > STM32_DMAC_CH3 ? - STM32_IRQ_DMA_CHANNEL_4_7 : - STM32_IRQ_DMA_CHANNEL_2_3; -#elif defined(CHIP_FAMILY_STM32L4) - if (channel < STM32_DMAC_PER_CTLR) - return STM32_IRQ_DMA_CHANNEL_1 + channel; - else { - if (channel <= STM32_DMAC_CH13) - return STM32_IRQ_DMA2_CHANNEL1 + - (channel - STM32_DMAC_PER_CTLR); - else - return STM32_IRQ_DMA2_CHANNEL6 + - (channel - STM32_DMAC_PER_CTLR - 5); - } -#else - if (channel < STM32_DMAC_PER_CTLR) - return STM32_IRQ_DMA_CHANNEL_1 + channel; - else - return STM32_IRQ_DMA2_CHANNEL1 + - (channel - STM32_DMAC_PER_CTLR); -#endif -} - -/* - * Note, you must decrement the channel value by 1 from what is specified - * in the datasheets, as they index from 1 and this indexes from 0! - */ -stm32_dma_chan_t *dma_get_channel(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - - return &dma->chan[channel % STM32_DMAC_PER_CTLR]; -} - -#ifdef STM32_DMAMUX_CxCR -void dma_select_channel(enum dma_channel channel, uint8_t req) -{ - /* - * STM32G4 includes a DMAMUX block which is used to handle dma requests - * by peripherals. The correct 'req' number for a given peripheral is - * given in ST doc RM0440. - */ - STM32_DMAMUX_CxCR(channel) = req; -} -#elif defined(STM32_DMA_CSELR) -void dma_select_channel(enum dma_channel channel, unsigned char stream) -{ - /* Local channel # starting from 0 on each DMA controller */ - const unsigned char ch = channel % STM32_DMAC_PER_CTLR; - const unsigned char shift = STM32_DMA_PERIPHERALS_PER_CHANNEL; - const unsigned char mask = BIT(shift) - 1; - uint32_t val; - - ASSERT(ch < STM32_DMAC_PER_CTLR); - ASSERT(stream <= mask); - val = STM32_DMA_CSELR(channel) & ~(mask << ch * shift); - STM32_DMA_CSELR(channel) = val | (stream << ch * shift); -} -#endif /* STM32_DMAMUX_CxCR/STM32_DMA_CSELR */ - -void dma_disable(enum dma_channel channel) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - - if (chan->ccr & STM32_DMA_CCR_EN) - chan->ccr &= ~STM32_DMA_CCR_EN; -} - -void dma_disable_all(void) -{ - int ch; - - for (ch = 0; ch < STM32_DMAC_COUNT; ch++) { - stm32_dma_chan_t *chan = dma_get_channel(ch); - - chan->ccr &= ~STM32_DMA_CCR_EN; - } -} - -/** - * Prepare a channel for use and start it - * - * @param chan Channel to read - * @param count Number of bytes to transfer - * @param periph Pointer to peripheral data register - * @param memory Pointer to memory address for receive/transmit - * @param flags DMA flags for the control register, normally: - * STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx - * 0 for rx - */ -static void prepare_channel(enum dma_channel channel, unsigned int count, - void *periph, void *memory, unsigned int flags) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; - - dma_disable(channel); - dma_clear_isr(channel); - - /* Following the order in Doc ID 15965 Rev 5 p194 */ - chan->cpar = (uint32_t)periph; - chan->cmar = (uint32_t)memory; - chan->cndtr = count; - chan->ccr = ccr; - ccr |= flags; - chan->ccr = ccr; -} - -void dma_go(stm32_dma_chan_t *chan) -{ - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dsb;"); - - /* Fire it up */ - chan->ccr |= STM32_DMA_CCR_EN; -} - -void dma_prepare_tx(const struct dma_option *option, unsigned int count, - const void *memory) -{ - /* - * Cast away const for memory pointer; this is ok because we know - * we're preparing the channel for transmit. - */ - prepare_channel(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | - option->flags); -} - -void dma_start_rx(const struct dma_option *option, unsigned int count, - void *memory) -{ - stm32_dma_chan_t *chan = dma_get_channel(option->channel); - - prepare_channel(option->channel, count, option->periph, memory, - STM32_DMA_CCR_MINC | option->flags); - dma_go(chan); -} - -int dma_bytes_done(stm32_dma_chan_t *chan, int orig_count) -{ - return orig_count - chan->cndtr; -} - -bool dma_is_enabled(stm32_dma_chan_t *chan) -{ - return (chan->ccr & STM32_DMA_CCR_EN); -} - -#ifdef CONFIG_DMA_HELP -void dma_dump(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - stm32_dma_chan_t *chan = dma_get_channel(channel); - - CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, - chan->cndtr, chan->cpar, chan->cmar); - CPRINTF("chan %d, isr=%x, ifcr=%x\n", - channel, - (dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf, - (dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf); -} - -void dma_check(enum dma_channel channel, char *buf) -{ - stm32_dma_chan_t *chan; - int count; - int i; - - chan = dma_get_channel(channel); - count = chan->cndtr; - CPRINTF("c=%d\n", count); - udelay(100 * MSEC); - CPRINTF("c=%d\n", chan->cndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); - udelay(100 * MSEC); - CPRINTF("c=%d\n", chan->cndtr); - for (i = 0; i < count; i++) - CPRINTF("%02x ", buf[i]); -} - -/* Run a check of memory-to-memory DMA */ -void dma_test(enum dma_channel channel) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - uint32_t ctrl; - char periph[16], memory[16]; - unsigned int count = sizeof(periph); - int i; - - memset(memory, '\0', sizeof(memory)); - for (i = 0; i < count; i++) - periph[i] = 10 + i; - - /* Following the order in Doc ID 15965 Rev 5 p194 */ - chan->cpar = (uint32_t)periph; - chan->cmar = (uint32_t)memory; - chan->cndtr = count; - ctrl = STM32_DMA_CCR_PL_MEDIUM; - chan->ccr = ctrl; - - ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */; - ctrl |= STM32_DMA_CCR_MEM2MEM; - ctrl |= STM32_DMA_CCR_PINC; -/* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */ -/* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */ - chan->ccr = ctrl; - chan->ccr = ctrl | STM32_DMA_CCR_EN; - - for (i = 0; i < count; i++) - CPRINTF("%d/%d ", periph[i], memory[i]); - CPRINTF("\ncount=%d\n", chan->cndtr); -} -#endif /* CONFIG_DMA_HELP */ - -void dma_init(void) -{ -#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN; -#elif defined(CHIP_FAMILY_STM32G4) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN | - STM32_RCC_AHB1ENR_DMAMUXEN; -#else - STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1; -#endif -#ifdef CHIP_FAMILY_STM32F3 - STM32_RCC_AHBENR |= STM32_RCC_HB_DMA2; -#endif - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -int dma_wait(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - const uint32_t mask = STM32_DMA_ISR_TCIF(channel); - timestamp_t deadline; - - deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while ((dma->isr & mask) != mask) { - if (deadline.val <= get_time().val) - return EC_ERROR_TIMEOUT; - - udelay(DMA_POLLING_INTERVAL_US); - } - return EC_SUCCESS; -} - -static inline void _dma_wake_callback(void *cb_data) -{ - task_id_t id = (task_id_t)(int)cb_data; - - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_DMA_TC); -} - -void dma_enable_tc_interrupt(enum dma_channel channel) -{ - dma_enable_tc_interrupt_callback(channel, _dma_wake_callback, - (void *)(int)task_get_current()); -} - -void dma_enable_tc_interrupt_callback(enum dma_channel channel, - void (*callback)(void *), - void *callback_data) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - - dma_irq[channel].cb = callback; - dma_irq[channel].cb_data = callback_data; - - chan->ccr |= STM32_DMA_CCR_TCIE; - task_enable_irq(dma_get_irq(channel)); -} - -void dma_disable_tc_interrupt(enum dma_channel channel) -{ - stm32_dma_chan_t *chan = dma_get_channel(channel); - - chan->ccr &= ~STM32_DMA_CCR_TCIE; - task_disable_irq(dma_get_irq(channel)); - - dma_irq[channel].cb = NULL; - dma_irq[channel].cb_data = NULL; -} - -void dma_clear_isr(enum dma_channel channel) -{ - stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); - - dma->ifcr |= STM32_DMA_ISR_ALL(channel); -} - -#ifdef CONFIG_DMA_DEFAULT_HANDLERS -#ifdef CHIP_FAMILY_STM32F0 -void dma_event_interrupt_channel_1(void) -{ - if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) { - dma_clear_isr(STM32_DMAC_CH1); - if (dma_irq[STM32_DMAC_CH1].cb != NULL) - (*dma_irq[STM32_DMAC_CH1].cb) - (dma_irq[STM32_DMAC_CH1].cb_data); - } -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1); - -void dma_event_interrupt_channel_2_3(void) -{ - int i; - - for (i = STM32_DMAC_CH2; i <= STM32_DMAC_CH3; i++) { - if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { - dma_clear_isr(i); - if (dma_irq[i].cb != NULL) - (*dma_irq[i].cb)(dma_irq[i].cb_data); - } - } -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1); - -void dma_event_interrupt_channel_4_7(void) -{ - int i; - const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT); - - for (i = STM32_DMAC_CH4; i <= max_chan; i++) { - if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { - dma_clear_isr(i); - if (dma_irq[i].cb != NULL) - (*dma_irq[i].cb)(dma_irq[i].cb_data); - } - } -} -DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1); - -#else /* !CHIP_FAMILY_STM32F0 */ - -#define DECLARE_DMA_IRQ(x) \ - void CONCAT2(dma_event_interrupt_channel_, x)(void) \ - { \ - dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ - if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \ - (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \ - (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ - CONCAT2(dma_event_interrupt_channel_, x), 1) - -DECLARE_DMA_IRQ(1); -DECLARE_DMA_IRQ(2); -DECLARE_DMA_IRQ(3); -DECLARE_DMA_IRQ(4); -DECLARE_DMA_IRQ(5); -DECLARE_DMA_IRQ(6); -DECLARE_DMA_IRQ(7); -#ifdef CHIP_FAMILY_STM32F3 -DECLARE_DMA_IRQ(9); -DECLARE_DMA_IRQ(10); -#endif -#ifdef CHIP_FAMILY_STM32L4 -DECLARE_DMA_IRQ(9); -DECLARE_DMA_IRQ(10); -DECLARE_DMA_IRQ(11); -DECLARE_DMA_IRQ(12); -DECLARE_DMA_IRQ(13); -DECLARE_DMA_IRQ(14); -DECLARE_DMA_IRQ(15); -#endif - -#endif /* CHIP_FAMILY_STM32F0 */ -#endif /* CONFIG_DMA_DEFAULT_HANDLERS */ diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c deleted file mode 100644 index 9e35a2c689..0000000000 --- a/chip/stm32/flash-f.c +++ /dev/null @@ -1,833 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Common flash memory module for STM32F and STM32F0 */ - -#include <stdbool.h> -#include "battery.h" -#include "console.h" -#include "clock.h" -#include "flash.h" -#include "flash-f.h" -#include "hooks.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status - */ -#define CYCLE_PER_FLASH_LOOP 10 - -/* - * While flash write / erase is in progress, the stm32 CPU core is mostly - * non-functional, due to the inability to fetch instructions from flash. - * This may greatly increase interrupt latency. - */ - -/* Flash page programming timeout. This is 2x the datasheet max. */ -#define FLASH_WRITE_TIMEOUT_US 16000 -/* 20ms < tERASE < 40ms on F0/F3, for 1K / 2K sector size. */ -#define FLASH_ERASE_TIMEOUT_US 40000 - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -#if !defined(CHIP_FAMILY_STM32F4) -#error "CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE should work with all STM32F " -"series chips, but has not been tested" -#endif /* !CHIP_FAMILY_STM32F4 */ -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -/* Forward declarations */ -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -static enum flash_rdp_level flash_physical_get_rdp_level(void); -static int flash_physical_set_rdp_level(enum flash_rdp_level level); -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -static inline int calculate_flash_timeout(void) -{ - return (FLASH_WRITE_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); -} - -static int wait_busy(void) -{ - int timeout = calculate_flash_timeout(); - while ((STM32_FLASH_SR & FLASH_SR_BUSY) && timeout-- > 0) - udelay(CYCLE_PER_FLASH_LOOP); - return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; -} - - -void unlock_flash_control_register(void) -{ - STM32_FLASH_KEYR = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR = FLASH_KEYR_KEY2; -} - -void unlock_flash_option_bytes(void) -{ - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; -} - -void disable_flash_option_bytes(void) -{ - ignore_bus_fault(1); - /* - * Writing anything other than the pre-defined keys to the option key - * register results in a bus fault and the register being locked until - * reboot (even with a further correct key write). - */ - STM32_FLASH_OPTKEYR = 0xffffffff; - ignore_bus_fault(0); -} - -void disable_flash_control_register(void) -{ - ignore_bus_fault(1); - /* - * Writing anything other than the pre-defined keys to the key - * register results in a bus fault and the register being locked until - * reboot (even with a further correct key write). - */ - STM32_FLASH_KEYR = 0xffffffff; - ignore_bus_fault(0); -} - -void lock_flash_control_register(void) -{ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - /* FLASH_CR_OPTWRE was set by writing the keys in unlock(). */ - STM32_FLASH_CR &= ~FLASH_CR_OPTWRE; -#endif - STM32_FLASH_CR |= FLASH_CR_LOCK; -} - -void lock_flash_option_bytes(void) -{ -#if !(defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)) - STM32_FLASH_OPTCR |= FLASH_OPTLOCK; -#endif -} - -bool flash_option_bytes_locked(void) -{ - return !!STM32_FLASH_OPT_LOCKED; -} - -bool flash_control_register_locked(void) -{ - return !!(STM32_FLASH_CR & FLASH_CR_LOCK); -} - -/* - * We at least unlock the control register lock. - * We may also unlock other locks. - */ -enum extra_lock_type { - NO_EXTRA_LOCK = 0, - OPT_LOCK = 1, -}; - -static int unlock(int locks) -{ - /* - * We may have already locked the flash module and get a bus fault - * in the attempt to unlock. Need to disable bus fault handler now. - */ - ignore_bus_fault(1); - - /* Always unlock CR if needed */ - if (flash_control_register_locked()) - unlock_flash_control_register(); - - /* unlock option memory if required */ - if ((locks & OPT_LOCK) && flash_option_bytes_locked()) - unlock_flash_option_bytes(); - - /* Re-enable bus fault handler */ - ignore_bus_fault(0); - - if ((locks & OPT_LOCK) && flash_option_bytes_locked()) - return EC_ERROR_UNKNOWN; - if (STM32_FLASH_CR & FLASH_CR_LOCK) - return EC_ERROR_UNKNOWN; - return EC_SUCCESS; -} - -static void lock(void) -{ - lock_flash_control_register(); -} - -#ifdef CHIP_FAMILY_STM32F4 -static int write_optb(uint32_t mask, uint32_t value) -{ - int rv; - - rv = wait_busy(); - if (rv) - return rv; - - /* The target byte is the value we want to write. */ - if ((STM32_FLASH_OPTCR & mask) == value) - return EC_SUCCESS; - - rv = unlock(OPT_LOCK); - if (rv) - return rv; - - STM32_FLASH_OPTCR = (STM32_FLASH_OPTCR & ~mask) | value; - STM32_FLASH_OPTCR |= FLASH_OPTSTRT; - - rv = wait_busy(); - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} -#else -static int write_optb(int byte, uint8_t value); -/* - * Option byte organization - * - * [31:24] [23:16] [15:8] [7:0] - * - * 0x1FFF_F800 nUSER USER nRDP RDP - * - * 0x1FFF_F804 nData1 Data1 nData0 Data0 - * - * 0x1FFF_F808 nWRP1 WRP1 nWRP0 WRP0 - * - * 0x1FFF_F80C nWRP3 WRP2 nWRP2 WRP2 - * - * Note that the variable with n prefix means the complement. - */ -static uint8_t read_optb(int byte) -{ - return *(uint8_t *)(STM32_OPTB_BASE + byte); -} - -static int erase_optb(void) -{ - int rv; - - rv = wait_busy(); - if (rv) - return rv; - - rv = unlock(OPT_LOCK); - if (rv) - return rv; - - /* Must be set in 2 separate lines. */ - STM32_FLASH_CR |= FLASH_CR_OPTER; - STM32_FLASH_CR |= FLASH_CR_STRT; - - rv = wait_busy(); - - STM32_FLASH_CR &= ~FLASH_CR_OPTER; - - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} - -static int write_optb(int byte, uint8_t value); -/* - * Since the option byte erase is WHOLE erase, this function is to keep - * rest of bytes, but make this byte 0xff. - * Note that this could make a recursive call to write_optb(). - */ -static int preserve_optb(int byte) -{ - int i, rv; - uint8_t optb[8]; - - /* The byte has been reset, no need to run preserve. */ - if (*(uint16_t *)(STM32_OPTB_BASE + byte) == 0xffff) - return EC_SUCCESS; - - for (i = 0; i < ARRAY_SIZE(optb); ++i) - optb[i] = read_optb(i * 2); - - optb[byte / 2] = 0xff; - - rv = erase_optb(); - if (rv) - return rv; - for (i = 0; i < ARRAY_SIZE(optb); ++i) { - rv = write_optb(i * 2, optb[i]); - if (rv) - return rv; - } - - return EC_SUCCESS; -} - -static int write_optb(int byte, uint8_t value) -{ - volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte); - int rv; - - rv = wait_busy(); - if (rv) - return rv; - - /* The target byte is the value we want to write. */ - if (*(uint8_t *)hword == value) - return EC_SUCCESS; - - /* Try to erase that byte back to 0xff. */ - rv = preserve_optb(byte); - if (rv) - return rv; - - /* The value is 0xff after erase. No need to write 0xff again. */ - if (value == 0xff) - return EC_SUCCESS; - - rv = unlock(OPT_LOCK); - if (rv) - return rv; - - /* set OPTPG bit */ - STM32_FLASH_CR |= FLASH_CR_OPTPG; - - *hword = ((~value) << STM32_OPTB_COMPL_SHIFT) | value; - - /* reset OPTPG bit */ - STM32_FLASH_CR &= ~FLASH_CR_OPTPG; - - rv = wait_busy(); - if (rv) - return rv; - lock(); - - return EC_SUCCESS; -} -#endif - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -/** - * @return true if RDP (read protection) Level 1 or 2 enabled, false otherwise - */ -bool is_flash_rdp_enabled(void) -{ - enum flash_rdp_level level = flash_physical_get_rdp_level(); - - if (level == FLASH_RDP_LEVEL_INVALID) { - CPRINTS("ERROR: unable to read RDP level"); - return false; - } - - return level != FLASH_RDP_LEVEL_0; -} -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -/*****************************************************************************/ -/* Physical layer APIs */ - -int crec_flash_physical_write(int offset, int size, const char *data) -{ -#if CONFIG_FLASH_WRITE_SIZE == 1 - uint8_t *address = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - uint8_t quantum = 0; -#elif CONFIG_FLASH_WRITE_SIZE == 2 - uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - uint16_t quantum = 0; -#elif CONFIG_FLASH_WRITE_SIZE == 4 - uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - uint32_t quantum = 0; -#else -#error "CONFIG_FLASH_WRITE_SIZE not supported." -#endif - int res = EC_SUCCESS; - int timeout = calculate_flash_timeout(); - - if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP; - - /* set PG bit */ - STM32_FLASH_CR |= FLASH_CR_PG; - - for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) { - int i; - - for (i = CONFIG_FLASH_WRITE_SIZE - 1, quantum = 0; i >= 0; i--) - quantum = (quantum << 8) + data[i]; - data += CONFIG_FLASH_WRITE_SIZE; - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing with interrupt disabled. - */ - watchdog_reload(); - - /* wait to be ready */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); - i++) - ; - - /* write the data */ - *address++ = quantum; - - /* Wait for writes to complete */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); - i++) - ; - - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* Check for error conditions - erase failed, voltage error, - * protection error */ - if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Disable PG bit */ - STM32_FLASH_CR &= ~FLASH_CR_PG; - - lock(); - - return res; -} - -int crec_flash_physical_erase(int offset, int size) -{ - int res = EC_SUCCESS; - int sector_size; - int timeout_us; -#ifdef CHIP_FAMILY_STM32F4 - int sector = crec_flash_bank_index(offset); - /* we take advantage of sector_size == erase_size */ - if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0)) - return EC_ERROR_INVAL; /* Invalid range */ -#endif - - if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ALL_ERR | FLASH_SR_EOP; - - /* set SER/PER bit */ - STM32_FLASH_CR |= FLASH_CR_PER; - - while (size > 0) { - timestamp_t deadline; -#ifdef CHIP_FAMILY_STM32F4 - sector_size = crec_flash_bank_size(sector); - /* Timeout: from spec, proportional to the size - * inversely proportional to the write size. - */ - timeout_us = sector_size * 4 / CONFIG_FLASH_WRITE_SIZE; -#else - sector_size = CONFIG_FLASH_ERASE_SIZE; - timeout_us = FLASH_ERASE_TIMEOUT_US; -#endif - /* Do nothing if already erased */ - if (crec_flash_is_erased(offset, sector_size)) - goto next_sector; -#ifdef CHIP_FAMILY_STM32F4 - /* select page to erase */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) | - (sector << STM32_FLASH_CR_SNB_OFFSET); -#else - /* select page to erase */ - STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; -#endif - /* set STRT bit : start erase */ - STM32_FLASH_CR |= FLASH_CR_STRT; - - deadline.val = get_time().val + timeout_us; - /* Wait for erase to complete */ - watchdog_reload(); - while ((STM32_FLASH_SR & FLASH_SR_BUSY) && - (get_time().val < deadline.val)) { - usleep(timeout_us/100); - } - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & FLASH_SR_ALL_ERR) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } -next_sector: - size -= sector_size; - offset += sector_size; -#ifdef CHIP_FAMILY_STM32F4 - sector++; -#endif - } - -exit_er: - /* reset SER/PER bit */ - STM32_FLASH_CR &= ~FLASH_CR_PER; - - lock(); - - return res; -} - -#ifdef CHIP_FAMILY_STM32F4 -static int flash_physical_get_protect_at_boot(int block) -{ - /* 0: Write protection active on sector i. */ - return !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)); -} - -static int flash_physical_protect_at_boot_update_rdp_pstate(uint32_t new_flags) -{ -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) - int rv = EC_SUCCESS; - - bool rdp_enable = (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) != 0; - - /* - * This is intentionally a one-way latch. Once we have enabled RDP - * Level 1, we will only allow going back to Level 0 using the - * bootloader (e.g., "stm32mon -U") since transitioning from Level 1 to - * Level 0 triggers a mass erase. - */ - if (rdp_enable) - rv = flash_physical_set_rdp_level(FLASH_RDP_LEVEL_1); - - return rv; -#else - return EC_SUCCESS; -#endif -} - -int crec_flash_physical_protect_at_boot(uint32_t new_flags) -{ - int block; - int original_val, val; - - original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL; - - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; - block++) { - int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; - - if (block >= WP_BANK_OFFSET && - block < WP_BANK_OFFSET + WP_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT; -#ifdef CONFIG_FLASH_PROTECT_RW - else - protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - - if (protect) - val &= ~BIT(block); - else - val |= 1 << block; - } - if (original_val != val) { - int rv = write_optb(STM32_FLASH_nWRP_ALL, - val << STM32_FLASH_nWRP_OFFSET); - if (rv != EC_SUCCESS) - return rv; - } - - return flash_physical_protect_at_boot_update_rdp_pstate(new_flags); -} - -static void unprotect_all_blocks(void) -{ - write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL); -} - -#else /* CHIP_FAMILY_STM32F4 */ -static int flash_physical_get_protect_at_boot(int block) -{ - uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8)); - return (!(val & (1 << (block % 8)))) ? 1 : 0; -} - -int crec_flash_physical_protect_at_boot(uint32_t new_flags) -{ - int block; - int i; - int original_val[4], val[4]; - - for (i = 0; i < 4; ++i) - original_val[i] = val[i] = read_optb(i * 2 + 8); - - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; - block++) { - int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; - int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4; - - if (block >= WP_BANK_OFFSET && - block < WP_BANK_OFFSET + WP_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_RO_AT_BOOT; -#ifdef CONFIG_ROLLBACK - else if (block >= ROLLBACK_BANK_OFFSET && - block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif -#ifdef CONFIG_FLASH_PROTECT_RW - else - protect |= new_flags & EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - - if (protect) - val[byte_off] = val[byte_off] & (~(1 << (block % 8))); - else - val[byte_off] = val[byte_off] | (1 << (block % 8)); - } - - for (i = 0; i < 4; ++i) - if (original_val[i] != val[i]) - write_optb(i * 2 + 8, val[i]); - -#ifdef CONFIG_FLASH_READOUT_PROTECTION - /* - * Set a permanent protection by increasing RDP to level 1, - * trying to unprotected the flash will trigger a full erase. - */ - write_optb(0, 0x11); -#endif - - return EC_SUCCESS; -} - -static void unprotect_all_blocks(void) -{ - int i; - - for (i = 4; i < 8; ++i) - write_optb(i * 2, 0xff); -} -#endif - -/** - * Check if write protect register state is inconsistent with RO_AT_BOOT and - * ALL_AT_BOOT state. - * - * @return zero if consistent, non-zero if inconsistent. - */ -static int registers_need_reset(void) -{ - uint32_t flags = crec_flash_get_protect(); - int i; - int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0; - int ro_wp_region_start = WP_BANK_OFFSET; - int ro_wp_region_end = WP_BANK_OFFSET + WP_BANK_COUNT; - - for (i = ro_wp_region_start; i < ro_wp_region_end; i++) - if (flash_physical_get_protect_at_boot(i) != ro_at_boot) - return 1; - return 0; -} - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -/** - * Set Flash RDP (read protection) level. - * - * @note Does not take effect until reset. - * - * @param level new RDP (read protection) level to set - * @return EC_SUCCESS on success, other on failure - */ -int flash_physical_set_rdp_level(enum flash_rdp_level level) -{ - uint32_t reg_level; - - switch (level) { - case FLASH_RDP_LEVEL_0: - /* - * Asserting by default since we don't want to inadvertently - * go from Level 1 to Level 0, which triggers a mass erase. - * Remove assert if you want to use it. - */ - ASSERT(false); - reg_level = FLASH_OPTCR_RDP_LEVEL_0; - break; - case FLASH_RDP_LEVEL_1: - reg_level = FLASH_OPTCR_RDP_LEVEL_1; - break; - case FLASH_RDP_LEVEL_2: - /* - * Asserting by default since it's permanent (there is no - * way to reverse). Remove assert if you want to use it. - */ - ASSERT(false); - reg_level = FLASH_OPTCR_RDP_LEVEL_2; - break; - default: - return EC_ERROR_INVAL; - } - - return write_optb(FLASH_OPTCR_RDP_MASK, reg_level); -} - -/** - * @return On success, current flash read protection level. - * On failure, FLASH_RDP_LEVEL_INVALID - */ -enum flash_rdp_level flash_physical_get_rdp_level(void) -{ - uint32_t level = (STM32_FLASH_OPTCR & FLASH_OPTCR_RDP_MASK); - - switch (level) { - case FLASH_OPTCR_RDP_LEVEL_0: - return FLASH_RDP_LEVEL_0; - case FLASH_OPTCR_RDP_LEVEL_1: - return FLASH_RDP_LEVEL_1; - case FLASH_OPTCR_RDP_LEVEL_2: - return FLASH_RDP_LEVEL_2; - default: - return FLASH_RDP_LEVEL_INVALID; - } -} -#endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ - -/*****************************************************************************/ -/* High-level APIs */ - -int crec_flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = crec_flash_get_protect(); - int need_reset = 0; - - -#ifdef CHIP_FAMILY_STM32F4 - unlock(NO_EXTRA_LOCK); - /* Set the proper write size */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) | - (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) << - STM32_FLASH_CR_PSIZE_OFFSET; - lock(); -#endif - if (crec_flash_physical_restore_state()) - return EC_SUCCESS; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - if (prot_flags & EC_FLASH_PROTECT_RO_NOW) { - /* Enable physical protection for RO (0 means RO). */ - crec_flash_physical_protect_now(0); - } - - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - /* - * Pstate wants RO protected at boot, but the write - * protect register wasn't set to protect it. Force an - * update to the write protect register and reboot so - * it takes effect. - */ - crec_flash_physical_protect_at_boot( - EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - - if (registers_need_reset()) { - /* - * Write protect register was in an inconsistent state. - * Set it back to a good state and reboot. - * - * TODO(crosbug.com/p/23798): this seems really similar - * to the check above. One of them should be able to - * go away. - */ - crec_flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - } else { - if (prot_flags & EC_FLASH_PROTECT_RO_NOW) { - /* - * Write protect pin unasserted but some section is - * protected. Drop it and reboot. - */ - unprotect_all_blocks(); - need_reset = 1; - } - } - - if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ALL_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { - /* - * ALL_AT_BOOT and ALL_NOW should be both set or both unset - * at boot. If they are not, it must be that the chip requires - * OBL_LAUNCH to be set to reload option bytes. Let's reset - * the system with OBL_LAUNCH set. - * This assumes OBL_LAUNCH is used for hard reset in - * chip/stm32/system.c. - */ - need_reset = 1; - } - -#ifdef CONFIG_FLASH_PROTECT_RW - if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_RW_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { - /* RW_AT_BOOT and RW_NOW do not match. */ - need_reset = 1; - } -#endif - -#ifdef CONFIG_ROLLBACK - if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) { - /* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */ - need_reset = 1; - } -#endif - - if (need_reset) - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - return EC_SUCCESS; -} diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h deleted file mode 100644 index cbbe6ec86f..0000000000 --- a/chip/stm32/flash-f.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_STM32_FLASH_F_H -#define __CROS_EC_STM32_FLASH_F_H - -#include <stdbool.h> - -enum flash_rdp_level { - FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */ - FLASH_RDP_LEVEL_0, /**< No read protection. */ - FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in - * bootloader mode or JTAG attached. - * Changing to Level 0 from this level - * triggers mass erase. - */ - FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent - * and can never be disabled. - */ -}; - -bool is_flash_rdp_enabled(void); - -#endif /* __CROS_EC_STM32_FLASH_F_H */ diff --git a/chip/stm32/flash-regs.h b/chip/stm32/flash-regs.h deleted file mode 100644 index b0a46667a1..0000000000 --- a/chip/stm32/flash-regs.h +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_STM32_FLASH_REGS_H -#define __CROS_EC_STM32_FLASH_REGS_H - -#include <stdbool.h> - -/** - * Unlock the flash control register using the unlock sequence. - * - * If the flash control register has been disabled since the last reset when - * this function is called, a bus fault will be generated. - * - * See "3.5.1 Unlocking the Flash control register" in RM0402. - * See "4.9.2 FLASH key register for bank 1" in RM0433. - */ -void unlock_flash_control_register(void); - -/** - * Unlock the flash option bytes register using the unlock sequence. - * - * If the flash option bytes register has been disabled since the last reset - * when this function is called, a bus fault will be generated. - * - * See "3.6.2 Programming user option bytes" in RM0402. - * See "4.9.3 FLASH option key register" in RM0433. - */ -void unlock_flash_option_bytes(void); - -/** - * Lock the flash control register. - * - * If the flash control register has been disabled since the last reset when - * this function is called, a bus fault will be generated. - * - * See "3.5.1 Unlocking the Flash control register" in RM0402. - * See "4.9.4 Flash control register for bank 1" in RM0433. - */ -void lock_flash_control_register(void); - -/** - * Lock the flash option bytes register. - * - * If the flash option bytes register has been disabled since the last reset - * when this function is called, a bus fault will be generated. - * - * See "3.6.2 Programming user option bytes" in RM0402. - * See "4.9.7 FLASH option control register" in RM0433. - */ -void lock_flash_option_bytes(void); - -/** - * Disable the flash option bytes register. - * - * This function expects that bus faults have not already been ignored when - * called. - * - * Once this function is called any attempt at accessing the flash option - * bytes register will generate a bus fault until the next reset. - * - * See "3.6.2 Programming user option bytes" in RM0402. - * See "4.9.7 FLASH option control register" in RM0433. - */ -void disable_flash_option_bytes(void); - -/** - * Disable the flash control register. - * - * This function expects that bus faults have not already been ignored when - * called. - * - * Once this function is called any attempt at accessing the flash control - * register will generate a bus fault until the next reset. - * - * See "3.5.1 Unlocking the Flash control register" in RM0402. - * See "4.9.4 Flash control register for bank 1" in RM0433. - */ -void disable_flash_control_register(void); - -/** - * Check if the flash option bytes are locked. - * - * If the flash option bytes register has been disabled since the last reset - * when this function is called, a bus fault will be generated. - - * See "3.6.2 Programming user option bytes" in RM0402. - * See "4.9.7 FLASH option control register" in RM0433. - * - * @return true if option bytes are locked, false otherwise - */ -bool flash_option_bytes_locked(void); - -/** - * Check if the flash control register is locked. - * - * If the flash control register has been disabled since the last reset - * when this function is called, a bus fault will be generated. - * - * See "3.5.1 Unlocking the Flash control register" in RM0402. - * See "4.9.4 Flash control register for bank 1" in RM0433. - * - * @return true if register is locked, false otherwise - */ -bool flash_control_register_locked(void); - -#endif /* __CROS_EC_STM32_FLASH_REGS_H */ diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c deleted file mode 100644 index f790a657c8..0000000000 --- a/chip/stm32/flash-stm32f0.c +++ /dev/null @@ -1,173 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Flash memory module for Chrome EC */ - -#include "common.h" -#include "flash.h" -#include "registers.h" -#include "util.h" - -/*****************************************************************************/ -/* Physical layer APIs */ - -int crec_flash_physical_get_protect(int block) -{ - return !(STM32_FLASH_WRPR & BIT(block)); -} - -/* - * Note: This does not need to update _NOW flags, as get_protect_flags - * in common code already does so. - */ -uint32_t crec_flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - uint32_t wrp01 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP01); -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 - uint32_t wrp23 = REG32(STM32_OPTB_BASE + STM32_OPTB_WRP23); -#endif - - /* - * We only need to return detailed flags if we want to protect RW or - * ROLLBACK independently (EC_FLASH_PROTECT_RO_AT_BOOT should be set - * by pstate logic). - */ -#if defined(CONFIG_FLASH_PROTECT_RW) || defined(CONFIG_ROLLBACK) - /* Flags that must be set for each region. */ - const int mask_flags[] = { - [FLASH_REGION_RW] = EC_FLASH_PROTECT_RW_AT_BOOT, - [FLASH_REGION_RO] = EC_FLASH_PROTECT_RO_AT_BOOT, -#ifdef CONFIG_ROLLBACK - [FLASH_REGION_ROLLBACK] = EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, -#endif - }; - - /* - * Sets up required mask for wrp01/23 registers: for protection to be - * set, values set in the mask must be zeros, values in the mask << 8 - * must be ones. - * - * Note that these masks are actually static, and could be precomputed - * at build time to save flash space. - */ - uint32_t wrp_mask[FLASH_REGION_COUNT][2]; - int i; - int shift = 0; - int reg = 0; - - memset(wrp_mask, 0, sizeof(wrp_mask)); - - /* Scan flash protection */ - for (i = 0; i < PHYSICAL_BANKS; i++) { - /* Default: RW. */ - int region = FLASH_REGION_RW; - - if (i >= WP_BANK_OFFSET && - i < WP_BANK_OFFSET + WP_BANK_COUNT) - region = FLASH_REGION_RO; -#ifdef CONFIG_ROLLBACK - if (i >= ROLLBACK_BANK_OFFSET && - i < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - region = FLASH_REGION_ROLLBACK; -#endif - - switch (i) { - case 8: -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 - case 24: -#endif - shift += 8; - break; -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 - case 16: - reg = 1; - shift = 0; - break; -#endif - } - - wrp_mask[region][reg] |= 1 << shift; - shift++; - } - - for (i = 0; i < FLASH_REGION_COUNT; i++) { - if (!(wrp01 & wrp_mask[i][0]) && - (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 - if (!(wrp23 & wrp_mask[i][1]) && - (wrp23 & wrp_mask[i][1] << 8) == - (wrp_mask[i][1] << 8)) -#endif - flags |= mask_flags[i]; - } -#endif /* CONFIG_FLASH_PROTECT_RW || CONFIG_ROLLBACK */ - - if (wrp01 == 0xff00ff00) -#if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 - if (wrp23 == 0xff00ff00) -#endif - flags |= EC_FLASH_PROTECT_ALL_AT_BOOT; - - return flags; -} - -int crec_flash_physical_protect_now(int all) -{ - return EC_ERROR_INVAL; -} - -int crec_flash_physical_restore_state(void) -{ - /* Nothing to restore */ - return 0; -} - -uint32_t crec_flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | -#ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | -#endif -#ifdef CONFIG_ROLLBACK - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_ROLLBACK_NOW | -#endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * ALL/RW at-boot state can be set if WP GPIO is asserted and can always - * be cleared. - */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; - -#ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - -#ifdef CONFIG_ROLLBACK - if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif - - return ret; -} diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c deleted file mode 100644 index 138e690fcc..0000000000 --- a/chip/stm32/flash-stm32f3.c +++ /dev/null @@ -1,198 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Flash memory module for stm32f3 and stm32f4 */ - -#include <stdbool.h> -#include "common.h" -#include "flash.h" -#include "flash-f.h" -#include "flash-regs.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "panic.h" - -/*****************************************************************************/ -/* Physical layer APIs */ -#ifdef CHIP_VARIANT_STM32F76X -/* - * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB - */ -struct ec_flash_bank const flash_bank_array[] = { - { - .count = 4, - .size_exp = __fls(SIZE_32KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_32KB), - .protect_size_exp = __fls(SIZE_32KB), - }, - { - .count = 1, - .size_exp = __fls(SIZE_128KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_128KB), - .protect_size_exp = __fls(SIZE_128KB), - }, - { - .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB, - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .size_exp = __fls(SIZE_256KB), - .erase_size_exp = __fls(SIZE_256KB), - .protect_size_exp = __fls(SIZE_256KB), - }, -}; -#elif defined(CHIP_FAMILY_STM32F4) -/* - * STM32F412xE has 512 KB flash - * 8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB - * - * STM32F412xG has 1 MB flash - * 12 "erase" sectors (1024 KB) : - * 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB - * - * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf - */ -struct ec_flash_bank const flash_bank_array[] = { - { - .count = 4, - .size_exp = __fls(SIZE_16KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_16KB), - .protect_size_exp = __fls(SIZE_16KB), - }, - { - .count = 1, - .size_exp = __fls(SIZE_64KB), - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .erase_size_exp = __fls(SIZE_64KB), - .protect_size_exp = __fls(SIZE_64KB), - }, - { - .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB, - .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), - .size_exp = __fls(SIZE_128KB), - .erase_size_exp = __fls(SIZE_128KB), - .protect_size_exp = __fls(SIZE_128KB), - }, -}; -#endif - -/* Flag indicating whether we have locked down entire flash */ -static int entire_flash_locked; - -#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ -#define FLASH_HOOK_VERSION 1 - -/* The previous write protect state before sys jump */ -struct flash_wp_state { - int entire_flash_locked; -}; - -/*****************************************************************************/ -/* Physical layer APIs */ - -int crec_flash_physical_get_protect(int block) -{ - return (entire_flash_locked || -#if defined(CHIP_FAMILY_STM32F3) - !(STM32_FLASH_WRPR & BIT(block)) -#elif defined(CHIP_FAMILY_STM32F4) - !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) -#endif - ); -} - -uint32_t crec_flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - /* Read all-protected state from our shadow copy */ - if (entire_flash_locked) - flags |= EC_FLASH_PROTECT_ALL_NOW; - -#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) - if (is_flash_rdp_enabled()) - flags |= EC_FLASH_PROTECT_RO_AT_BOOT; -#endif - - return flags; -} - -int crec_flash_physical_protect_now(int all) -{ - if (all) { - disable_flash_control_register(); - entire_flash_locked = 1; - - return EC_SUCCESS; - } - - disable_flash_option_bytes(); - - return EC_SUCCESS; -} - -uint32_t crec_flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -int crec_flash_physical_restore_state(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - int version, size; - const struct flash_wp_state *prev; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) { - prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); - if (prev && version == FLASH_HOOK_VERSION && - size == sizeof(*prev)) - entire_flash_locked = prev->entire_flash_locked; - return 1; - } - - return 0; -} - -/*****************************************************************************/ -/* Hooks */ - -static void flash_preserve_state(void) -{ - struct flash_wp_state state; - - state.entire_flash_locked = entire_flash_locked; - - system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, - sizeof(state), &state); -} -DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c deleted file mode 120000 index 6ff8130e17..0000000000 --- a/chip/stm32/flash-stm32f4.c +++ /dev/null @@ -1 +0,0 @@ -flash-stm32f3.c
\ No newline at end of file diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c deleted file mode 100644 index f792da6e3c..0000000000 --- a/chip/stm32/flash-stm32g4-l4.c +++ /dev/null @@ -1,792 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Flash memory module for STM32L4 family */ - -#include "common.h" -#include "clock.h" -#include "flash.h" -#include "hooks.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status - */ -#define CYCLE_PER_FLASH_LOOP 10 - -/* Flash page programming timeout. This is 2x the datasheet max. */ -#define FLASH_TIMEOUT_US 48000 - -/* - * Cros-Ec common flash APIs use the term 'bank' equivalent to how 'page' is - * used in the STM32 TRMs. Redifining macros here in terms of pages in order to - * match STM32 documentation for write protect computations in this file. - * - * These macros are from the common flash API and mean the following: - * WP_BANK_OFFSET -> index of first RO page - * CONFIG_WP_STORAGE_SIZE -> size of RO region in bytes - */ -#define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE -#define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE) -#define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET -#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \ - + FLASH_RO_FIRST_PAGE_IDX - 1) -#define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1) -#define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1) - - -#define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT -#define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET -#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\ - FLASH_PAGE_ROLLBACK_COUNT -1) - -#ifdef STM32_FLASH_DBANK_MODE -#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1) -#else -#ifdef CHIP_FAMILY_STM32L4 -#define FLASH_WRP_MASK 0xFF -#else -#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1) -#endif -#endif /* CONFIG_FLASH_DBANK_MODE */ -#define FLASH_WRP_START(val) ((val) & FLASH_WRP_MASK) -#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK) -#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \ - (((end) & FLASH_WRP_MASK) << 16)) -#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00) -#define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK) - -enum wrp_region { - WRP_RO, - WRP_RW, -}; - -struct wrp_info { - int enable; - int start; - int end; -}; - -static inline int calculate_flash_timeout(void) -{ - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); -} - -static int wait_while_busy(void) -{ - int timeout = calculate_flash_timeout(); - - while (STM32_FLASH_SR & FLASH_SR_BUSY && timeout-- > 0) - ; - return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; -} - -static int unlock(int locks) -{ - /* - * We may have already locked the flash module and get a bus fault - * in the attempt to unlock. Need to disable bus fault handler now. - */ - ignore_bus_fault(1); - - /* unlock CR if needed */ - if (STM32_FLASH_CR & FLASH_CR_LOCK) { - STM32_FLASH_KEYR = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR = FLASH_KEYR_KEY2; - } - /* unlock option memory if required */ - if ((locks & FLASH_CR_OPTLOCK) && - (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) { - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; - } - - /* Re-enable bus fault handler */ - ignore_bus_fault(0); - - return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; -} - -static void lock(void) -{ - STM32_FLASH_CR |= FLASH_CR_LOCK; -} - -static void ob_lock(void) -{ - STM32_FLASH_CR |= FLASH_CR_OPTLOCK; -} - -/* - * Option byte organization - * - * [63:56][55:48][47:40][39:32] [31:24][23:16][15: 8][ 7: 0] - * +--------------+-------------------+------+ +-------------------+------+ - * | 0x1FFF7800 | nUSER | nRDP | | USER | RDP | - * +--------------+------------+------+------+ +------------+------+------+ - * | 0x1FFF7808 | | nPCROP1_STRT| | | PCROP1_STRT | - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7810 | | nPCROP1_END | | | PCROP1_END | - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7818 | |nWRP1A| |nWRP1A| | | WRP1A| | WRP1A| - * | | |_END | |_STRT | | | _END | | _STRT| - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7820 | |nWRP1B| |nWRP1B| | | WRP1B| | WRP1B| - * | | |_END | |_STRT | | | _END | | _STRT| - * +--------------+------------+-------------+ +------------+-------------+ - * | 0x1FFF7828 | |nBOOT | |nSEC_ | | | BOOT | | SEC_ | - * | | |LOCK | |SIZE1 | | | _LOCK| | SIZE1| - * +--------------+------------+-------------+ +------------+-------------+ - * - * Note that the variable with n prefix means the complement. - */ -static int unlock_optb(void) -{ - int rv; - - rv = wait_while_busy(); - if (rv) - return rv; - - rv = unlock(FLASH_CR_OPTLOCK); - if (rv) - return rv; - - return EC_SUCCESS; -} - -static int commit_optb(void) -{ - int rv; - - /* - * Wait for last operation. - */ - rv = wait_while_busy(); - if (rv) - return rv; - - STM32_FLASH_CR |= FLASH_CR_OPTSTRT; - - rv = wait_while_busy(); - if (rv) - return rv; - - ob_lock(); - lock(); - - return EC_SUCCESS; -} - -/* - * There are a minimum of 2 WRP regions that can be set. The STM32G4 - * family has both category 2, and category 3 devices. Category 2 - * devices have only 2 WRP regions, but category 3 devices have 4 WRP - * regions that can be configured. Category 3 devices also support dual - * flash banks, and this mode is the default setting. When DB mode is enabled, - * then each WRP register can only protect up to 64 2kB pages. This means that - * one WRP register is needed per bank. - * - * 1. WRP1A -> used always for RO - * 2. WRP1B -> used always for RW - * 3. WRP2A -> may be used for RW if dual-bank (DB) mode is enabled - * 4. WRP2B -> currently never used - * - * WRP areas are specified in terms of page indices with a start index - * and an end index. start == end means a single page is protected. - * - * WRPnx_start = WRPnx_end --> WRPnx_start page is protected - * WRPnx_start > WRPnx_end --> No WRP area is specified - * WRPnx_start < WRPnx_end --> Pages WRPnx_start to WRPnx_end - */ -static void optb_get_wrp(enum wrp_region region, struct wrp_info *wrp) -{ -#ifdef STM32_FLASH_DBANK_MODE - int start; - int end; -#endif - /* Assume WRP regions are not configured */ - wrp->start = FLASH_WRP_MASK; - wrp->end = 0; - wrp->enable = 0; - - if (region == WRP_RO) { - /* - * RO write protect is fully described by WRP1AR. Get the - * start/end indices. If end >= start, then RO write protect is - * enabled. - */ - wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1AR); - wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1AR); - wrp->enable = wrp->end >= wrp->start; - } else if (region == WRP_RW) { - /* - * RW write always uses WRP1BR. If dual-bank mode is being used, - * then WRP2AR must also be check to determine the full range of - * flash page indices being protected. - */ - wrp->start = FLASH_WRP_START(STM32_OPTB_WRP1BR); - wrp->end = FLASH_WRP_END(STM32_OPTB_WRP1BR); - wrp->enable = wrp->end >= wrp->start; -#ifdef STM32_FLASH_DBANK_MODE - start = FLASH_WRP_START(STM32_FLASH_WRP2AR); - end = FLASH_WRP_END(STM32_FLASH_WRP2AR); - /* - * If WRP2AR protection is enabled, then need to adjust either - * the start, end, or both indices. - */ - if (end >= start) { - if (wrp->enable) { - /* WRP1BR is active, only need to adjust end */ - wrp->end += end; - } else { - /* - * WRP1BR is not active, so RW protection, if - * enabled, is fully controlled by WRP2AR. - */ - wrp->start = start; - wrp->end = end; - wrp->enable = 1; - } - } -#endif - } -} - -static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp) -{ - int start = wrp->start; - int end = wrp->end; - - if (!wrp->enable) { - /* - * If enable is not set, then ignore the passed in start/end - * values and set start/end to the default not protected range - * which satisfies start > end - */ - start = FLASH_WRP_MASK; - end = 0; - } - - if (region == WRP_RO) { - /* For RO can always use start/end directly */ - STM32_FLASH_WRP1AR = FLASH_WRP_RANGE(start, end); - } else if (region == WRP_RW) { -#ifdef STM32_FLASH_DBANK_MODE - /* - * In the dual-bank flash case (STM32G4 Category 3 devices with - * DB bit set), RW write protect can use both WRP1BR and WRP2AR - * registers in order to span the full flash memory range. - */ - if (wrp->enable) { - int rw_end; - - /* - * If the 1st RW flash page is in the 1st half of - * memory, then at least one block will be protected by - * WRP1BR. If the end flash page is in the 2nd half of - * memory, then cap the end for WRP1BR to its max - * value. Otherwise, can use end passed in directly. - */ - if (start <= FLASH_WRP_MASK) { - rw_end = end > FLASH_WRP_MASK ? - FLASH_WRP_MASK : end; - STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, - rw_end); - } - /* - * If the last RW flash page is in the 2nd half of - * memory, then at least one block will be protected by - * WRP2AR. If the start flash page is in the 2nd half of - * memory, can use start directly. Otherwise, start - * needs to be set to 0 here. - */ - if (end > FLASH_WRP_MASK) { - rw_end = end & FLASH_WRP_MASK; - STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(0, rw_end); - } - } else { - /* - * RW write protect is being disabled. Set both WRP1BR - * and WRP2AR to default start > end not protected - * state. - */ - STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end); - STM32_FLASH_WRP2AR = FLASH_WRP_RANGE(start, end); - } -#else - /* Single bank case, WRP1BR can cover the full memory range */ - STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, end); -#endif - } -} - -static void unprotect_all_blocks(void) -{ - struct wrp_info wrp; - - /* Set info values to unprotected */ - wrp.start = FLASH_WRP_MASK; - wrp.end = 0; - wrp.enable = 0; - - unlock_optb(); - /* Disable RO WRP */ - optb_set_wrp(WRP_RO, &wrp); - /* Disable RW WRP */ - optb_set_wrp(WRP_RW, &wrp); - commit_optb(); -} - -int crec_flash_physical_protect_at_boot(uint32_t new_flags) -{ - struct wrp_info wrp_ro; - struct wrp_info wrp_rw; - - wrp_ro.start = FLASH_WRP_MASK; - wrp_ro.end = 0; - wrp_ro.enable = 0; - - wrp_rw.start = FLASH_WRP_MASK; - wrp_rw.end = 0; - wrp_rw.enable = 0; - - /* - * Default operation for this function is to disable both RO and RW - * write protection in the option bytes. Based on new_flags either RO or - * RW or both regions write protect may be set. - */ - if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_RO_AT_BOOT)) { - wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX; - wrp_ro.end = FLASH_RO_LAST_PAGE_IDX; - wrp_ro.enable = 1; - } - - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) { - wrp_rw.start = FLASH_RW_FIRST_PAGE_IDX; - wrp_rw.end = FLASH_RW_LAST_PAGE_IDX; - wrp_rw.enable = 1; - } else { - /* - * Start index will be 1st index following RO region index. The - * end index is initialized as 'no protect' value. Only if end - * gets changed based on either rollback or RW protection will - * the 2nd memory protection area get written in option bytes. - */ - int start = FLASH_RW_FIRST_PAGE_IDX; - int end = 0; -#ifdef CONFIG_ROLLBACK - if (new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) { - start = FLASH_PAGE_ROLLBACK_FIRST_IDX; - end = FLASH_PAGE_ROLLBACK_LAST_IDX; - } else { - start = FLASH_PAGE_ROLLBACK_LAST_IDX; - } -#endif /* !CONFIG_ROLLBACK */ -#ifdef CONFIG_FLASH_PROTECT_RW - if (new_flags & EC_FLASH_PROTECT_RW_AT_BOOT) - end = FLASH_RW_LAST_PAGE_IDX; -#endif /* CONFIG_FLASH_PROTECT_RW */ - - if (end) { - wrp_rw.start = start; - wrp_rw.end = end; - wrp_rw.enable = 1; - } - } - - unlock_optb(); -#ifdef CONFIG_FLASH_READOUT_PROTECTION - /* - * Set a permanent protection by increasing RDP to level 1, - * trying to unprotected the flash will trigger a full erase. - */ - STM32_FLASH_OPTR = (STM32_FLASH_OPTR & ~0xff) | 0x11; -#endif - optb_set_wrp(WRP_RO, &wrp_ro); - optb_set_wrp(WRP_RW, &wrp_rw); - commit_optb(); - - return EC_SUCCESS; -} - -/** - * Check if write protect register state is inconsistent with RO_AT_BOOT and - * ALL_AT_BOOT state. - * - * @return zero if consistent, non-zero if inconsistent. - */ -static int registers_need_reset(void) -{ - uint32_t flags = crec_flash_get_protect(); - int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0; - /* The RO region is write-protected by the WRP1AR range. */ - uint32_t wrp1ar = STM32_OPTB_WRP1AR; - uint32_t ro_range = ro_at_boot ? - FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX, - FLASH_RO_LAST_PAGE_IDX) - : FLASH_WRP_RANGE_DISABLED; - - return ro_range != (wrp1ar & FLASH_WRP1X_MASK); -} - -/*****************************************************************************/ -/* Physical layer APIs */ - -int crec_flash_physical_write(int offset, int size, const char *data) -{ - uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - int res = EC_SUCCESS; - int timeout = calculate_flash_timeout(); - int i; - int unaligned = (uint32_t)data & (STM32_FLASH_MIN_WRITE_SIZE - 1); - uint32_t *data32 = (void *)data; - - /* Check Flash offset */ - if (offset % STM32_FLASH_MIN_WRITE_SIZE) - return EC_ERROR_MEMORY_ALLOCATION; - - if (unlock(FLASH_CR_LOCK) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ERR_MASK; - - /* set PG bit */ - STM32_FLASH_CR |= FLASH_CR_PG; - - for (; size > 0; size -= STM32_FLASH_MIN_WRITE_SIZE) { - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing. - */ - watchdog_reload(); - - /* wait to be ready */ - for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); - i++) - ; - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* write the 2 words */ - if (unaligned) { - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); - *address++ = (uint32_t)data[4] | (data[5] << 8) - | (data[6] << 16) | (data[7] << 24); - data += STM32_FLASH_MIN_WRITE_SIZE; - } else { - *address++ = *data32++; - *address++ = *data32++; - } - - /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); - i++) - ; - - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error. - */ - if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Disable PG bit */ - STM32_FLASH_CR &= ~FLASH_CR_PG; - - lock(); - - return res; -} - -int crec_flash_physical_erase(int offset, int size) -{ - int res = EC_SUCCESS; - int pg; - int last; - - if (unlock(FLASH_CR_LOCK) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_SR = FLASH_SR_ERR_MASK; - - last = (offset + size) / CONFIG_FLASH_ERASE_SIZE; - for (pg = offset / CONFIG_FLASH_ERASE_SIZE; pg < last; pg++) { - timestamp_t deadline; - - /* select page to erase and PER bit */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) - | FLASH_CR_PER | FLASH_CR_PNB(pg); - - /* set STRT bit : start erase */ - STM32_FLASH_CR |= FLASH_CR_STRT; - - /* - * Reload the watchdog timer to avoid watchdog reset during a - * long erase operation. - */ - watchdog_reload(); - - deadline.val = get_time().val + FLASH_TIMEOUT_US; - /* Wait for erase to complete */ - while ((STM32_FLASH_SR & FLASH_SR_BUSY) && - (get_time().val < deadline.val)) { - usleep(300); - } - if (STM32_FLASH_SR & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & FLASH_SR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } - } - -exit_er: - /* reset PER bit */ - STM32_FLASH_CR &= ~(FLASH_CR_PER | FLASH_CR_PNB_MASK); - - lock(); - - return res; -} - -int crec_flash_physical_get_protect(int block) -{ - struct wrp_info wrp_ro; - struct wrp_info wrp_rw; - - optb_get_wrp(WRP_RO, &wrp_ro); - optb_get_wrp(WRP_RW, &wrp_rw); - - return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) || - ((block >= wrp_rw.start) && (block <= wrp_rw.end)); -} - -/* - * Note: This does not need to update _NOW flags, as get_protect_flags - * in common code already does so. - */ -uint32_t crec_flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - struct wrp_info wrp_ro; - struct wrp_info wrp_rw; - - optb_get_wrp(WRP_RO, &wrp_ro); - optb_get_wrp(WRP_RW, &wrp_rw); - - /* Check if RO is fully protected */ - if (wrp_ro.start == FLASH_RO_FIRST_PAGE_IDX && - wrp_ro.end == FLASH_RO_LAST_PAGE_IDX) - flags |= EC_FLASH_PROTECT_RO_AT_BOOT; - - if (wrp_rw.enable) { - -#ifdef CONFIG_ROLLBACK - if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX && - wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX) - flags |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif /* CONFIG_ROLLBACK */ -#ifdef CONFIG_FLASH_PROTECT_RW - if (wrp_rw.end == PHYSICAL_BANKS) - flags |= EC_FLASH_PROTECT_RW_AT_BOOT; -#endif /* CONFIG_FLASH_PROTECT_RW */ - if (wrp_rw.end == PHYSICAL_BANKS && - wrp_rw.start == WP_BANK_OFFSET + WP_BANK_COUNT && - flags & EC_FLASH_PROTECT_RO_AT_BOOT) - flags |= EC_FLASH_PROTECT_ALL_AT_BOOT; - } - - return flags; -} - -int crec_flash_physical_protect_now(int all) -{ - return EC_ERROR_INVAL; -} - -uint32_t crec_flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | -#ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | -#endif -#ifdef CONFIG_ROLLBACK - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_ROLLBACK_NOW | -#endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * ALL/RW at-boot state can be set if WP GPIO is asserted and can always - * be cleared. - */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; - -#ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_RW_AT_BOOT; -#endif - -#ifdef CONFIG_ROLLBACK - if (cur_flags & (EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; -#endif - - return ret; -} - -int crec_flash_physical_force_reload(void) -{ - int rv = unlock(FLASH_CR_OPTLOCK); - - if (rv) - return rv; - - /* Force a reboot; this should never return. */ - STM32_FLASH_CR = FLASH_CR_OBL_LAUNCH; - while (1) - ; - - return EC_ERROR_UNKNOWN; -} - -int crec_flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = crec_flash_get_protect(); - int need_reset = 0; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - /* - * Pstate wants RO protected at boot, but the write - * protect register wasn't set to protect it. Force an - * update to the write protect register and reboot so - * it takes effect. - */ - crec_flash_physical_protect_at_boot( - EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - - if (registers_need_reset()) { - /* - * Write protect register was in an inconsistent state. - * Set it back to a good state and reboot. - * - * TODO(crosbug.com/p/23798): this seems really similar - * to the check above. One of them should be able to - * go away. - */ - crec_flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - } else { - if (prot_flags & EC_FLASH_PROTECT_RO_NOW) { - /* - * Write protect pin unasserted but some section is - * protected. Drop it and reboot. - */ - unprotect_all_blocks(); - need_reset = 1; - } - } - - if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ALL_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { - /* - * ALL_AT_BOOT and ALL_NOW should be both set or both unset - * at boot. If they are not, it must be that the chip requires - * OBL_LAUNCH to be set to reload option bytes. Let's reset - * the system with OBL_LAUNCH set. - * This assumes OBL_LAUNCH is used for hard reset in - * chip/stm32/system.c. - */ - need_reset = 1; - } - -#ifdef CONFIG_FLASH_PROTECT_RW - if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_RW_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { - /* RW_AT_BOOT and RW_NOW do not match. */ - need_reset = 1; - } -#endif - -#ifdef CONFIG_ROLLBACK - if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && - (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) != - !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) { - /* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */ - need_reset = 1; - } -#endif - - if (need_reset) - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - return EC_SUCCESS; -} diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c deleted file mode 100644 index 087ddbf062..0000000000 --- a/chip/stm32/flash-stm32h7.c +++ /dev/null @@ -1,643 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* Flash memory module for STM32H7 family */ - -#include "common.h" -#include "clock.h" -#include "cpu.h" -#include "flash.h" -#include "flash-regs.h" -#include "hooks.h" -#include "registers.h" -#include "panic.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status - */ -#define CYCLE_PER_FLASH_LOOP 2 - -/* Flash 256-bit word programming timeout. */ -#define FLASH_TIMEOUT_US 600 - -/* - * Flash 128-KB block erase timeout. - * Datasheet says maximum is about 4 seconds in x8. - * Real delay seems to be: < 1 second in x64, < 2 seconds in x8. - */ -#define FLASH_ERASE_TIMEOUT_US (4200 * MSEC) - -/* - * Option bytes programming timeout. - * No specification, real delay seems to be around 300ms. - */ -#define FLASH_OPT_PRG_TIMEOUT_US (1000 * MSEC) - -/* - * All variants have 2 banks (as in parallel hardware / controllers) - * not what is called 'bank' in the common code (ie Write-Protect sectors) - * both have the same number of 128KB blocks. - */ -#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) -#define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) -#define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) - -/* - * We can tune the power consumption vs erase/write speed - * by default, go fast (and consume current) - */ -#define DEFAULT_PSIZE FLASH_CR_PSIZE_DWORD - -/* Can no longer write/erase flash until next reboot */ -static int access_disabled; -/* Can no longer modify write-protection in option bytes until next reboot */ -static int option_disabled; -/* Is physical flash stuck protected? (avoid reboot loop) */ -static int stuck_locked; - -#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ -#define FLASH_HOOK_VERSION 1 - -/* The previous write protect state before sys jump */ -struct flash_wp_state { - int access_disabled; - int option_disabled; - int stuck_locked; -}; - -static inline int calculate_flash_timeout(void) -{ - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); -} - -static int unlock(int bank) -{ - /* unlock CR only if needed */ - if (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) { - /* - * We may have already locked the flash module and get a bus - * fault in the attempt to unlock. Need to disable bus fault - * handler now. - */ - ignore_bus_fault(1); - - STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR(bank) = FLASH_KEYR_KEY2; - ignore_bus_fault(0); - } - - return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; -} - -static void lock(int bank) -{ - STM32_FLASH_CR(bank) |= FLASH_CR_LOCK; -} - -static int unlock_optb(void) -{ - if (option_disabled) - return EC_ERROR_ACCESS_DENIED; - - if (unlock(0)) - return EC_ERROR_UNKNOWN; - - if (flash_option_bytes_locked()) { - /* - * We may have already locked the flash module and get a bus - * fault in the attempt to unlock. Need to disable bus fault - * handler now. - */ - ignore_bus_fault(1); - - unlock_flash_option_bytes(); - ignore_bus_fault(0); - } - - return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN - : EC_SUCCESS; -} - -static int commit_optb(void) -{ - /* might use this before timer_init, cannot use get_time/usleep */ - int timeout = (FLASH_OPT_PRG_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); - - STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART; - - while (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_BUSY && timeout-- > 0) - ; - - lock_flash_option_bytes(); - lock(0); - - return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; -} - -static void protect_blocks(uint32_t blocks) -{ - if (unlock_optb()) - return; - STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK); - STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK) - & BLOCKS_HWBANK_MASK); - commit_optb(); -} - - -/* - * Helper function definitions for consistency with F4 to enable flash - * physical unitesting - */ -void unlock_flash_control_register(void) -{ - unlock(0); - unlock(1); -} - -void unlock_flash_option_bytes(void) -{ - /* - * Always use bank 0 flash controller as there is only one option bytes - * set for both banks. See http://b/181130245 - * - * Consecutively program values. Ref: RM0433:4.9.2 - */ - STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR(0) = FLASH_OPTKEYR_KEY2; -} - -void disable_flash_option_bytes(void) -{ - ignore_bus_fault(1); - /* - * Always use bank 0 flash controller as there is only one option bytes - * set for both banks. See http://b/181130245 - * - * Writing anything other than the pre-defined keys to the option key - * register results in a bus fault and the register being locked until - * reboot (even with a further correct key write). - */ - STM32_FLASH_OPTKEYR(0) = 0xffffffff; - ignore_bus_fault(0); -} - -void disable_flash_control_register(void) -{ - ignore_bus_fault(1); - /* - * Writing anything other than the pre-defined keys to a key - * register results in a bus fault and the register being locked until - * reboot (even with a further correct key write). - */ - STM32_FLASH_KEYR(0) = 0xffffffff; - STM32_FLASH_KEYR(1) = 0xffffffff; - ignore_bus_fault(0); -} - -void lock_flash_control_register(void) -{ - lock(0); - lock(1); -} - -void lock_flash_option_bytes(void) -{ - /* - * Always use bank 0 flash controller as there is only one option bytes - * set for both banks. See http://b/181130245 - */ - STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTLOCK; -} - -bool flash_option_bytes_locked(void) -{ - /* - * Always use bank 0 flash controller as there is only one option bytes - * set for both banks. See http://b/181130245 - */ - return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK); -} - -bool flash_control_register_locked(void) -{ - return !!(STM32_FLASH_CR(0) & FLASH_CR_LOCK) && - !!(STM32_FLASH_CR(1) & FLASH_CR_LOCK); -} - -/* - * If RDP as PSTATE option is defined, use that as 'Write Protect enabled' flag: - * it makes no sense to be able to unlock RO, as that'd allow flashing - * arbitrary RO that could read back all flash. - * - * crbug.com/888109: Do not copy this code over to other STM32 chips without - * understanding the full implications. - * - * If RDP is not defined, use the option bytes RSS1 bit. - * TODO(crbug.com/888104): Validate that using RSS1 for this purpose is safe. - */ -#ifndef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE -#error "crbug.com/888104: Using RSS1 for write protect PSTATE may not be safe." -#endif -static int is_wp_enabled(void) -{ -#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) - != FLASH_OPTSR_RDP_LEVEL_0; -#else - return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1); -#endif -} - -static int set_wp(int enabled) -{ - int rv; - - rv = unlock_optb(); - if (rv) - return rv; - -#ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - if (enabled) { - /* Enable RDP level 1. */ - STM32_FLASH_OPTSR_PRG(0) = - (STM32_FLASH_OPTSR_PRG(0) & ~FLASH_OPTSR_RDP_MASK) | - FLASH_OPTSR_RDP_LEVEL_1; - } -#else - if (enabled) - STM32_FLASH_OPTSR_PRG(0) |= FLASH_OPTSR_RSS1; - else - STM32_FLASH_OPTSR_PRG(0) &= ~FLASH_OPTSR_RSS1; -#endif - - return commit_optb(); -} - -/*****************************************************************************/ -/* Physical layer APIs */ - -int crec_flash_physical_write(int offset, int size, const char *data) -{ - int res = EC_SUCCESS; - int bank = offset / HWBANK_SIZE; - uint32_t *address = (void *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - int timeout = calculate_flash_timeout(); - int i; - int unaligned = (uint32_t)data & (CONFIG_FLASH_WRITE_SIZE - 1); - uint32_t *data32 = (void *)data; - - if (access_disabled) - return EC_ERROR_ACCESS_DENIED; - - /* work on a single hardware bank at a time */ - if ((offset + size - 1) / HWBANK_SIZE != bank) - return EC_ERROR_INVAL; - - if (unlock(bank) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; - - /* select write parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; - - /* set PG bit */ - STM32_FLASH_CR(bank) |= FLASH_CR_PG; - - for (; size > 0; size -= CONFIG_FLASH_WRITE_SIZE) { - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing. - */ - watchdog_reload(); - - /* write a 256-bit flash word */ - if (unaligned) { - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++, - data += 4) - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); - } else { - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++) - *address++ = *data32++; - } - - /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR(bank) & - (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++) - ; - - if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Disable PG bit */ - STM32_FLASH_CR(bank) &= ~FLASH_CR_PG; - - lock(bank); - -#ifdef CONFIG_ARMV7M_CACHE - /* Invalidate D-cache, to make sure we do not read back stale data. */ - cpu_clean_invalidate_dcache(); -#endif - - return res; -} - -int crec_flash_physical_erase(int offset, int size) -{ - int res = EC_SUCCESS; - int bank = offset / HWBANK_SIZE; - int last = (offset + size) / CONFIG_FLASH_ERASE_SIZE; - int sect; - - if (access_disabled) - return EC_ERROR_ACCESS_DENIED; - - /* work on a single hardware bank at a time */ - if ((offset + size - 1) / HWBANK_SIZE != bank) - return EC_ERROR_INVAL; - - if (unlock(bank) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - - /* Clear previous error status */ - STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; - - /* select erase parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; - - for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) { - timestamp_t deadline; - - /* select page to erase and PER bit */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) - & ~FLASH_CR_SNB_MASK) - | FLASH_CR_SER | FLASH_CR_SNB(sect); - - /* set STRT bit : start erase */ - STM32_FLASH_CR(bank) |= FLASH_CR_STRT; - - /* - * Reload the watchdog timer to avoid watchdog reset during a - * long erase operation. - */ - watchdog_reload(); - - deadline.val = get_time().val + FLASH_ERASE_TIMEOUT_US; - /* Wait for erase to complete */ - while ((STM32_FLASH_SR(bank) & FLASH_SR_BUSY) && - (get_time().val < deadline.val)) { - /* - * Interrupts may not be enabled, so we are using - * udelay() instead of usleep() which can trigger - * Forced Hard Fault (see b/180761547). - */ - udelay(5000); - } - if (STM32_FLASH_SR(bank) & FLASH_SR_BUSY) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions - erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR(bank) & FLASH_CCR_ERR_MASK) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } - } - -exit_er: - /* reset SER bit */ - STM32_FLASH_CR(bank) &= ~(FLASH_CR_SER | FLASH_CR_SNB_MASK); - - lock(bank); - -#ifdef CONFIG_ARMV7M_CACHE - /* Invalidate D-cache, to make sure we do not read back stale data. */ - cpu_clean_invalidate_dcache(); -#endif - - return res; -} - -int crec_flash_physical_get_protect(int block) -{ - int bank = block / BLOCKS_PER_HWBANK; - int index = block % BLOCKS_PER_HWBANK; - - return !(STM32_FLASH_WPSN_CUR(bank) & BIT(index)); -} - -/* - * Note: This does not need to update _NOW flags, as flash_get_protect - * in common code already does so. - */ -uint32_t crec_flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - if (access_disabled) - flags |= EC_FLASH_PROTECT_ALL_NOW; - - if (is_wp_enabled()) - flags |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* Check if blocks were stuck locked at pre-init */ - if (stuck_locked) - flags |= EC_FLASH_PROTECT_ERROR_STUCK; - - return flags; -} - -#define WP_RANGE(start, count) (((1 << (count)) - 1) << (start)) -#define RO_WP_RANGE WP_RANGE(WP_BANK_OFFSET, WP_BANK_COUNT) - -int crec_flash_physical_protect_now(int all) -{ - protect_blocks(RO_WP_RANGE); - - /* - * Lock the option bytes or the full access by writing a wrong - * key to FLASH_*KEYR. This triggers a bus fault, so we need to - * disable bus fault handler while doing this. - * - * This incorrect key fault causes the flash to become - * permanently locked until reset, a correct keyring write - * will not unlock it. - */ - - if (all) { - /* cannot do any write/erase access until next reboot */ - disable_flash_control_register(); - access_disabled = 1; - } - /* cannot modify the WP bits in the option bytes until reboot */ - disable_flash_option_bytes(); - option_disabled = 1; - - return EC_SUCCESS; -} - -int crec_flash_physical_protect_at_boot(uint32_t new_flags) -{ - int new_wp_enable = !!(new_flags & EC_FLASH_PROTECT_RO_AT_BOOT); - - if (is_wp_enabled() != new_wp_enable) - return set_wp(new_wp_enable); - - return EC_SUCCESS; -} - -uint32_t crec_flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -int crec_flash_physical_restore_state(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - int version, size; - const struct flash_wp_state *prev; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. We simply need to represent these - * irreversible flags to other components. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) { - prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); - if (prev && version == FLASH_HOOK_VERSION && - size == sizeof(*prev)) { - access_disabled = prev->access_disabled; - option_disabled = prev->option_disabled; - stuck_locked = prev->stuck_locked; - } - return 1; - } - - return 0; -} - -int crec_flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = crec_flash_get_protect(); - uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; - - if (crec_flash_physical_restore_state()) - return EC_SUCCESS; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - /* - * Write protect is asserted. If we want RO flash protected, - * protect it now. - */ - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - int rv; - - rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, - EC_FLASH_PROTECT_RO_NOW); - if (rv) - return rv; - - /* Re-read flags */ - prot_flags = crec_flash_get_protect(); - } - } else { - /* Don't want RO flash protected */ - unwanted_prot_flags |= EC_FLASH_PROTECT_RO_NOW; - } - - /* If there are no unwanted flags, done */ - if (!(prot_flags & unwanted_prot_flags)) - return EC_SUCCESS; - - /* - * If the last reboot was a power-on reset, it should have cleared - * write-protect. If it didn't, then the flash write protect registers - * have been permanently committed and we can't fix that. - */ - if (reset_flags & EC_RESET_FLAG_POWER_ON) { - stuck_locked = 1; - return EC_ERROR_ACCESS_DENIED; - } - - /* Otherwise, do a hard boot to clear the flash protection registers */ - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - /* That doesn't return, so if we're still here that's an error */ - return EC_ERROR_UNKNOWN; -} - -/*****************************************************************************/ -/* Hooks */ - -static void flash_preserve_state(void) -{ - const struct flash_wp_state state = { - .access_disabled = access_disabled, - .option_disabled = option_disabled, - .stuck_locked = stuck_locked, - }; - - system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, - sizeof(state), &state); -} -DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c deleted file mode 100644 index f34200219a..0000000000 --- a/chip/stm32/flash-stm32l.c +++ /dev/null @@ -1,480 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Flash memory module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "flash.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Approximate number of CPU cycles per iteration of the loop when polling - * the flash status. - */ -#define CYCLE_PER_FLASH_LOOP 10 - -/* Flash page programming timeout. This is 2x the datasheet max. */ -#define FLASH_TIMEOUT_MS 16 - -static int flash_timeout_loop; - -/** - * Lock all the locks. - */ -static void lock(void) -{ - ignore_bus_fault(1); - - STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK | - STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK; - - ignore_bus_fault(0); -} - -/** - * Unlock the specified locks. - */ -static int unlock(int locks) -{ - /* - * We may have already locked the flash module and get a bus fault - * in the attempt to unlock. Need to disable bus fault handler now. - */ - ignore_bus_fault(1); - - /* Unlock PECR if needed */ - if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) { - STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY1; - STM32_FLASH_PEKEYR = STM32_FLASH_PEKEYR_KEY2; - } - - /* Fail if it didn't unlock */ - if (STM32_FLASH_PECR & STM32_FLASH_PECR_PE_LOCK) { - ignore_bus_fault(0); - return EC_ERROR_ACCESS_DENIED; - } - - /* Unlock program memory if required */ - if ((locks & STM32_FLASH_PECR_PRG_LOCK) && - (STM32_FLASH_PECR & STM32_FLASH_PECR_PRG_LOCK)) { - STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY1; - STM32_FLASH_PRGKEYR = STM32_FLASH_PRGKEYR_KEY2; - } - - /* Unlock option memory if required */ - if ((locks & STM32_FLASH_PECR_OPT_LOCK) && - (STM32_FLASH_PECR & STM32_FLASH_PECR_OPT_LOCK)) { - STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = STM32_FLASH_OPTKEYR_KEY2; - } - - ignore_bus_fault(0); - - /* Successful if we unlocked everything we wanted */ - if (!(STM32_FLASH_PECR & (locks | STM32_FLASH_PECR_PE_LOCK))) - return EC_SUCCESS; - - /* Otherwise relock everything and return error */ - lock(); - return EC_ERROR_ACCESS_DENIED; -} - -/** - * Read an option byte word. - * - * Option bytes are stored in pairs in 32-bit registers; the upper 16 bits is - * the 1's compliment of the lower 16 bits. - */ -static uint16_t read_optb(int offset) -{ - return REG16(STM32_OPTB_BASE + offset); -} - -/** - * Write an option byte word. - * - * Requires OPT_LOCK unlocked. - */ -static void write_optb(int offset, uint16_t value) -{ - REG32(STM32_OPTB_BASE + offset) = - (uint32_t)value | ((uint32_t)(~value) << 16); -} - -/** - * Read the at-boot protection option bits. - */ -static uint32_t read_optb_wrp(void) -{ - return read_optb(STM32_OPTB_WRP1L) | - ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); -} - -/** - * Write the at-boot protection option bits. - */ -static void write_optb_wrp(uint32_t value) -{ - write_optb(STM32_OPTB_WRP1L, (uint16_t)value); - write_optb(STM32_OPTB_WRP1H, value >> 16); -} - -/** - * Write data to flash. - * - * This function lives in internal RAM, as we cannot read flash during writing. - * You must not call other functions from this one or declare it static. - */ -void __attribute__((section(".iram.text"))) - iram_flash_write(uint32_t *addr, uint32_t *data) -{ - int i; - - /* Wait for ready */ - for (i = 0; (STM32_FLASH_SR & 1) && (i < flash_timeout_loop); i++) - ; - - /* Set PROG and FPRG bits */ - STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG; - - /* Send words for the half page */ - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); i++) - *addr++ = *data++; - - /* Wait for writes to complete */ - for (i = 0; ((STM32_FLASH_SR & 9) != 8) && (i < flash_timeout_loop); - i++) - ; - - /* Disable PROG and FPRG bits */ - STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_FPRG); -} - -int crec_flash_physical_write(int offset, int size, const char *data) -{ - uint32_t *data32 = (uint32_t *)data; - uint32_t *address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - int res = EC_SUCCESS; - int word_mode = 0; - int i; - - /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size | (uint32_t)(uintptr_t)data) & 3) - return EC_ERROR_INVAL; - - /* Unlock program area */ - res = unlock(STM32_FLASH_PECR_PRG_LOCK); - if (res) - goto exit_wr; - - /* Clear previous error status */ - STM32_FLASH_SR = 0xf00; - - /* - * If offset and size aren't on word boundaries, do word writes. This - * is slower, but since we claim to the outside world that writes must - * be half-page size, the only code which hits this path is writing - * pstate (which is just writing one word). - */ - if ((offset | size) & (CONFIG_FLASH_WRITE_SIZE - 1)) - word_mode = 1; - - /* Update flash timeout based on current clock speed */ - flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) / - CYCLE_PER_FLASH_LOOP; - - while (size > 0) { - /* - * Reload the watchdog timer to avoid watchdog reset when doing - * long writing with interrupt disabled. - */ - watchdog_reload(); - - if (word_mode) { - /* Word write */ - *address++ = *data32++; - - /* Wait for writes to complete */ - for (i = 0; ((STM32_FLASH_SR & 9) != 8) && - (i < flash_timeout_loop); i++) - ; - - size -= sizeof(uint32_t); - } else { - /* Half page write */ - interrupt_disable(); - iram_flash_write(address, data32); - interrupt_enable(); - address += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); - data32 += CONFIG_FLASH_WRITE_SIZE / sizeof(uint32_t); - size -= CONFIG_FLASH_WRITE_SIZE; - } - - if (STM32_FLASH_SR & 1) { - res = EC_ERROR_TIMEOUT; - goto exit_wr; - } - - /* - * Check for error conditions: erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & 0xf00) { - res = EC_ERROR_UNKNOWN; - goto exit_wr; - } - } - -exit_wr: - /* Relock program lock */ - lock(); - - return res; -} - -int crec_flash_physical_erase(int offset, int size) -{ - uint32_t *address; - int res = EC_SUCCESS; - - res = unlock(STM32_FLASH_PECR_PRG_LOCK); - if (res) - return res; - - /* Clear previous error status */ - STM32_FLASH_SR = 0xf00; - - /* Set PROG and ERASE bits */ - STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE; - - for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); - size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { - timestamp_t deadline; - - /* Do nothing if already erased */ - if (crec_flash_is_erased((uint32_t)address - - CONFIG_PROGRAM_MEMORY_BASE, - CONFIG_FLASH_ERASE_SIZE)) - continue; - - /* Start erase */ - *address = 0x00000000; - - /* - * Reload the watchdog timer to avoid watchdog reset during - * multi-page erase operations. - */ - watchdog_reload(); - - deadline.val = get_time().val + FLASH_TIMEOUT_MS * MSEC; - /* Wait for erase to complete */ - while ((STM32_FLASH_SR & 1) && - (get_time().val < deadline.val)) { - usleep(300); - } - if (STM32_FLASH_SR & 1) { - res = EC_ERROR_TIMEOUT; - goto exit_er; - } - - /* - * Check for error conditions: erase failed, voltage error, - * protection error - */ - if (STM32_FLASH_SR & 0xF00) { - res = EC_ERROR_UNKNOWN; - goto exit_er; - } - } - -exit_er: - /* Disable program and erase, and relock PECR */ - STM32_FLASH_PECR &= ~(STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE); - lock(); - - return res; -} - -int crec_flash_physical_get_protect(int block) -{ - /* - * If the entire flash interface is locked, then all blocks are - * protected until reboot. - */ - if (crec_flash_physical_get_protect_flags() & EC_FLASH_PROTECT_ALL_NOW) - return 1; - - /* Check the active write protect status */ - return STM32_FLASH_WRPR & BIT(block); -} - -int crec_flash_physical_protect_at_boot(uint32_t new_flags) -{ - uint32_t prot; - uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; - int rv; - - if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) - return EC_ERROR_UNIMPLEMENTED; - - /* Read the current protection status */ - prot = read_optb_wrp(); - - /* Set/clear bits */ - if (new_flags & EC_FLASH_PROTECT_RO_AT_BOOT) - prot |= mask; - else - prot &= ~mask; - - if (prot == read_optb_wrp()) - return EC_SUCCESS; /* No bits changed */ - - /* Unlock option bytes */ - rv = unlock(STM32_FLASH_PECR_OPT_LOCK); - if (rv) - return rv; - - /* Update them */ - write_optb_wrp(prot); - - /* Relock */ - lock(); - - return EC_SUCCESS; -} - -int crec_flash_physical_force_reload(void) -{ - int rv = unlock(STM32_FLASH_PECR_OPT_LOCK); - - if (rv) - return rv; - - /* Force a reboot; this should never return. */ - STM32_FLASH_PECR = STM32_FLASH_PECR_OBL_LAUNCH; - while (1) - ; - - return EC_ERROR_UNKNOWN; -} - -uint32_t crec_flash_physical_get_protect_flags(void) -{ - uint32_t flags = 0; - - /* - * Try to unlock PECR; if that fails, then all flash is protected for - * the current boot. - */ - if (unlock(STM32_FLASH_PECR_PE_LOCK)) - flags |= EC_FLASH_PROTECT_ALL_NOW; - lock(); - - return flags; -} - -int crec_flash_physical_protect_now(int all) -{ - if (all) { - /* Re-lock the registers if they're unlocked */ - lock(); - - /* Prevent unlocking until reboot */ - ignore_bus_fault(1); - STM32_FLASH_PEKEYR = 0; - ignore_bus_fault(0); - - return EC_SUCCESS; - } else { - /* No way to protect just the RO flash until next boot */ - return EC_ERROR_INVAL; - } -} - -uint32_t crec_flash_physical_get_valid_flags(void) -{ - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; -} - -uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) -{ - uint32_t ret = 0; - - /* If RO protection isn't enabled, its at-boot state can be changed. */ - if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) - ret |= EC_FLASH_PROTECT_RO_AT_BOOT; - - /* - * If entire flash isn't protected at this boot, it can be enabled if - * the WP GPIO is asserted. - */ - if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) - ret |= EC_FLASH_PROTECT_ALL_NOW; - - return ret; -} - -int crec_flash_pre_init(void) -{ - uint32_t reset_flags = system_get_reset_flags(); - uint32_t prot_flags = crec_flash_get_protect(); - int need_reset = 0; - - /* - * If we have already jumped between images, an earlier image could - * have applied write protection. Nothing additional needs to be done. - */ - if (reset_flags & EC_RESET_FLAG_SYSJUMP) - return EC_SUCCESS; - - if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { - if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && - !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - /* - * Pstate wants RO protected at boot, but the write - * protect register wasn't set to protect it. Force an - * update to the write protect register and reboot so - * it takes effect. - */ - crec_flash_protect_at_boot(EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - - if (prot_flags & EC_FLASH_PROTECT_ERROR_INCONSISTENT) { - /* - * Write protect register was in an inconsistent state. - * Set it back to a good state and reboot. - */ - crec_flash_protect_at_boot(prot_flags & - EC_FLASH_PROTECT_RO_AT_BOOT); - need_reset = 1; - } - } else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT)) { - /* - * Write protect pin unasserted but some section is - * protected. Drop it and reboot. - */ - unlock(STM32_FLASH_PECR_OPT_LOCK); - write_optb_wrp(0); - lock(); - need_reset = 1; - } - - if (need_reset) - system_reset(SYSTEM_RESET_HARD | SYSTEM_RESET_PRESERVE_FLAGS); - - return EC_SUCCESS; -} diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c deleted file mode 100644 index 55628cb6d4..0000000000 --- a/chip/stm32/gpio-f0-l.c +++ /dev/null @@ -1,180 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * GPIO module for Chrome EC - * - * These functions are shared by the STM32F0 and STM32L variants. - */ - -#include "common.h" -#include "gpio_chip.h" -#include "registers.h" -#include "util.h" - -static uint32_t expand_to_2bit_mask(uint32_t mask) -{ - uint32_t mask_out = 0; - while (mask) { - int bit = get_next_bit(&mask); - mask_out |= 3 << (bit * 2); - } - return mask_out; -} - -int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) -{ - uint32_t flags = 0; - uint32_t val = 0; - const uint32_t mask2 = expand_to_2bit_mask(mask); - - /* Only one bit must be set. */ - if ((mask != (mask & -mask)) || (mask == 0)) - return 0; - - /* Check output type. */ - val = STM32_GPIO_PUPDR(port) & mask2; - if (val == (0x55555555 & mask2)) - flags |= GPIO_PULL_UP; - if (val == (0xaaaaaaaa & mask2)) - flags |= GPIO_PULL_DOWN; - - if (STM32_GPIO_OTYPER(port) & mask) - flags |= GPIO_OPEN_DRAIN; - - /* Check mode. */ - val = STM32_GPIO_MODER(port) & mask2; - if (val == (0x55555555 & mask2)) - flags |= GPIO_OUTPUT; - if (val == (0xFFFFFFFF & mask2)) - flags |= GPIO_ANALOG; - if (val == (0x0 & mask2)) - flags |= GPIO_INPUT; - if (val == (0xaaaaaaaa & mask2)) - flags |= GPIO_ALTERNATE; - - if (flags & GPIO_OUTPUT) { - if (STM32_GPIO_ODR(port) & mask) - flags |= GPIO_HIGH; - else - flags |= GPIO_LOW; - } - - - if (STM32_EXTI_RTSR & mask) - flags |= GPIO_INT_F_RISING; - if (STM32_EXTI_RTSR & mask) - flags |= GPIO_INT_F_RISING; - - return flags; -} - -void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) -{ - /* Bitmask for registers with 2 bits per GPIO pin */ - const uint32_t mask2 = expand_to_2bit_mask(mask); - uint32_t val; - - /* Set up pullup / pulldown */ - val = STM32_GPIO_PUPDR(port) & ~mask2; - if (flags & GPIO_PULL_UP) - val |= 0x55555555 & mask2; /* Pull Up = 01 */ - else if (flags & GPIO_PULL_DOWN) - val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */ - STM32_GPIO_PUPDR(port) = val; - - /* - * Select open drain first, so that we don't glitch the signal when - * changing the line to an output. - */ - if (flags & GPIO_OPEN_DRAIN) - STM32_GPIO_OTYPER(port) |= mask; - else - STM32_GPIO_OTYPER(port) &= ~mask; - - val = STM32_GPIO_MODER(port) & ~mask2; - if (flags & GPIO_OUTPUT) { - /* - * Set pin level first to avoid glitching. This is harmless on - * STM32L because the set/reset register isn't connected to the - * output drivers until the pin is made an output. - */ - if (flags & GPIO_HIGH) - STM32_GPIO_BSRR(port) = mask; - else if (flags & GPIO_LOW) - STM32_GPIO_BSRR(port) = mask << 16; - - /* General purpose, MODE = 01 */ - val |= 0x55555555 & mask2; - STM32_GPIO_MODER(port) = val; - - } else if (flags & GPIO_ANALOG) { - /* Analog, MODE=11 */ - val |= 0xFFFFFFFF & mask2; - STM32_GPIO_MODER(port) = val; - } else if (flags & GPIO_INPUT) { - /* Input, MODE=00 */ - STM32_GPIO_MODER(port) = val; - } else if (flags & GPIO_ALTERNATE) { - /* Alternate, MODE=10 */ - val |= 0xaaaaaaaa & mask2; - STM32_GPIO_MODER(port) = val; - } - - /* Set up interrupts if necessary */ - ASSERT(!(flags & (GPIO_INT_F_LOW | GPIO_INT_F_HIGH))); - if (flags & GPIO_INT_F_RISING) - STM32_EXTI_RTSR |= mask; - if (flags & GPIO_INT_F_FALLING) - STM32_EXTI_FTSR |= mask; - /* Interrupt is enabled by gpio_enable_interrupt() */ -} - -void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) -{ - /* Ensure that the func parameter isn't overflowed */ - BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX); - - int bit; - uint32_t half; - uint32_t afr; - uint32_t moder = STM32_GPIO_MODER(port); - - if (func == GPIO_ALT_FUNC_NONE) { - /* Return to normal GPIO function, defaulting to input. */ - while (mask) { - bit = get_next_bit(&mask); - moder &= ~(0x3 << (bit * 2)); - } - STM32_GPIO_MODER(port) = moder; - return; - } - - /* Low half of the GPIO bank */ - half = mask & 0xff; - afr = STM32_GPIO_AFRL(port); - while (half) { - bit = get_next_bit(&half); - afr &= ~(0xf << (bit * 4)); - afr |= func << (bit * 4); - moder &= ~(0x3 << (bit * 2 + 0)); - moder |= 0x2 << (bit * 2 + 0); - } - STM32_GPIO_AFRL(port) = afr; - - /* High half of the GPIO bank */ - half = (mask >> 8) & 0xff; - afr = STM32_GPIO_AFRH(port); - while (half) { - bit = get_next_bit(&half); - afr &= ~(0xf << (bit * 4)); - afr |= func << (bit * 4); - moder &= ~(0x3 << (bit * 2 + 16)); - moder |= 0x2 << (bit * 2 + 16); - } - STM32_GPIO_AFRH(port) = afr; - STM32_GPIO_MODER(port) = moder; -} diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c deleted file mode 100644 index d7e7aa4391..0000000000 --- a/chip/stm32/gpio-stm32f0.c +++ /dev/null @@ -1,39 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHBENR |= 0x7e0000; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0_1); - task_enable_irq(STM32_IRQ_EXTI2_3); - task_enable_irq(STM32_IRQ_EXTI4_15); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c deleted file mode 100644 index bfc2631de8..0000000000 --- a/chip/stm32/gpio-stm32f3.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHBENR |= 0x7e0000; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c deleted file mode 100644 index 4a4e095a71..0000000000 --- a/chip/stm32/gpio-stm32f4.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -int gpio_required_clocks(void) -{ - const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" - ); - - /* - * If no ports are in use, then system_is_reboot_warm - * may not be valid. - */ - ASSERT(gpio_ports_used); - - return gpio_ports_used; -} - -void gpio_enable_clocks(void) -{ - /* Enable only ports that are referenced in the gpio.inc */ - STM32_RCC_AHB1ENR |= gpio_required_clocks(); - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c deleted file mode 100644 index 55b2c11e7b..0000000000 --- a/chip/stm32/gpio-stm32g4.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -int gpio_required_clocks(void) -{ - const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" - ); - - /* - * If no ports are in use, then system_is_reboot_warm - * may not be valid. - */ - ASSERT(gpio_ports_used); - - return gpio_ports_used; -} - -void gpio_enable_clocks(void) -{ - /* Enable only ports that are referenced in the gpio.inc */ - STM32_RCC_AHB2ENR |= gpio_required_clocks(); - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c deleted file mode 100644 index a2fb97225d..0000000000 --- a/chip/stm32/gpio-stm32h7.c +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* Enable all GPIOs clocks */ - STM32_RCC_AHB4ENR |= STM32_RCC_AHB4ENR_GPIOMASK; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); - -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c deleted file mode 100644 index 52c424eea0..0000000000 --- a/chip/stm32/gpio-stm32l.c +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHBENR |= 0x3f; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c deleted file mode 100644 index b5c4940454..0000000000 --- a/chip/stm32/gpio-stm32l4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI9_5); - task_enable_irq(STM32_IRQ_EXTI15_10); - -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c deleted file mode 100644 index 43a7db05da..0000000000 --- a/chip/stm32/gpio-stm32l5.c +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -void gpio_enable_clocks(void) -{ - /* - * Enable all GPIOs clocks - * - * TODO(crosbug.com/p/23770): only enable the banks we need to, - * and support disabling some of them in low-power idle. - */ - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_GPIOMASK; - - /* Delay 1 AHB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_AHB, 1); -} - -static void gpio_init(void) -{ - /* Enable IRQs now that pins are set up */ - task_enable_irq(STM32_IRQ_EXTI0); - task_enable_irq(STM32_IRQ_EXTI1); - task_enable_irq(STM32_IRQ_EXTI2); - task_enable_irq(STM32_IRQ_EXTI3); - task_enable_irq(STM32_IRQ_EXTI4); - task_enable_irq(STM32_IRQ_EXTI5); - task_enable_irq(STM32_IRQ_EXTI6); - task_enable_irq(STM32_IRQ_EXTI7); - task_enable_irq(STM32_IRQ_EXTI8); - task_enable_irq(STM32_IRQ_EXTI9); - task_enable_irq(STM32_IRQ_EXTI10); - task_enable_irq(STM32_IRQ_EXTI11); - task_enable_irq(STM32_IRQ_EXTI12); - task_enable_irq(STM32_IRQ_EXTI13); - task_enable_irq(STM32_IRQ_EXTI14); - task_enable_irq(STM32_IRQ_EXTI15); - -} -DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); - -DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI5, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI6, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI7, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI8, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI9, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI10, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI11, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI12, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI13, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI14, gpio_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_EXTI15, gpio_interrupt, 1); - -#include "gpio-f0-l.c" diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c deleted file mode 100644 index ccfd3399e2..0000000000 --- a/chip/stm32/gpio.c +++ /dev/null @@ -1,177 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* GPIO module for Chrome EC */ - -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio_chip.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -/* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) -/* For each EXTI bit, record which GPIO entry is using it */ -static uint8_t exti_events[16]; - -void gpio_pre_init(void) -{ - const struct gpio_info *g = gpio_list; - const struct unused_pin_info *u = unused_pin_list; - int is_warm = system_is_reboot_warm(); - int i; - - /* Required to configure external IRQ lines (SYSCFG_EXTICRn) */ -#ifdef CHIP_FAMILY_STM32H7 - STM32_RCC_APB4ENR |= STM32_RCC_SYSCFGEN; -#else - STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN; -#endif - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* Disable all GPIO EXTINTs (EXTINT0..15) left enabled after sysjump. */ - STM32_EXTI_IMR &= ~0xFFFF; - - if (!is_warm) - gpio_enable_clocks(); - - /* Set all GPIOs to defaults */ - for (i = 0; i < GPIO_COUNT; i++, g++) { - int flags = g->flags; - - if (flags & GPIO_DEFAULT) - continue; - - /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. - */ - if (is_warm) - flags &= ~(GPIO_LOW | GPIO_HIGH); - - /* Set up GPIO based on flags */ - gpio_set_flags_by_mask(g->port, g->mask, flags); - } - - /* Configure optional unused pins for low power optimization. */ - for (i = 0; i < unused_pin_count; i++, u++) { - /* - * Configure unused pins as ANALOG INPUT to save power. - * For more info, please see - * "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY" - * ("AN4365") section 1.2.6 and section 7.3.12 of the STM32F412 - * reference manual. - */ - if (IS_ENABLED(CHIP_FAMILY_STM32F4)) - gpio_set_flags_by_mask(u->port, u->mask, GPIO_ANALOG); - } -} - -test_mockable int gpio_get_level(enum gpio_signal signal) -{ - return !!(STM32_GPIO_IDR(gpio_list[signal].port) & - gpio_list[signal].mask); -} - -void gpio_set_level(enum gpio_signal signal, int value) -{ - STM32_GPIO_BSRR(gpio_list[signal].port) = - gpio_list[signal].mask << (value ? 0 : 16); -} - -int gpio_enable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - const struct gpio_info *g_old = gpio_list; - - uint32_t bit, group, shift, bank; - - /* Fail if not implemented or no interrupt handler */ - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - bit = GPIO_MASK_TO_NUM(g->mask); - - g_old += exti_events[bit]; - - if ((exti_events[bit]) && (exti_events[bit] != signal)) { - CPRINTS("Overriding %s with %s on EXTI%d", - g_old->name, g->name, bit); - } - exti_events[bit] = signal; - - group = bit / 4; - shift = (bit % 4) * 4; - bank = (g->port - STM32_GPIOA_BASE) / 0x400; - - STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) & - ~(0xF << shift)) | (bank << shift); - STM32_EXTI_IMR |= g->mask; - - return EC_SUCCESS; -} - -int gpio_disable_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - uint32_t bit; - - /* Fail if not implemented or no interrupt handler */ - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - STM32_EXTI_IMR &= ~g->mask; - - bit = GPIO_MASK_TO_NUM(g->mask); - - exti_events[bit] = 0; - - return EC_SUCCESS; -} - -int gpio_clear_pending_interrupt(enum gpio_signal signal) -{ - const struct gpio_info *g = gpio_list + signal; - - if (!g->mask || signal >= GPIO_IH_COUNT) - return EC_ERROR_INVAL; - - /* Write 1 to clear interrupt */ - STM32_EXTI_PR = g->mask; - - return EC_SUCCESS; -} - -/*****************************************************************************/ -/* Interrupt handler */ - -void __keep gpio_interrupt(void) -{ - int bit; - /* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */ - uint32_t pending = STM32_EXTI_PR & 0xFFFF; - uint8_t signal; - - /* Write 1 to clear interrupt */ - STM32_EXTI_PR = pending; - - while (pending) { - bit = get_next_bit(&pending); - signal = exti_events[bit]; - if (signal < GPIO_IH_COUNT) - gpio_irq_handlers[signal](signal); - } -} -#ifdef CHIP_FAMILY_STM32F0 -DECLARE_IRQ(STM32_IRQ_EXTI0_1, gpio_interrupt, STM32_IRQ_EXT0_1_PRIORITY); -DECLARE_IRQ(STM32_IRQ_EXTI2_3, gpio_interrupt, STM32_IRQ_EXT2_3_PRIORITY); -DECLARE_IRQ(STM32_IRQ_EXTI4_15, gpio_interrupt, STM32_IRQ_EXTI4_15_PRIORITY); -#endif diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h deleted file mode 100644 index a5b642fb05..0000000000 --- a/chip/stm32/gpio_chip.h +++ /dev/null @@ -1,22 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CHIP_STM32_GPIO_CHIP_H -#define __CROS_EC_CHIP_STM32_GPIO_CHIP_H - -#include "include/gpio.h" - -/** - * Enable GPIO peripheral clocks. - */ -void gpio_enable_clocks(void); - -/** - * Return gpio port clocks that are necessary to support - * the pins in gpio.inc. - */ -int gpio_required_clocks(void); - -#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */ diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c deleted file mode 100644 index b39a298c64..0000000000 --- a/chip/stm32/host_command_common.c +++ /dev/null @@ -1,46 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "fpsensor_detect.h" -#include "host_command.h" -#include "spi.h" -#include "usart_host_command.h" - -#ifndef CONFIG_I2C_PERIPHERAL - -/* Store current transport type */ -static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN; - -/* - * Get protocol information - */ -static enum ec_status host_command_protocol_info(struct host_cmd_handler_args - *args) -{ - enum ec_status ret_status = EC_RES_INVALID_COMMAND; - - /* - * Read transport type from TRANSPORT_SEL bootstrap pin the first - * time this function is called. - */ - if (IS_ENABLED(CONFIG_FINGERPRINT_MCU) && - (curr_transport_type == FP_TRANSPORT_TYPE_UNKNOWN)) - curr_transport_type = get_fp_transport_type(); - - if (IS_ENABLED(CONFIG_USART_HOST_COMMAND) && - curr_transport_type == FP_TRANSPORT_TYPE_UART) - ret_status = usart_get_protocol_info(args); - else if (IS_ENABLED(CONFIG_SPI) && - curr_transport_type == FP_TRANSPORT_TYPE_SPI) - ret_status = spi_get_protocol_info(args); - - return ret_status; -} -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - host_command_protocol_info, - EC_VER_MASK(0)); - -#endif /* CONFIG_I2C_PERIPHERAL */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c deleted file mode 100644 index 953110017f..0000000000 --- a/chip/stm32/hwtimer.c +++ /dev/null @@ -1,454 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware timers driver */ - -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "watchdog.h" - -/* - * Trigger select mapping for slave timer from master timer. This is - * unfortunately not very straightforward; there's no tidy way to do this - * algorithmically. To avoid burning memory for a lookup table, use macros to - * compute the offset. This also has the benefit that compilation will fail if - * an unsupported master/slave pairing is used. - */ -#ifdef CHIP_FAMILY_STM32F0 -/* - * Slave Master - * 1 15 2 3 17 - * 2 1 15 3 14 - * 3 1 2 15 14 - * 15 2 3 16 17 - * -------------------- - * ts = 0 1 2 3 - */ -#define STM32_TIM_TS_SLAVE_1_MASTER_15 0 -#define STM32_TIM_TS_SLAVE_1_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_1_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_1_MASTER_17 3 -#define STM32_TIM_TS_SLAVE_2_MASTER_1 0 -#define STM32_TIM_TS_SLAVE_2_MASTER_15 1 -#define STM32_TIM_TS_SLAVE_2_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_2_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_3_MASTER_1 0 -#define STM32_TIM_TS_SLAVE_3_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_3_MASTER_15 2 -#define STM32_TIM_TS_SLAVE_3_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_15_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_15_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_15_MASTER_16 2 -#define STM32_TIM_TS_SLAVE_15_MASTER_17 3 -#elif defined(CHIP_FAMILY_STM32F3) -/* - * Slave Master - * 2 19 15 3 14 - * 3 19 2 5 14 - * 4 19 2 3 15 - * 5 2 3 4 15 - * 12 4 5 13 14 - * 19 2 3 15 16 - * --------------------- - * ts = 0 1 2 3 - */ -#define STM32_TIM_TS_SLAVE_2_MASTER_19 0 -#define STM32_TIM_TS_SLAVE_2_MASTER_15 1 -#define STM32_TIM_TS_SLAVE_2_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_2_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_3_MASTER_19 0 -#define STM32_TIM_TS_SLAVE_3_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_3_MASTER_5 2 -#define STM32_TIM_TS_SLAVE_3_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_4_MASTER_19 0 -#define STM32_TIM_TS_SLAVE_4_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_4_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_4_MASTER_15 3 -#define STM32_TIM_TS_SLAVE_5_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_5_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_5_MASTER_4 2 -#define STM32_TIM_TS_SLAVE_5_MASTER_15 3 -#define STM32_TIM_TS_SLAVE_12_MASTER_4 0 -#define STM32_TIM_TS_SLAVE_12_MASTER_5 1 -#define STM32_TIM_TS_SLAVE_12_MASTER_13 2 -#define STM32_TIM_TS_SLAVE_12_MASTER_14 3 -#define STM32_TIM_TS_SLAVE_19_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_19_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_19_MASTER_15 2 -#define STM32_TIM_TS_SLAVE_19_MASTER_16 3 -#else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ -/* - * Slave Master - * 1 15 2 3 4 (STM32F100 only) - * 2 9 10 3 4 - * 3 9 2 11 4 - * 4 10 2 3 9 - * 9 2 3 10 11 (STM32L15x only) - * -------------------- - * ts = 0 1 2 3 - */ -#define STM32_TIM_TS_SLAVE_1_MASTER_15 0 -#define STM32_TIM_TS_SLAVE_1_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_1_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_1_MASTER_4 3 -#define STM32_TIM_TS_SLAVE_2_MASTER_9 0 -#define STM32_TIM_TS_SLAVE_2_MASTER_10 1 -#define STM32_TIM_TS_SLAVE_2_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_2_MASTER_4 3 -#define STM32_TIM_TS_SLAVE_3_MASTER_9 0 -#define STM32_TIM_TS_SLAVE_3_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_3_MASTER_11 2 -#define STM32_TIM_TS_SLAVE_3_MASTER_4 3 -#define STM32_TIM_TS_SLAVE_4_MASTER_10 0 -#define STM32_TIM_TS_SLAVE_4_MASTER_2 1 -#define STM32_TIM_TS_SLAVE_4_MASTER_3 2 -#define STM32_TIM_TS_SLAVE_4_MASTER_9 3 -#define STM32_TIM_TS_SLAVE_9_MASTER_2 0 -#define STM32_TIM_TS_SLAVE_9_MASTER_3 1 -#define STM32_TIM_TS_SLAVE_9_MASTER_10 2 -#define STM32_TIM_TS_SLAVE_9_MASTER_11 3 -#endif /* !CHIP_FAMILY_STM32F0 */ -#define TSMAP(slave, master) \ - CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master) - -/* - * Timers are defined per board. This gives us flexibility to work around - * timers which are dedicated to board-specific PWM sources. - */ -#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) -#define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) -#define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) - -/* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ -#if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1) -#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_BRK_UP_TRG -#else /* !(TIM_WATCHDOG == 1) */ -#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_CC -#endif /* !(TIM_WATCHDOG == 1) */ - -#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) -#define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG) - -static uint32_t last_deadline; - -void __hw_clock_event_set(uint32_t deadline) -{ - last_deadline = deadline; - - if ((deadline >> 16) > STM32_TIM_CNT(TIM_CLOCK_MSB)) { - /* first set a match on the MSB */ - STM32_TIM_CCR1(TIM_CLOCK_MSB) = deadline >> 16; - /* disable LSB match */ - STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2; - /* Clear the match flags */ - STM32_TIM_SR(TIM_CLOCK_MSB) = ~2; - STM32_TIM_SR(TIM_CLOCK_LSB) = ~2; - /* Set the match interrupt */ - STM32_TIM_DIER(TIM_CLOCK_MSB) |= 2; - } - /* - * In the unlikely case where the MSB has increased and matched - * the deadline MSB before we set the match interrupt, as the STM - * hardware timer won't trigger an interrupt, we fall back to the - * following LSB event code to set another interrupt. - */ - if ((deadline >> 16) == STM32_TIM_CNT(TIM_CLOCK_MSB)) { - /* we can set a match on the LSB only */ - STM32_TIM_CCR1(TIM_CLOCK_LSB) = deadline & 0xffff; - /* disable MSB match */ - STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2; - /* Clear the match flags */ - STM32_TIM_SR(TIM_CLOCK_MSB) = ~2; - STM32_TIM_SR(TIM_CLOCK_LSB) = ~2; - /* Set the match interrupt */ - STM32_TIM_DIER(TIM_CLOCK_LSB) |= 2; - } - /* - * If the LSB deadline is already in the past and won't trigger an - * interrupt, the common code in process_timers will deal with the - * expired timer and automatically set the next deadline, we don't need - * to do anything here. - */ -} - -uint32_t __hw_clock_event_get(void) -{ - return last_deadline; -} - -void __hw_clock_event_clear(void) -{ - /* Disable the match interrupts */ - STM32_TIM_DIER(TIM_CLOCK_LSB) &= ~2; - STM32_TIM_DIER(TIM_CLOCK_MSB) &= ~2; -} - -uint32_t __hw_clock_source_read(void) -{ - uint32_t hi; - uint32_t lo; - - /* Ensure the two half-words are coherent */ - do { - hi = STM32_TIM_CNT(TIM_CLOCK_MSB); - lo = STM32_TIM_CNT(TIM_CLOCK_LSB); - } while (hi != STM32_TIM_CNT(TIM_CLOCK_MSB)); - - return (hi << 16) | lo; -} - -void __hw_clock_source_set(uint32_t ts) -{ - STM32_TIM_CNT(TIM_CLOCK_MSB) = ts >> 16; - STM32_TIM_CNT(TIM_CLOCK_LSB) = ts & 0xffff; -} - -void __hw_clock_source_irq(void) -{ - uint32_t stat_tim_msb = STM32_TIM_SR(TIM_CLOCK_MSB); - - /* Clear status */ - STM32_TIM_SR(TIM_CLOCK_LSB) = 0; - STM32_TIM_SR(TIM_CLOCK_MSB) = 0; - - /* - * Find expired timers and set the new timer deadline - * signal overflow if the 16-bit MSB counter has overflowed. - */ - process_timers(stat_tim_msb & 0x01); -} -DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1); -DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1); - -void __hw_timer_enable_clock(int n, int enable) -{ - volatile uint32_t *reg; - uint32_t mask = 0; - - /* - * Mapping of timers to reg/mask is split into a few different ranges, - * some specific to individual chips. - */ -#if defined(CHIP_FAMILY_STM32F0) - if (n == 1) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM1; - } -#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) - if (n >= 9 && n <= 11) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM9 << (n - 9); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) - if (n >= 15 && n <= 17) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM15 << (n - 15); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - if (n == 14) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM14; - } -#endif - -#if defined(CHIP_FAMILY_STM32F3) - if (n == 12 || n == 13) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM12 << (n - 12); - } - if (n == 18) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM18; - } - if (n == 19) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM19; - } -#endif - - if (n >= 2 && n <= 7) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM2 << (n - 2); - } - - if (!mask) - return; - - if (enable) - *reg |= mask; - else - *reg &= ~mask; -} - -static void update_prescaler(void) -{ - /* - * Pre-scaler value : - * TIM_CLOCK_LSB is counting microseconds; - * TIM_CLOCK_MSB is counting every TIM_CLOCK_LSB overflow. - * - * This will take effect at the next update event (when the current - * prescaler counter ticks down, or if forced via EGR). - */ - STM32_TIM_PSC(TIM_CLOCK_MSB) = 0; - STM32_TIM_PSC(TIM_CLOCK_LSB) = (clock_get_timer_freq() / SECOND) - 1; -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); - -int __hw_clock_source_init(uint32_t start_t) -{ - /* - * we use 2 chained 16-bit counters to emulate a 32-bit one : - * TIM_CLOCK_MSB is the MSB (Slave) - * TIM_CLOCK_LSB is the LSB (Master) - */ - - /* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */ - __hw_timer_enable_clock(TIM_CLOCK_MSB, 1); - __hw_timer_enable_clock(TIM_CLOCK_LSB, 1); - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Upcounter, counter disabled, update event only - * on overflow. - */ - STM32_TIM_CR1(TIM_CLOCK_MSB) = 0x0004; - STM32_TIM_CR1(TIM_CLOCK_LSB) = 0x0004; - /* - * TIM_CLOCK_LSB (master mode) generates a periodic trigger signal on - * each UEV - */ - STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000; - STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020; - - STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 | - (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); - STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000; - - /* Auto-reload value : 16-bit free-running counters */ - STM32_TIM_ARR(TIM_CLOCK_MSB) = 0xffff; - STM32_TIM_ARR(TIM_CLOCK_LSB) = 0xffff; - - /* Update prescaler */ - update_prescaler(); - - /* Reload the pre-scaler */ - STM32_TIM_EGR(TIM_CLOCK_MSB) = 0x0001; - STM32_TIM_EGR(TIM_CLOCK_LSB) = 0x0001; - - /* Set up the overflow interrupt on TIM_CLOCK_MSB */ - STM32_TIM_DIER(TIM_CLOCK_MSB) = 0x0001; - STM32_TIM_DIER(TIM_CLOCK_LSB) = 0x0000; - - /* Start counting */ - STM32_TIM_CR1(TIM_CLOCK_MSB) |= 1; - STM32_TIM_CR1(TIM_CLOCK_LSB) |= 1; - - /* Override the count with the start value now that counting has - * started. */ - __hw_clock_source_set(start_t); - - /* Enable timer interrupts */ - task_enable_irq(IRQ_MSB); - task_enable_irq(IRQ_LSB); - - return IRQ_LSB; -} - -#ifdef CONFIG_WATCHDOG_HELP - -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE; - - /* clear status */ - timer->sr = 0; - - watchdog_trace(excep_lr, excep_sp); -} - -void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked)); -void IRQ_HANDLER(IRQ_WD)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0,pc}\n"); -} -const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ - -void hwtimer_setup_watchdog(void) -{ - struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE; - - /* Enable clock */ - __hw_timer_enable_clock(TIM_WATCHDOG, 1); - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Down counter, counter disabled, update - * event only on overflow. - */ - timer->cr1 = 0x0014 | BIT(7); - - /* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */ - timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4); - - /* - * The auto-reload value is based on the period between rollovers for - * TIM_CLOCK_LSB. Since TIM_CLOCK_LSB runs at 1MHz, it will overflow - * in 65.536ms. We divide our required watchdog period by this amount - * to obtain the number of times TIM_CLOCK_LSB can overflow before we - * generate an interrupt. - */ - timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16); - - /* count on every TIM_CLOCK_LSB overflow */ - timer->psc = 0; - - /* Reload the pre-scaler from arr when it goes below zero */ - timer->egr = 0x0000; - - /* setup the overflow interrupt */ - timer->dier = 0x0001; - - /* Start counting */ - timer->cr1 |= 1; - - /* Enable timer interrupts */ - task_enable_irq(IRQ_WD); -} - -void hwtimer_reset_watchdog(void) -{ - struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE; - - timer->cnt = timer->arr; -} - -#endif /* defined(CONFIG_WATCHDOG_HELP) */ diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c deleted file mode 100644 index 963fa44e51..0000000000 --- a/chip/stm32/hwtimer32.c +++ /dev/null @@ -1,333 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware 32-bit timer driver */ - -#include "clock.h" -#include "clock-f.h" -#include "common.h" -#include "hooks.h" -#include "hwtimer.h" -#include "panic.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "watchdog.h" - -#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) - -void __hw_clock_event_set(uint32_t deadline) -{ - /* set the match on the deadline */ - STM32_TIM32_CCR1(TIM_CLOCK32) = deadline; - /* Clear the match flags */ - STM32_TIM_SR(TIM_CLOCK32) = ~2; - /* Set the match interrupt */ - STM32_TIM_DIER(TIM_CLOCK32) |= 2; -} - -uint32_t __hw_clock_event_get(void) -{ - return STM32_TIM32_CCR1(TIM_CLOCK32); -} - -void __hw_clock_event_clear(void) -{ - /* Disable the match interrupts */ - STM32_TIM_DIER(TIM_CLOCK32) &= ~2; -} - -uint32_t __hw_clock_source_read(void) -{ - return STM32_TIM32_CNT(TIM_CLOCK32); -} - -void __hw_clock_source_set(uint32_t ts) -{ - STM32_TIM32_CNT(TIM_CLOCK32) = ts; -} - -void __hw_clock_source_irq(void) -{ - uint32_t stat_tim = STM32_TIM_SR(TIM_CLOCK32); - - /* Clear status */ - STM32_TIM_SR(TIM_CLOCK32) = 0; - - /* - * Find expired timers and set the new timer deadline - * signal overflow if the update interrupt flag is set. - */ - process_timers(stat_tim & 0x01); -} -DECLARE_IRQ(IRQ_TIM(TIM_CLOCK32), __hw_clock_source_irq, 1); - -void __hw_timer_enable_clock(int n, int enable) -{ - volatile uint32_t *reg; - uint32_t mask = 0; - - /* - * Mapping of timers to reg/mask is split into a few different ranges, - * some specific to individual chips. - */ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7) - if (n == 1) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM1; - } -#elif defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) - if (n >= 9 && n <= 11) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM9 << (n - 9); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32H7) - if (n >= 15 && n <= 17) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM15 << (n - 15); - } -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ -defined(CHIP_FAMILY_STM32H7) - if (n == 14) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM14; - } -#endif - -#if defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32H7) - if (n == 12 || n == 13) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM12 << (n - 12); - } -#endif -#if defined(CHIP_FAMILY_STM32F3) - if (n == 18) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM18; - } - if (n == 19) { - reg = &STM32_RCC_APB2ENR; - mask = STM32_RCC_PB2_TIM19; - } -#endif -#if defined(CHIP_FAMILY_STM32G4) - reg = &STM32_RCC_APB2ENR; - if (n == 1) - mask = STM32_RCC_APB2ENR_TIM1; - else if (n == 8) - mask = STM32_RCC_APB2ENR_TIM8; - else if (n == 20) - mask = STM32_RCC_APB2ENR_TIM20; - else if (n >= 15 && n <= 17) - mask = STM32_RCC_APB2ENR_TIM15 << (n - 15); -#endif -#if defined(CHIP_FAMILY_STM32L4) - if (n >= 2 && n <= 7) { - reg = &STM32_RCC_APB1ENR1; - mask = STM32_RCC_PB1_TIM2 << (n - 2); - } else if (n == 1 || n == 15 || n == 16) { - reg = &STM32_RCC_APB2ENR; - mask = (n == 1) ? STM32_RCC_APB2ENR_TIM1EN : - (n == 15) ? STM32_RCC_APB2ENR_TIM15EN : - STM32_RCC_APB2ENR_TIM16EN; - } -#else - if (n >= 2 && n <= 7) { - reg = &STM32_RCC_APB1ENR; - mask = STM32_RCC_PB1_TIM2 << (n - 2); - } -#endif - - if (!mask) - return; - - if (enable) - *reg |= mask; - else - *reg &= ~mask; -} - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7) -/* for families using a variable clock feeding the timer */ -static void update_prescaler(void) -{ - uint32_t t; - /* - * Pre-scaler value : - * the timer is incrementing every microsecond - */ - STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1; - /* - * Forcing reloading the pre-scaler, - * but try to maintain a sensible time-keeping while triggering - * the update event. - */ - interrupt_disable(); - /* Ignore the next update */ - STM32_TIM_DIER(TIM_CLOCK32) &= ~0x0001; - /* - * prepare to reload the counter with the current value - * to avoid rolling backward the microsecond counter. - */ - t = STM32_TIM32_CNT(TIM_CLOCK32) + 1; - /* issue an update event, reloads the pre-scaler and the counter */ - STM32_TIM_EGR(TIM_CLOCK32) = 0x0001; - /* clear the 'spurious' update unless we were going to roll-over */ - if (t) - STM32_TIM_SR(TIM_CLOCK32) = ~1; - /* restore a sensible time value */ - STM32_TIM32_CNT(TIM_CLOCK32) = t; - /* restore roll-over events */ - STM32_TIM_DIER(TIM_CLOCK32) |= 0x0001; - interrupt_enable(); - -#ifdef CONFIG_WATCHDOG_HELP - /* Watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC)- 1; -#endif /* CONFIG_WATCHDOG_HELP */ -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); -#endif /* CHIP_FAMILY_STM32L || CHIP_FAMILY_STM32L4 || */ - /* CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */ - -int __hw_clock_source_init(uint32_t start_t) -{ - /* Enable TIM peripheral block clocks */ - __hw_timer_enable_clock(TIM_CLOCK32, 1); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Upcounter, counter disabled, update event only - * on overflow. - */ - STM32_TIM_CR1(TIM_CLOCK32) = 0x0004; - /* No special configuration */ - STM32_TIM_CR2(TIM_CLOCK32) = 0x0000; - STM32_TIM_SMCR(TIM_CLOCK32) = 0x0000; - - /* Auto-reload value : 32-bit free-running counter */ - STM32_TIM32_ARR(TIM_CLOCK32) = 0xffffffff; - - /* Update prescaler to increment every microsecond */ - STM32_TIM_PSC(TIM_CLOCK32) = (clock_get_timer_freq() / SECOND) - 1; - - /* Reload the pre-scaler */ - STM32_TIM_EGR(TIM_CLOCK32) = 0x0001; - - /* Set up the overflow interrupt */ - STM32_TIM_DIER(TIM_CLOCK32) = 0x0001; - - /* Start counting */ - STM32_TIM_CR1(TIM_CLOCK32) |= 1; - - /* Override the count with the start value now that counting has - * started. */ - __hw_clock_source_set(start_t); - - /* Enable timer interrupts */ - task_enable_irq(IRQ_TIM(TIM_CLOCK32)); - - return IRQ_TIM(TIM_CLOCK32); -} - -#ifdef CONFIG_WATCHDOG_HELP - -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) - -void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) -{ - /* clear status */ - STM32_TIM_SR(TIM_WATCHDOG) = 0; - - watchdog_trace(excep_lr, excep_sp); -} - -void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked)); -void IRQ_HANDLER(IRQ_WD)(void) -{ - /* Naked call so we can extract raw LR and SP */ - asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0,pc}\n"); -} -const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ - -void hwtimer_setup_watchdog(void) -{ - int freq; - - /* Enable clock */ - __hw_timer_enable_clock(TIM_WATCHDOG, 1); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Timer configuration : Up counter, counter disabled, update - * event only on overflow. - */ - STM32_TIM_CR1(TIM_WATCHDOG) = 0x0004; - /* No special configuration */ - STM32_TIM_CR2(TIM_WATCHDOG) = 0x0000; - STM32_TIM_SMCR(TIM_WATCHDOG) = 0x0000; - - /* - * all timers has 16-bit prescale. - * For clock freq > 64MHz, 16bit prescale cannot meet 1KHz. - * set prescale as 10KHz and 10 times arr value instead. - * For clock freq < 64MHz, timer runs at 1KHz. - */ - freq = clock_get_timer_freq(); - - if (freq <= 64000000 || !IS_ENABLED(CHIP_FAMILY_STM32L4)) { - /* AUto-reload value */ - STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; - - /* Update prescaler: watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (freq / SECOND * MSEC) - 1; - } -#ifdef CHIP_FAMILY_STM32L4 - else { - /* 10 times ARR value with 10KHz timer */ - STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS * 10; - - /* Update prescaler: watchdog timer runs at 10KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND / 10 * MSEC) - 1; - } -#endif - /* Reload the pre-scaler */ - STM32_TIM_EGR(TIM_WATCHDOG) = 0x0001; - - /* setup the overflow interrupt */ - STM32_TIM_DIER(TIM_WATCHDOG) = 0x0001; - STM32_TIM_SR(TIM_WATCHDOG) = 0; - - /* Start counting */ - STM32_TIM_CR1(TIM_WATCHDOG) |= 1; - - /* Enable timer interrupts */ - task_enable_irq(IRQ_WD); -} - -void hwtimer_reset_watchdog(void) -{ - STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000; -} - -#endif /* CONFIG_WATCHDOG_HELP */ diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c deleted file mode 100644 index cdf5421efc..0000000000 --- a/chip/stm32/i2c-stm32f0.c +++ /dev/null @@ -1,653 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "hwtimer.h" -#include "i2c.h" -#include "i2c_private.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "usb_pd_tcpc.h" -#include "usb_pd_tcpm.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -#if (I2C_PORT_EC == STM32_I2C1_PORT) -#define IRQ_PERIPHERAL STM32_IRQ_I2C1 -#else -#define IRQ_PERIPHERAL STM32_IRQ_I2C2 -#endif -#endif - - -/* I2C port state data */ -struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER; -} - -/* timingr register values for supported input clks / i2c clk rates */ -static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { - [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ -}; - -/** - * Wait for ISR register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_isr(int port, int mask) -{ - uint32_t start = __hw_clock_source_read(); - uint32_t delta = 0; - - do { - int isr = STM32_I2C_ISR(port); - - /* Check for errors */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) - return EC_ERROR_UNKNOWN; - - /* Check for desired mask */ - if ((isr & mask) == mask) - return EC_SUCCESS; - - delta = __hw_clock_source_read() - start; - - /** - * Depending on the bus speed, busy loop for a while before - * sleeping and letting other things run. - */ - if (delta >= busyloop_us[pdata[port].freq]) - usleep(100); - } while (delta < pdata[port].timeout_us); - - return EC_ERROR_TIMEOUT; -} - -/* Supported i2c input clocks */ -enum stm32_i2c_clk_src { - I2C_CLK_SRC_48MHZ = 0, - I2C_CLK_SRC_8MHZ = 1, - I2C_CLK_SRC_COUNT, -}; - -/* timingr register values for supported input clks / i2c clk rates */ -static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { - [I2C_CLK_SRC_48MHZ] = { - [I2C_FREQ_1000KHZ] = 0x50100103, - [I2C_FREQ_400KHZ] = 0x50330609, - [I2C_FREQ_100KHZ] = 0xB0421214, - }, - [I2C_CLK_SRC_8MHZ] = { - [I2C_FREQ_1000KHZ] = 0x00100306, - [I2C_FREQ_400KHZ] = 0x00310309, - [I2C_FREQ_100KHZ] = 0x10420f13, - }, -}; - -int chip_i2c_set_freq(int port, enum i2c_freq freq) -{ - enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ; - -#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ - defined(CONFIG_LOW_POWER_IDLE) && \ - (I2C_PORT_EC == STM32_I2C1_PORT) - if (port == STM32_I2C1_PORT) { - /* - * Use HSI (8MHz) for i2c clock. This allows smooth wakeup - * from STOP mode since HSI is only clock running immediately - * upon exit from STOP mode. - */ - src = I2C_CLK_SRC_8MHZ; - } -#endif - - /* Disable port */ - STM32_I2C_CR1(port) = 0; - STM32_I2C_CR2(port) = 0; - /* Set clock frequency */ - STM32_I2C_TIMINGR(port) = timingr_regs[src][freq]; - /* Enable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; - - pdata[port].freq = freq; - - return EC_SUCCESS; -} - -enum i2c_freq chip_i2c_get_freq(int port) -{ - return pdata[port].freq; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static int i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - int ret = EC_SUCCESS; - enum i2c_freq freq; - - /* Enable clocks to I2C modules if necessary */ - if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) - STM32_RCC_APB1ENR |= 1 << (21 + port); - - if (port == STM32_I2C1_PORT) { -#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ - defined(CONFIG_LOW_POWER_IDLE) && \ - (I2C_PORT_EC == STM32_I2C1_PORT) - /* - * Use HSI (8MHz) for i2c clock. This allows smooth wakeup - * from STOP mode since HSI is only clock running immediately - * upon exit from STOP mode. - */ - STM32_RCC_CFGR3 &= ~0x10; -#else - /* Use SYSCLK for i2c clock. */ - STM32_RCC_CFGR3 |= 0x10; -#endif - } - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Set clock frequency */ - switch (p->kbps) { - case 1000: - freq = I2C_FREQ_1000KHZ; - break; - case 400: - freq = I2C_FREQ_400KHZ; - break; - case 100: - freq = I2C_FREQ_100KHZ; - break; - default: /* unknown speed, defaults to 100kBps */ - CPRINTS("I2C bad speed %d kBps", p->kbps); - freq = I2C_FREQ_100KHZ; - ret = EC_ERROR_INVAL; - } - - /* Set up initial bus frequencies */ - chip_i2c_set_freq(p->port, freq); - - /* Set up default timeout */ - i2c_set_timeout(port, 0); - - return ret; -} - -/*****************************************************************************/ -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -/* Host command peripheral */ -/* - * Buffer for received host command packets (including prefix byte on request, - * and result/size on response). After any protocol-specific headers, the - * buffers must be 32-bit aligned. - */ -static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + - CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; -static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); -static int host_i2c_resp_port; -static int tx_pending; -static int tx_index, tx_end; -static struct host_packet i2c_packet; - -static void i2c_send_response_packet(struct host_packet *pkt) -{ - int size = pkt->response_size; - uint8_t *out = host_buffer; - - /* Ignore host command in-progress */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result and size to first two bytes. */ - *out++ = pkt->driver_result; - *out++ = size; - - /* host_buffer data range */ - tx_index = 0; - tx_end = size + 2; - - /* - * Set the transmitter to be in 'not full' state to keep sending - * '0xec' in the event loop. Because of this, the controller i2c - * doesn't need to snoop the response stream to abort transaction. - */ - STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; -} - -/* Process the command in the i2c host buffer */ -static void i2c_process_command(void) -{ - char *buff = host_buffer; - - /* - * TODO(crosbug.com/p/29241): Combine this functionality with the - * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one - * host command i2c process function which handles all protocol - * versions. - */ - i2c_packet.send_response = i2c_send_response_packet; - - i2c_packet.request = (const void *)(&buff[1]); - i2c_packet.request_temp = params_copy; - i2c_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; - - /* - * Stuff response at buff[2] to leave the first two bytes of - * buffer available for the result and size to send over i2c. Note - * that this 2-byte offset and the 2-byte offset from host_buffer - * add up to make the response buffer 32-bit aligned. - */ - i2c_packet.response = (void *)(&buff[2]); - i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; - i2c_packet.response_size = 0; - - if (*buff >= EC_COMMAND_PROTOCOL_3) { - i2c_packet.driver_result = EC_RES_SUCCESS; - } else { - /* Only host command protocol 3 is supported. */ - i2c_packet.driver_result = EC_RES_INVALID_HEADER; - } - host_packet_receive(&i2c_packet); -} - -#ifdef TCPCI_I2C_PERIPHERAL -static void i2c_send_tcpc_response(int len) -{ - /* host_buffer data range, beyond this length, will return 0xec */ - tx_index = 0; - tx_end = len; - - /* enable transmit interrupt and use irq to send data back */ - STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; -} - -static void i2c_process_tcpc_command(int read, int addr, int len) -{ - tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0], - i2c_send_tcpc_response); -} -#endif - -static void i2c_event_handler(int port) -{ - int i2c_isr; - static int rx_pending, buf_idx; -#ifdef TCPCI_I2C_PERIPHERAL - int addr; -#endif - - i2c_isr = STM32_I2C_ISR(port); - - /* - * Check for error conditions. Note, arbitration loss and bus error - * are the only two errors we can get as a peripheral allowing clock - * stretching and in non-SMBus mode. - */ - if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) { - rx_pending = 0; - tx_pending = 0; - - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear error status bits */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | - STM32_I2C_ICR_ARLOCF; - } - - /* Transfer matched our peripheral address */ - if (i2c_isr & STM32_I2C_ISR_ADDR) { - if (i2c_isr & STM32_I2C_ISR_DIR) { - /* Transmitter peripheral */ - /* Clear transmit buffer */ - STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE; - - /* Enable txis interrupt to start response */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE; - } else { - /* Receiver peripheral */ - buf_idx = 0; - rx_pending = 1; - } - - /* Clear ADDR bit by writing to ADDRCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF; - /* Inhibit sleep mode when addressed until STOPF flag is set */ - disable_sleep(SLEEP_MASK_I2C_PERIPHERAL); - } - - /* Receiver full event */ - if (i2c_isr & STM32_I2C_ISR_RXNE) - host_buffer[buf_idx++] = STM32_I2C_RXDR(port); - - /* Stop condition on bus */ - if (i2c_isr & STM32_I2C_ISR_STOP) { -#ifdef TCPCI_I2C_PERIPHERAL - /* - * if tcpc is being addressed, and we received a stop - * while rx is pending, then this is a write only to - * the tcpc. - */ - addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port)); - if (rx_pending && ADDR_IS_TCPC(addr)) - i2c_process_tcpc_command(0, addr, buf_idx); -#endif - rx_pending = 0; - tx_pending = 0; - - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear STOPF bit by writing to STOPCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF; - - /* No longer inhibit deep sleep after stop condition */ - enable_sleep(SLEEP_MASK_I2C_PERIPHERAL); - } - - /* Controller requested STOP or RESTART */ - if (i2c_isr & STM32_I2C_ISR_NACK) { - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - /* Clear NACK */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF; - /* Resend last byte on RESTART */ - if (port == I2C_PORT_EC && tx_index) - tx_index--; - } - - /* Transmitter empty event */ - if (i2c_isr & STM32_I2C_ISR_TXIS) { - if (port == I2C_PORT_EC) { /* host is waiting for PD response */ - if (tx_pending) { - if (tx_index < tx_end) { - STM32_I2C_TXDR(port) = - host_buffer[tx_index++]; - } else { - STM32_I2C_TXDR(port) = 0xec; - /* - * Set tx_index = 0 to prevent NACK - * handler resending last buffer byte. - */ - tx_index = 0; - tx_end = 0; - /* No pending data */ - tx_pending = 0; - } - } else if (rx_pending) { - host_i2c_resp_port = port; - /* - * Disable TXIS interrupt, transmission will - * be prepared by host command task. - */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - -#ifdef TCPCI_I2C_PERIPHERAL - addr = STM32_I2C_ISR_ADDCODE( - STM32_I2C_ISR(port)); - if (ADDR_IS_TCPC(addr)) - i2c_process_tcpc_command(1, addr, - buf_idx); - else -#endif - i2c_process_command(); - - /* Reset host buffer after end of transfer */ - rx_pending = 0; - tx_pending = 1; - } else { - STM32_I2C_TXDR(port) = 0xec; - } - } - } -} -void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } -DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2); -#endif - -/*****************************************************************************/ -/* Interface */ - -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; - int rv = EC_SUCCESS; - int i; - int xfer_start = flags & I2C_XFER_START; - int xfer_stop = flags & I2C_XFER_STOP; - -#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT) - if (port == CONFIG_I2C_SCL_GATE_PORT && - addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) - gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1); -#endif - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - /* Clear status */ - if (xfer_start) { - uint32_t cr2 = STM32_I2C_CR2(port); - - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - STM32_I2C_CR2(port) = 0; - if (cr2 & STM32_I2C_CR2_RELOAD) { - /* - * If I2C_XFER_START flag is on and we've set RELOAD=1 - * in previous chip_i2c_xfer() call. Then we are - * probably in the middle of an i2c transaction. - * - * In this case, we need to clear the RELOAD bit and - * wait for Transfer Complete (TC) flag, to make sure - * the chip is not expecting another NBYTES data, And - * send repeated-start correctly. - */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - } - - if (out_bytes || !in_bytes) { - /* - * Configure the write transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we are starting, then set START bit. - */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < out_bytes; i++) { - rv = wait_isr(port, STM32_I2C_ISR_TXIS); - if (rv) - goto xfer_exit; - /* Write next data byte */ - STM32_I2C_TXDR(port) = out[i]; - } - } - if (in_bytes) { - if (out_bytes) { /* wait for completion of the write */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - /* - * Configure the read transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we were just transmitting, we need to - * set START bit to send (re)start and begin read transaction. - */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < in_bytes; i++) { - /* Wait for receive buffer not empty */ - rv = wait_isr(port, STM32_I2C_ISR_RXNE); - if (rv) - goto xfer_exit; - - in[i] = STM32_I2C_RXDR(port); - } - } - - /* - * If we are stopping, then we already set AUTOEND and we should - * wait for the stop bit to be transmitted. Otherwise, we set - * the RELOAD bit and we should wait for transfer complete - * reload (TCR). - */ - rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); - if (rv) - goto xfer_exit; - -xfer_exit: - /* clear status */ - if (xfer_stop) - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - - /* On error, queue a stop condition */ - if (rv) { - /* queue a STOP condition */ - STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; - /* wait for it to take effect */ - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows peripherals on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - /* re-initialize the controller */ - STM32_I2C_CR2(port) = 0; - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; - udelay(10); - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; - } - -#ifdef CONFIG_I2C_SCL_GATE_ADDR - if (port == CONFIG_I2C_SCL_GATE_PORT && - addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) - gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0); -#endif - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; -#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) - /* - * If using low power idle and EC port is I2C1, then set I2C1 to wake - * from STOP mode on address match. Note, this only works on I2C1 and - * only if the clock to I2C1 is HSI 8MHz. - */ - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN; -#endif - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); -#ifdef TCPCI_I2C_PERIPHERAL - /* - * Configure TCPC address with OA2[1] masked so that we respond - * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2. - */ - STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100 - | (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); -#endif - task_enable_irq(IRQ_PERIPHERAL); -#endif -} - diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c deleted file mode 120000 index ce8523ea90..0000000000 --- a/chip/stm32/i2c-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -i2c-stm32f0.c
\ No newline at end of file diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c deleted file mode 100644 index c1f19704b5..0000000000 --- a/chip/stm32/i2c-stm32f4.c +++ /dev/null @@ -1,1010 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "hooks.h" -#include "i2c.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -#if (I2C_PORT_EC == STM32_I2C1_PORT) -#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C1_EV -#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C1_ER -#else -#define IRQ_PERIPHERAL_EV STM32_IRQ_I2C2_EV -#define IRQ_PERIPHERAL_ER STM32_IRQ_I2C2_ER -#endif -#endif - -/* Define I2C blocks available in stm32f4: - * We have standard ST I2C blocks and a "fast mode plus" I2C block, - * which do not share the same registers or functionality. So we'll need - * two sets of functions to handle this for stm32f4. In stm32f446, we - * only have one FMP block so we'll hardcode its port number. - */ -#define STM32F4_FMPI2C_PORT 3 - -static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)}, - {STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)}, - {STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)}, -}; - -static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)}, - {STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)}, - {STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)}, -}; - -/* Callback for ISR to wake task on DMA complete. */ -static inline void _i2c_dma_wake_callback(void *cb_data, int port) -{ - task_id_t id = (task_id_t)(int)cb_data; - - if (id != TASK_ID_INVALID) - task_set_event(id, TASK_EVENT_I2C_COMPLETION(port)); -} - -/* Each callback is hardcoded to an I2C channel. */ -static void _i2c_dma_wake_callback_0(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 0); -} - -static void _i2c_dma_wake_callback_1(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 1); -} - -static void _i2c_dma_wake_callback_2(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 2); -} - -static void _i2c_dma_wake_callback_3(void *cb_data) -{ - _i2c_dma_wake_callback(cb_data, 3); -} - -/* void (*callback)(void *) */ -static void (*i2c_callbacks[I2C_PORT_COUNT])(void *) = { - _i2c_dma_wake_callback_0, - _i2c_dma_wake_callback_1, - _i2c_dma_wake_callback_2, - _i2c_dma_wake_callback_3, -}; - -/* Enable the I2C interrupt callback for this port. */ -void i2c_dma_enable_tc_interrupt(enum dma_channel stream, int port) -{ - dma_enable_tc_interrupt_callback(stream, i2c_callbacks[port], - (void *)(int)task_get_current()); -} - -/** - * Wait for SR1 register to contain the specified mask of 0 or 1. - * - * @param port I2C port - * @param mask mask of bits of interest - * @param val desired value of bits of interest - * @param poll uS poll frequency - * - * @return EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -#define SET 0xffffffff -#define UNSET 0 -static int wait_sr1_poll(int port, int mask, int val, int poll) -{ - uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER; - - while (get_time().val < timeout) { - int sr1 = STM32_I2C_SR1(port); - - /* Check for errors */ - if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR | - STM32_I2C_SR1_AF)) { - return EC_ERROR_UNKNOWN; - } - - /* Check for desired mask */ - if ((sr1 & mask) == (val & mask)) - return EC_SUCCESS; - - /* I2C is slow, so let other things run while we wait */ - usleep(poll); - } - - CPRINTS("I2C timeout: p:%d m:%x", port, mask); - return EC_ERROR_TIMEOUT; -} - -/* Wait for SR1 register to contain the specified mask of ones */ -static int wait_sr1(int port, int mask) -{ - return wait_sr1_poll(port, mask, SET, 100); -} - - -/** - * Send a start condition and peripheral address on the specified port. - * - * @param port I2C port - * @param addr_8bit I2C address, with LSB set for receive-mode - * - * @return Non-zero if error. - */ -static int send_start(const int port, const uint16_t addr_8bit) -{ - int rv; - - /* Send start bit */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_START; - rv = wait_sr1_poll(port, STM32_I2C_SR1_SB, SET, 1); - if (rv) - return I2C_ERROR_FAILED_START; - - /* Write peripheral address */ - STM32_I2C_DR(port) = addr_8bit; - rv = wait_sr1_poll(port, STM32_I2C_SR1_ADDR, SET, 1); - if (rv) - return rv; - - /* Read SR2 to clear ADDR bit */ - rv = STM32_I2C_SR2(port); - - return EC_SUCCESS; -} - -/** - * Find the i2c port structure associated with the port. - * - * @return i2c_port_t * associated with this port number. - */ -static const struct i2c_port_t *find_port(int port) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) { - if (p->port == port) - return p; - } - CPRINTS("I2C port %d invalid! Crashing now.", port); - return NULL; -} - -/** - * Wait for ISR register to contain the specified mask. - * - * @param port I2C port - * @param mask mask of bits of interest - * @param val desired value of bits of interest - * @param poll uS poll frequency - * - * @return EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll) -{ - uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_CONTROLLER; - - while (get_time().val < timeout) { - int isr = STM32_FMPI2C_ISR(port); - - /* Check for errors */ - if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | - FMPI2C_ISR_NACKF)) { - return EC_ERROR_UNKNOWN; - } - - /* Check for desired mask */ - if ((isr & mask) == (val & mask)) - return EC_SUCCESS; - - /* I2C is slow, so let other things run while we wait */ - usleep(poll); - } - - CPRINTS("FMPI2C timeout p:%d, m:0x%08x", port, mask); - return EC_ERROR_TIMEOUT; -} - -/* Wait for ISR register to contain the specified mask of ones */ -static int wait_fmpi2c_isr(int port, int mask) -{ - return wait_fmpi2c_isr_poll(port, mask, SET, 100); -} - -/** - * Send a start condition and peripheral address on the specified port. - * - * @param port I2C port - * @param addr_8bit I2C address - * @param size bytes to transfer - * @param is_read read, or write? - * - * @return Non-zero if error. - */ -static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, - int size, int is_read) -{ - uint32_t reg; - - /* Send start bit */ - reg = STM32_FMPI2C_CR2(port); - reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK | - FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP); - reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | - addr_8bit | FMPI2C_CR2_SIZE(size) | - (is_read ? FMPI2C_CR2_RD_WRN : 0); - STM32_FMPI2C_CR2(port) = reg; - - return EC_SUCCESS; -} - -/** - * Set i2c clock rate.. - * - * @param p I2C port struct - */ -static void i2c_set_freq_port(const struct i2c_port_t *p) -{ - int port = p->port; - int freq = clock_get_freq(); - - if (p->port == STM32F4_FMPI2C_PORT) { - int prescalar; - int actual; - uint32_t reg; - - /* FMP I2C clock set. */ - STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE; - prescalar = (freq / (p->kbps * 1000 * - (0x12 + 1 + 0xe + 1 + 1))) - 1; - actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1)); - - reg = FMPI2C_TIMINGR_SCLL(0x12) | - FMPI2C_TIMINGR_SCLH(0xe) | - FMPI2C_TIMINGR_PRESC(prescalar); - STM32_FMPI2C_TIMINGR(port) = reg; - - CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", - port, p->kbps, prescalar, actual, reg); - - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; - udelay(10); - } else { - /* Force peripheral reset and disable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST; - STM32_I2C_CR1(port) = 0; - - /* Set clock frequency */ - if (p->kbps > 100) { - STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); - } else { - STM32_I2C_CCR(port) = STM32_I2C_CCR_FM - | STM32_I2C_CCR_DUTY - | (freq / (16 + 9 * MSEC * p->kbps)); - } - STM32_I2C_CR2(port) = freq / SECOND; - STM32_I2C_TRISE(port) = freq / SECOND + 1; - - /* Enable port */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; - } -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - - /* Configure GPIOs, clocks */ - gpio_config_module(MODULE_I2C, 1); - clock_enable_module(MODULE_I2C, 1); - - if (p->port == STM32F4_FMPI2C_PORT) { - /* FMP I2C block */ - /* Set timing (?) */ - STM32_FMPI2C_TIMINGR(port) = TIMINGR_THE_RIGHT_VALUE; - udelay(10); - /* Device enable */ - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; - /* Need to wait 3 APB cycles */ - udelay(10); - /* Device only. */ - STM32_FMPI2C_OAR1(port) = 0; - STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_AUTOEND; - } else { - STM32_I2C_CR1(port) |= STM32_I2C_CR1_SWRST; - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_SWRST; - udelay(10); - } - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p); -} - -/*****************************************************************************/ -/* Interface */ - -/** - * Clear status regs on the specified I2C port. - * - * @param port the I2c port - */ -static void fmpi2c_clear_regs(int port) -{ - /* Clear status */ - STM32_FMPI2C_ICR(port) = 0xffffffff; - - /* Clear start, stop, NACK, etc. bits to get us in a known state */ - STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK | - FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK); -} - -/** - * Perform an i2c transaction - * - * @param port i2c port to use - * @param addr_8bit the i2c address - * @param out source buffer for data - * @param out_bytes bytes of data to write - * @param in destination buffer for data - * @param in_bytes bytes of data to read - * @param flags user cached I2C state - * - * @return EC_SUCCESS on success. - */ -static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int started = (flags & I2C_XFER_START) ? 0 : 1; - int rv = EC_SUCCESS; - int i; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - ASSERT(!started); - - if (STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY) { - CPRINTS("fmpi2c port %d busy", port); - return EC_ERROR_BUSY; - } - - fmpi2c_clear_regs(port); - - /* No out bytes and no in bytes means just check for active */ - if (out_bytes || !in_bytes) { - rv = send_fmpi2c_start( - port, addr_8bit, out_bytes, FMPI2C_WRITE); - if (rv) - goto xfer_exit; - - /* Write data, if any */ - for (i = 0; i < out_bytes; i++) { - rv = wait_fmpi2c_isr(port, FMPI2C_ISR_TXIS); - if (rv) - goto xfer_exit; - - /* Write next data byte */ - STM32_FMPI2C_TXDR(port) = out[i]; - } - - /* Wait for transaction STOP. */ - wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF); - } - - if (in_bytes) { - int rv_start; - const struct dma_option *dma = dma_rx_option + port; - - dma_start_rx(dma, in_bytes, in); - i2c_dma_enable_tc_interrupt(dma->channel, port); - - rv_start = send_fmpi2c_start( - port, addr_8bit, in_bytes, FMPI2C_READ); - if (rv_start) - goto xfer_exit; - - rv = wait_fmpi2c_isr(port, FMPI2C_ISR_RXNE); - if (rv) - goto xfer_exit; - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN; - - rv = task_wait_event_mask( - TASK_EVENT_I2C_COMPLETION(port), - DMA_TRANSFER_TIMEOUT_US); - if (rv & TASK_EVENT_I2C_COMPLETION(port)) - rv = EC_SUCCESS; - else - rv = EC_ERROR_TIMEOUT; - - dma_disable(dma->channel); - dma_disable_tc_interrupt(dma->channel); - - /* Validate i2c is STOPped */ - if (!rv) - rv = wait_fmpi2c_isr(port, FMPI2C_ISR_STOPF); - - STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN; - } - - xfer_exit: - /* On error, queue a stop condition */ - if (rv) { - flags |= I2C_XFER_STOP; - STM32_FMPI2C_CR2(port) |= FMPI2C_CR2_STOP; - - /* - * If failed at sending start, try resetting the port - * to unwedge the bus. - */ - if (rv == I2C_ERROR_FAILED_START) { - const struct i2c_port_t *p; - - CPRINTS("chip_fmpi2c_xfer start error; " - "unwedging and resetting i2c %d", port); - - p = find_port(port); - i2c_unwedge(port); - i2c_init_port(p); - } - } - - /* If a stop condition is queued, wait for it to take effect */ - if (flags & I2C_XFER_STOP) { - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_FMPI2C_ISR(port) & FMPI2C_ISR_BUSY)) - break; - usleep(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows peripherals on the bus to detect bus-idle before - * the next start condition. - */ - STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE; - usleep(10); - STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; - } - - return rv; -} - - -/** - * Clear status regs on the specified I2C port. - * - * @param port the I2c port - */ -static void i2c_clear_regs(int port) -{ - /* - * Clear status - * - * TODO(crosbug.com/p/29314): should check for any leftover error - * status, and reset the port if present. - */ - STM32_I2C_SR1(port) = 0; - - /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); -} - -/***************************************************************************** - * Exported functions declared in i2c.h - */ - -/* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; - int started = (flags & I2C_XFER_START) ? 0 : 1; - int rv = EC_SUCCESS; - int i; - const struct i2c_port_t *p = find_port(port); - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - ASSERT(!started); - - if (p->port == STM32F4_FMPI2C_PORT) { - return chip_fmpi2c_xfer(port, addr_8bit, - out, out_bytes, - in, in_bytes, flags); - } - - i2c_clear_regs(port); - - /* No out bytes and no in bytes means just check for active */ - if (out_bytes || !in_bytes) { - rv = send_start(port, addr_8bit); - if (rv) - goto xfer_exit; - - /* Write data, if any */ - for (i = 0; i < out_bytes; i++) { - /* Write next data byte */ - STM32_I2C_DR(port) = out[i]; - - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - } - - /* If no input bytes, queue stop condition */ - if (!in_bytes && (flags & I2C_XFER_STOP)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - } - - if (in_bytes) { - int rv_start; - - const struct dma_option *dma = dma_rx_option + port; - - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_POS; - dma_start_rx(dma, in_bytes, in); - i2c_dma_enable_tc_interrupt(dma->channel, port); - - /* Setup ACK/POS before sending start as per user manual */ - if (in_bytes == 2) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS; - else if (in_bytes != 1) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK; - - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_STOP; - - STM32_I2C_CR2(port) |= STM32_I2C_CR2_LAST; - STM32_I2C_CR2(port) |= STM32_I2C_CR2_DMAEN; - - rv_start = send_start(port, addr_8bit | 0x01); - - if ((in_bytes == 1) && (flags & I2C_XFER_STOP)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - if (!rv_start) { - rv = task_wait_event_mask( - TASK_EVENT_I2C_COMPLETION(port), - DMA_TRANSFER_TIMEOUT_US); - if (rv & TASK_EVENT_I2C_COMPLETION(port)) - rv = EC_SUCCESS; - else - rv = EC_ERROR_TIMEOUT; - } - - dma_disable(dma->channel); - dma_disable_tc_interrupt(dma->channel); - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN; - /* Disable ack */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK; - - if (rv_start) - rv = rv_start; - - /* Send stop. */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK; - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_LAST; - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN; - } - - xfer_exit: - /* On error, queue a stop condition */ - if (rv) { - flags |= I2C_XFER_STOP; - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - /* - * If failed at sending start, try resetting the port - * to unwedge the bus. - */ - if (rv == I2C_ERROR_FAILED_START) { - const struct i2c_port_t *p; - - CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); - - p = find_port(port); - i2c_unwedge(port); - i2c_init_port(p); - } - } - - /* If a stop condition is queued, wait for it to take effect */ - if (flags & I2C_XFER_STOP) { - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY)) - break; - usleep(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows peripherals on the bus to detect bus-idle before - * the next start condition. - */ - usleep(10); - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SDA pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -/*****************************************************************************/ -/* Hooks */ - -#ifdef CONFIG_I2C_CONTROLLER -/* Handle CPU clock changing frequency */ -static void i2c_freq_change(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_set_freq_port(p); -} - -/* Handle an upcoming frequency change. */ -static void i2c_pre_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* Lock I2C ports so freq change can't interrupt an I2C transaction */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 1); -} -DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT); - -/* Handle a frequency change */ -static void i2c_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - i2c_freq_change(); - - /* Unlock I2C ports we locked in pre-freq change hook */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 0); -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); -#endif - -/*****************************************************************************/ -/* Peripheral */ -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -/* Host command peripheral */ -/* - * Buffer for received host command packets (including prefix byte on request, - * and result/size on response). After any protocol-specific headers, the - * buffers must be 32-bit aligned. - */ -static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + - CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; -static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); -static int host_i2c_resp_port; -static int tx_pending; -static int tx_index, tx_end; -static struct host_packet i2c_packet; - -static void i2c_send_response_packet(struct host_packet *pkt) -{ - int size = pkt->response_size; - uint8_t *out = host_buffer; - - /* Ignore host command in-progress */ - if (pkt->driver_result == EC_RES_IN_PROGRESS) - return; - - /* Write result and size to first two bytes. */ - *out++ = pkt->driver_result; - *out++ = size; - - /* host_buffer data range */ - tx_index = 0; - tx_end = size + 2; - - /* - * Set the transmitter to be in 'not full' state to keep sending - * '0xec' in the event loop. Because of this, the controller i2c - * doesn't need to snoop the response stream to abort transaction. - */ - STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN; -} - -/* Process the command in the i2c host buffer */ -static void i2c_process_command(void) -{ - char *buff = host_buffer; - - /* - * TODO(crosbug.com/p/29241): Combine this functionality with the - * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one - * host command i2c process function which handles all protocol - * versions. - */ - i2c_packet.send_response = i2c_send_response_packet; - - i2c_packet.request = (const void *)(&buff[1]); - i2c_packet.request_temp = params_copy; - i2c_packet.request_max = sizeof(params_copy); - /* Don't know the request size so pass in the entire buffer */ - i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; - - /* - * Stuff response at buff[2] to leave the first two bytes of - * buffer available for the result and size to send over i2c. Note - * that this 2-byte offset and the 2-byte offset from host_buffer - * add up to make the response buffer 32-bit aligned. - */ - i2c_packet.response = (void *)(&buff[2]); - i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; - i2c_packet.response_size = 0; - - if (*buff >= EC_COMMAND_PROTOCOL_3) { - i2c_packet.driver_result = EC_RES_SUCCESS; - } else { - /* Only host command protocol 3 is supported. */ - i2c_packet.driver_result = EC_RES_INVALID_HEADER; - } - host_packet_receive(&i2c_packet); -} - -#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS -static void i2c_send_board_response(int len) -{ - /* host_buffer data range, beyond this length, will return 0xec */ - tx_index = 0; - tx_end = len; - - /* enable transmit interrupt and use irq to send data back */ - STM32_I2C_CR2(host_i2c_resp_port) |= STM32_I2C_CR2_ITBUFEN; -} - -static void i2c_process_board_command(int read, int addr, int len) -{ - board_i2c_process(read, addr, len, &host_buffer[0], - i2c_send_board_response); -} -#endif - -static void i2c_event_handler(int port) -{ - volatile uint32_t i2c_cr1; - volatile uint32_t i2c_sr2; - volatile uint32_t i2c_sr1; - static int rx_pending, buf_idx; - static uint16_t addr_8bit; - - volatile uint32_t unused __attribute__((unused)); - - i2c_cr1 = STM32_I2C_CR1(port); - i2c_sr2 = STM32_I2C_SR2(port); - i2c_sr1 = STM32_I2C_SR1(port); - - /* - * Check for error conditions. Note, arbitration loss and bus error - * are the only two errors we can get as a peripheral allowing clock - * stretching and in non-SMBus mode. - */ - if (i2c_sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR)) { - rx_pending = 0; - tx_pending = 0; - /* Disable buffer interrupt */ - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; - /* Clear error status bits */ - STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO | - STM32_I2C_SR1_BERR); - } - - /* Transfer matched our peripheral address */ - if (i2c_sr1 & STM32_I2C_SR1_ADDR) { - addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ? - STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe; - if (i2c_sr2 & STM32_I2C_SR2_TRA) { - /* Transmitter peripheral */ - i2c_sr1 |= STM32_I2C_SR1_TXE; -#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS - if (!rx_pending && !tx_pending) { - tx_pending = 1; - i2c_process_board_command(1, addr_8bit, 0); - } -#endif - } else { - /* Receiver peripheral */ - buf_idx = 0; - rx_pending = 1; - } - - /* Enable buffer interrupt to start receive/response */ - STM32_I2C_CR2(port) |= STM32_I2C_CR2_ITBUFEN; - /* Clear ADDR bit */ - unused = STM32_I2C_SR1(port); - unused = STM32_I2C_SR2(port); - /* Inhibit stop mode when addressed until STOPF flag is set */ - disable_sleep(SLEEP_MASK_I2C_PERIPHERAL); - } - - /* I2C in peripheral transmitter */ - if (i2c_sr2 & STM32_I2C_SR2_TRA) { - if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_TXE)) { - if (tx_pending) { - if (tx_index < tx_end) { - STM32_I2C_DR(port) = - host_buffer[tx_index++]; - } else { - STM32_I2C_DR(port) = 0xec; - tx_index = 0; - tx_end = 0; - tx_pending = 0; - } - } else if (rx_pending) { - host_i2c_resp_port = port; - /* Disable buffer interrupt */ - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; -#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS - if ((addr_8bit >> 1) == - I2C_STRIP_FLAGS( - CONFIG_BOARD_I2C_ADDR_FLAGS)) - i2c_process_board_command(1, addr_8bit, - buf_idx); - else -#endif - i2c_process_command(); - /* Reset host buffer */ - rx_pending = 0; - tx_pending = 1; - } else { - STM32_I2C_DR(port) = 0xec; - } - } - } else { /* I2C in peripheral receiver */ - if (i2c_sr1 & (STM32_I2C_SR1_BTF | STM32_I2C_SR1_RXNE)) - host_buffer[buf_idx++] = STM32_I2C_DR(port); - } - - /* STOPF or AF */ - if (i2c_sr1 & (STM32_I2C_SR1_STOPF | STM32_I2C_SR1_AF)) { - /* Disable buffer interrupt */ - STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; - -#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS - if (rx_pending && - (addr_8b >> 1) == - I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS)) - i2c_process_board_command(0, addr_8bit, buf_idx); -#endif - rx_pending = 0; - tx_pending = 0; - - /* Clear AF */ - STM32_I2C_SR1(port) &= ~STM32_I2C_SR1_AF; - /* Clear STOPF: read SR1 and write CR1 */ - unused = STM32_I2C_SR1(port); - STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE; - - /* No longer inhibit deep sleep after stop condition */ - enable_sleep(SLEEP_MASK_I2C_PERIPHERAL); - } - - /* Enable again */ - if (!(i2c_cr1 & STM32_I2C_CR1_PE)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; -} -void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } -DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2); -DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2); -#endif - - -/* Init all available i2c ports */ -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); - - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - /* Enable ACK */ - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK; - /* Enable interrupts */ - STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN - | STM32_I2C_CR2_ITERREN; - /* Setup host command peripheral */ - STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14 - | (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); -#ifdef CONFIG_BOARD_I2C_ADDR_FLAGS - STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL - | (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1); -#endif - task_enable_irq(IRQ_PERIPHERAL_EV); - task_enable_irq(IRQ_PERIPHERAL_ER); -#endif -} diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c deleted file mode 100644 index eb1c7f1560..0000000000 --- a/chip/stm32/i2c-stm32g4.c +++ /dev/null @@ -1,457 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "i2c.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) - -enum i2c_freq_khz { - freq_100 = 100, - freq_400 = 400, - freq_1000 = 1000, -}; - -struct i2c_timing { - uint8_t scll; - uint8_t sclh; - uint8_t sdadel; - uint8_t scldel; - uint8_t presc; -}; - -/* timing register values for supported input clks / i2c clk rates */ -static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { - [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ -}; - -/* - * The following timing config values are given in Table 371 of TM0440 which - * assumes an I2CCLK freq of 16 MHZ. I2CCLK is connected to HSI, with is @ - * 16MHz. The TRM recommends using the STM32CubeMX tool to get more accurate - * values. Note that the actual clock period is (scll + 1) + (schl + 1) + - * internal detection delays for SCL being low/high. - */ -const struct i2c_timing i2c_timingr[I2C_FREQ_COUNT] = { - [I2C_FREQ_1000KHZ] = { - .scll = 4, - .sclh = 2, - .sdadel = 0, - .scldel = 2, - .presc = 0, - }, - [I2C_FREQ_400KHZ] = { - .scll = 9, - .sclh = 4, - .sdadel = 2, - .scldel = 3, - .presc = 1, - }, - [I2C_FREQ_100KHZ] = { - .scll = 19, - .sclh = 15, - .sdadel = 2, - .scldel = 4, - .presc = 3, - }, -}; - -/* - * For G4, I2C1 and I2C2 are contiguous in address space, but I2C3 and I2C4 are - * at different offsets. In order to make the driver code easier, the base - * address for each port's register block is defined here and can be used in i2c - * register read/write accesses. - */ -static const uint32_t i2c_regs_base[] = { - STM32_I2C1_BASE, - STM32_I2C2_BASE, - STM32_I2C3_BASE, - STM32_I2C4_BASE, -}; - -/* I2C port state data */ -struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER; -} - -/** - * Set i2c clock rate.. - * - * @param p I2C port struct - */ -static void i2c_set_timingr_port(const struct i2c_port_t *p) -{ - int port = p->port; - uint32_t base; - int index; - uint32_t timingr; - - ASSERT(port < I2C_PORT_COUNT); - base = i2c_regs_base[port]; - - /* - * To configure an I2C port frequency requires 5 values. scll, sclh, - * sdadel, scldel, and presc. With these settings, the actual SCL period - * (Tscl) is given by: - * Tscl = Tsync1 + Tsync2 + [(scll+1) + (sclh+1)] * presc * Ti2clck - * - * Using HSI for i2cclk, so this is fixed @ 16MHz. The recommended - * values for the 5 parameters are from the TRM for i2clck @ 16 MHZ. - * Note that Tsyncx is a function of SCL rise/fall times and filtering - * selected for the given I2C port. sdadel and scldel affect when data - * is written or read relative to SCL edges. - */ - - if (p->kbps == freq_100) { - index = I2C_FREQ_100KHZ; - } else if (p->kbps == freq_400) { - index = I2C_FREQ_400KHZ; - } else if (p->kbps == freq_400) { - index = I2C_FREQ_1000KHZ; - } else { - index = I2C_FREQ_100KHZ; - CPRINTS("stm32 i2c[p%d]: Invalid freq, setting 100Khz instead!", - port); - } - /* Assemble write value for timingr register */ - timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) | - (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) | - (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) | - (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) | - (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF); - - /* Write timingr value */ - STM32_I2C_TIMINGR(base) = timingr; - - /* Save freq lookup index for polling loop delay */ - pdata[port].freq = index; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - uint32_t base; - - ASSERT(port < I2C_PORT_COUNT); - base = i2c_regs_base[port]; - - /* - * The I2C module clock can be derived from sysclk, hsi16, or pclk1. - * CrosEC will typically have sysclk = pclk = cpuclk. hsi16 is fixed at - * 16 Mhz and given that it's a known freq, the timing register values - * can be obtained via table lookup. The I2C clock source is selected - * via the I2CnSEL field for a given I2C port. - * - * I2CnSEL is a 2 bit field in same register for ports 0-2 (1-3 in - * STM32 notation), but is in a different register for port 3. - */ - if (port < 3) { - int clksel; - int mask; - int shift; - - shift = STM32_RCC_CCIPR_I2C1SEL_SHIFT + 2 * port; - mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift; - clksel = STM32_RCC_CCIPR; - clksel &= ~mask; - STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI - << shift); - } else if (port == 3) { - /* i2c4sel is bits 1:0, no shift required */ - STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK; - STM32_RCC_CCIPR2 |= STM32_RCC_CCIPR_I2CNSEL_HSI; - } - - /* - * Software reset for an I2C port is performed by clearing the PE bit in - * that port's CR1 register. When this happens, SCL and SDA are - * released, internal stame machines are reset, control/status bits are - * also reset. The I2C block reset requires 3 APB cycles before setting - * PE back to 1. This wait is ensured by the call fo i2c_set_freq_port. - */ - STM32_I2C_CR1(base) &= ~STM32_I2C_CR1_PE; - /* Set up initial bus frequencies */ - i2c_set_timingr_port(p); - /* Enable the I2C port */ - STM32_I2C_CR1(base) |= STM32_I2C_CR1_PE; - - /* Set up default timeout */ - i2c_set_timeout(port, 0); -} - -/*****************************************************************************/ -/* Interface */ -/** - * Wait for ISR register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_isr(int port, int mask) -{ - uint32_t start = __hw_clock_source_read(); - uint32_t delta; - uint32_t base; - - ASSERT(port < I2C_PORT_COUNT); - base = i2c_regs_base[port]; - - do { - int isr = STM32_I2C_ISR(base); - - /* Check for errors */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) - return EC_ERROR_UNKNOWN; - - /* Check for desired mask */ - if ((isr & mask) == mask) - return EC_SUCCESS; - - delta = __hw_clock_source_read() - start; - - /** - * Depending on the bus speed, busy loop for a while before - * sleeping and letting other things run. - */ - if (delta >= busyloop_us[pdata[port].freq]) - usleep(100); - } while (delta < pdata[port].timeout_us); - - return EC_ERROR_TIMEOUT; -} - -/***************************************************************************** - * Exported functions declared in i2c.h - */ -/* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1; - int rv = EC_SUCCESS; - int i; - int xfer_start = flags & I2C_XFER_START; - int xfer_stop = flags & I2C_XFER_STOP; - uint32_t base; - - ASSERT(port < I2C_PORT_COUNT); - base = i2c_regs_base[port]; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - /* Clear status */ - if (xfer_start) { - STM32_I2C_ICR(base) = STM32_I2C_ICR_ALL; - STM32_I2C_CR2(base) = 0; - } - - if (out_bytes || !in_bytes) { - /* - * Configure the write transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we are starting, then set START bit. - */ - STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < out_bytes; i++) { - rv = wait_isr(port, STM32_I2C_ISR_TXIS); - if (rv) - goto xfer_exit; - /* Write next data byte */ - STM32_I2C_TXDR(base) = out[i]; - } - } - if (in_bytes) { - if (out_bytes) { /* wait for completion of the write */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - /* - * Configure the read transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we were just transmitting, we need to - * set START bit to send (re)start and begin read transaction. - */ - STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < in_bytes; i++) { - /* Wait for receive buffer not empty */ - rv = wait_isr(port, STM32_I2C_ISR_RXNE); - if (rv) - goto xfer_exit; - in[i] = STM32_I2C_RXDR(base); - } - } - - /* - * If we are stopping, then we already set AUTOEND and we should - * wait for the stop bit to be transmitted. Otherwise, we set - * the RELOAD bit and we should wait for transfer complete - * reload (TCR). - */ - rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); - if (rv) - goto xfer_exit; - -xfer_exit: - /* clear status */ - if (xfer_stop) - STM32_I2C_ICR(base) = STM32_I2C_ICR_ALL; - - /* On error, queue a stop condition */ - if (rv) { - /* queue a STOP condition */ - STM32_I2C_CR2(base) |= STM32_I2C_CR2_STOP; - /* wait for it to take effect */ - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_ISR(base) & STM32_I2C_ISR_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - /* re-initialize the controller */ - STM32_I2C_CR2(base) = 0; - STM32_I2C_CR1(base) &= ~STM32_I2C_CR1_PE; - udelay(10); - STM32_I2C_CR1(base) |= STM32_I2C_CR1_PE; - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SDA pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -/*****************************************************************************/ -/* Hooks */ - -#ifdef CONFIG_I2C_CONTROLLER -/* Handle an upcoming frequency change. */ -static void i2c_pre_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* Lock I2C ports so freq change can't interrupt an I2C transaction */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 1); -} -DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT); - -/* Handle a frequency change */ -static void i2c_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* - * Handle CPU clock changing frequency and unlock I2C ports we locked - * in pre-freq change hook - */ - for (i = 0; i < i2c_ports_used; i++, p++) { - i2c_set_timingr_port(p); - i2c_lock(p->port, 0); - } -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); -#endif - -/*****************************************************************************/ - -/* Init all available i2c ports */ -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* Configure GPIO alt-func for all I2C ports */ - gpio_config_module(MODULE_I2C, 1); - /* Enable the I2C clock for all I2C ports */ - clock_enable_module(MODULE_I2C, 1); - /* Per port configuration */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); -} diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c deleted file mode 100644 index 2edcb1c0b6..0000000000 --- a/chip/stm32/i2c-stm32l.c +++ /dev/null @@ -1,424 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "i2c.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -#define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST - -/* - * Transmit timeout in microseconds - * - * In theory we shouldn't have a timeout here (at least when we're in slave - * mode). The slave is supposed to wait forever for the master to read bytes. - * ...but we're going to keep the timeout to make sure we're robust. It may in - * fact be needed if the host resets itself mid-read. - * - * NOTE: One case where this timeout is useful is when the battery - * flips out. The battery may flip out and hold lines low for up to - * 25ms. If we just wait it will eventually let them go. - */ -#define I2C_TX_TIMEOUT_MASTER (30 * MSEC) - -/* - * Delay 5us in bitbang mode. That gives us roughly 5us low and 5us high or - * a frequency of 100kHz. - */ -#define I2C_BITBANG_HALF_CYCLE_US 5 - -#ifdef CONFIG_I2C_DEBUG -static void dump_i2c_reg(int port, const char *what) -{ - CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s", - STM32_I2C_CR1(port), - STM32_I2C_CR2(port), - STM32_I2C_SR1(port), - STM32_I2C_SR2(port), - what); -} -#else -static inline void dump_i2c_reg(int port, const char *what) -{ -} -#endif - -/** - * Wait for SR1 register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_sr1(int port, int mask) -{ - uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER; - - while (get_time().val < timeout) { - int sr1 = STM32_I2C_SR1(port); - - /* Check for errors */ - if (sr1 & (STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR | - STM32_I2C_SR1_AF)) { - dump_i2c_reg(port, "wait_sr1 failed"); - return EC_ERROR_UNKNOWN; - } - - /* Check for desired mask */ - if ((sr1 & mask) == mask) - return EC_SUCCESS; - - /* I2C is slow, so let other things run while we wait */ - usleep(100); - } - - return EC_ERROR_TIMEOUT; -} - -/** - * Send a start condition and slave address on the specified port. - * - * @param port I2C port - * @param slave_addr Slave address, with LSB set for receive-mode - * - * @return Non-zero if error. - */ -static int send_start(int port, uint16_t slave_addr_8bit) -{ - int rv; - - /* Send start bit */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_START; - dump_i2c_reg(port, "sent start"); - rv = wait_sr1(port, STM32_I2C_SR1_SB); - if (rv) - return I2C_ERROR_FAILED_START; - - /* Write slave address */ - STM32_I2C_DR(port) = slave_addr_8bit & 0xff; - rv = wait_sr1(port, STM32_I2C_SR1_ADDR); - if (rv) - return rv; - - /* Read SR2 to clear ADDR bit */ - rv = STM32_I2C_SR2(port); - - dump_i2c_reg(port, "wrote addr"); - - return EC_SUCCESS; -} - -static void i2c_set_freq_port(const struct i2c_port_t *p) -{ - int port = p->port; - int freq = clock_get_freq(); - - /* Force peripheral reset and disable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST; - STM32_I2C_CR1(port) = 0; - - /* Set clock frequency */ - STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); - STM32_I2C_CR2(port) = freq / SECOND; - STM32_I2C_TRISE(port) = freq / SECOND + 1; - - /* Enable port */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - - /* Enable clocks to I2C modules if necessary */ - if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) - STM32_RCC_APB1ENR |= 1 << (21 + port); - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p); -} - -/*****************************************************************************/ -/* Interface */ - -int chip_i2c_xfer(const int port, - const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1; - int started = (flags & I2C_XFER_START) ? 0 : 1; - int rv = EC_SUCCESS; - int i; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - dump_i2c_reg(port, "xfer start"); - - /* - * Clear status - * - * TODO(crosbug.com/p/29314): should check for any leftover error - * status, and reset the port if present. - */ - STM32_I2C_SR1(port) = 0; - - /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); - - /* No out bytes and no in bytes means just check for active */ - if (out_bytes || !in_bytes) { - if (!started) { - rv = send_start(port, addr_8bit); - if (rv) - goto xfer_exit; - } - - /* Write data, if any */ - for (i = 0; i < out_bytes; i++) { - /* Write next data byte */ - STM32_I2C_DR(port) = out[i]; - dump_i2c_reg(port, "wrote data"); - - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - } - - /* Need repeated start condition before reading */ - started = 0; - - /* If no input bytes, queue stop condition */ - if (!in_bytes && (flags & I2C_XFER_STOP)) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - } - - if (in_bytes) { - /* Setup ACK/POS before sending start as per user manual */ - if (in_bytes == 2) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_POS; - else if (in_bytes != 1) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_ACK; - - if (!started) { - rv = send_start(port, addr_8bit | 0x01); - if (rv) - goto xfer_exit; - } - - if (in_bytes == 1) { - /* Set stop immediately after ADDR cleared */ - if (flags & I2C_XFER_STOP) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - rv = wait_sr1(port, STM32_I2C_SR1_RXNE); - if (rv) - goto xfer_exit; - - in[0] = STM32_I2C_DR(port); - } else if (in_bytes == 2) { - /* Wait till the shift register is full */ - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - - if (flags & I2C_XFER_STOP) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - in[0] = STM32_I2C_DR(port); - in[1] = STM32_I2C_DR(port); - } else { - /* Read all but last three */ - for (i = 0; i < in_bytes - 3; i++) { - /* Wait for receive buffer not empty */ - rv = wait_sr1(port, STM32_I2C_SR1_RXNE); - if (rv) - goto xfer_exit; - - dump_i2c_reg(port, "read data"); - in[i] = STM32_I2C_DR(port); - dump_i2c_reg(port, "post read data"); - } - - /* Wait for BTF (data N-2 in DR, N-1 in shift) */ - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - - /* No more acking */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_ACK; - in[i++] = STM32_I2C_DR(port); - - /* Wait for BTF (data N-1 in DR, N in shift) */ - rv = wait_sr1(port, STM32_I2C_SR1_BTF); - if (rv) - goto xfer_exit; - - /* If this is the last byte, queue stop condition */ - if (flags & I2C_XFER_STOP) - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - - /* Read the last two bytes */ - in[i++] = STM32_I2C_DR(port); - in[i++] = STM32_I2C_DR(port); - } - } - - xfer_exit: - /* On error, queue a stop condition */ - if (rv) { - flags |= I2C_XFER_STOP; - STM32_I2C_CR1(port) |= STM32_I2C_CR1_STOP; - dump_i2c_reg(port, "stop after error"); - - /* - * If failed at sending start, try resetting the port - * to unwedge the bus. - */ - if (rv == I2C_ERROR_FAILED_START) { - const struct i2c_port_t *p = i2c_ports; - CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); - - i2c_unwedge(port); - - for (i = 0; i < i2c_ports_used; i++, p++) { - if (p->port == port) { - i2c_init_port(p); - break; - } - } - } - } - - /* If a stop condition is queued, wait for it to take effect */ - if (flags & I2C_XFER_STOP) { - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_SR2(port) & STM32_I2C_SR2_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) - return gpio_get_level(g); - - /* If no SCL pin defined for this port, then return 1 to appear idle. */ - return 1; -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -/*****************************************************************************/ -/* Hooks */ - -/* Handle CPU clock changing frequency */ -static void i2c_freq_change(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_set_freq_port(p); -} - -static void i2c_pre_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - /* Lock I2C ports so freq change can't interrupt an I2C transaction */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 1); -} -DECLARE_HOOK(HOOK_PRE_FREQ_CHANGE, i2c_pre_freq_change_hook, HOOK_PRIO_DEFAULT); -static void i2c_freq_change_hook(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - i2c_freq_change(); - - /* Unlock I2C ports we locked in pre-freq change hook */ - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_lock(p->port, 0); -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); - -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); -} - -/*****************************************************************************/ -/* Console commands */ - -static int command_i2cdump(int argc, char **argv) -{ - dump_i2c_reg(I2C_PORT_MASTER, "dump"); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, - NULL, - "Dump I2C regs"); diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c deleted file mode 100644 index 5997ed5b70..0000000000 --- a/chip/stm32/i2c-stm32l4.c +++ /dev/null @@ -1,470 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "printf.h" -#include "chipset.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "i2c.h" -#include "registers.h" - -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -/* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -#define I2C_SLAVE_ERROR_CODE 0xec -#if (I2C_PORT_EC == STM32_I2C1_PORT) -#define IRQ_SLAVE STM32_IRQ_I2C1 -#else -#define IRQ_SLAVE STM32_IRQ_I2C2 -#endif -#endif - -/* I2C port state data */ -struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ -}; -static struct i2c_port_data pdata[I2C_PORT_COUNT]; - -void i2c_set_timeout(int port, uint32_t timeout) -{ - pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER; -} - -/* timing register values for supported input clks / i2c clk rates */ -static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { - [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ -}; - -/** - * Wait for ISR register to contain the specified mask. - * - * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or - * EC_ERROR_UNKNOWN if an error bit appeared in the status register. - */ -static int wait_isr(int port, int mask) -{ - uint32_t start = __hw_clock_source_read(); - uint32_t delta = 0; - - do { - int isr = STM32_I2C_ISR(port); - - /* Check for errors */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) - return EC_ERROR_UNKNOWN; - - /* Check for desired mask */ - if ((isr & mask) == mask) - return EC_SUCCESS; - - delta = __hw_clock_source_read() - start; - - /** - * Depending on the bus speed, busy loop for a while before - * sleeping and letting other things run. - */ - if (delta >= busyloop_us[pdata[port].freq]) - usleep(100); - } while (delta < pdata[port].timeout_us); - - return EC_ERROR_TIMEOUT; -} - -/* Supported i2c input clocks */ -enum stm32_i2c_clk_src { - I2C_CLK_SRC_48MHZ = 0, - I2C_CLK_SRC_16MHZ = 1, - I2C_CLK_SRC_COUNT, -}; - -/* timing register values for supported input clks / i2c clk rates - * - * These values are calculated using ST's STM32cubeMX tool - */ -static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { - [I2C_CLK_SRC_48MHZ] = { - [I2C_FREQ_1000KHZ] = 0x20000209, - [I2C_FREQ_400KHZ] = 0x2010091A, - [I2C_FREQ_100KHZ] = 0x20303E5D, - }, - [I2C_CLK_SRC_16MHZ] = { - [I2C_FREQ_1000KHZ] = 0x00000107, - [I2C_FREQ_400KHZ] = 0x00100B15, - [I2C_FREQ_100KHZ] = 0x00303D5B, - }, -}; - -static void i2c_set_freq_port(const struct i2c_port_t *p, - enum stm32_i2c_clk_src src, - enum i2c_freq freq) -{ - int port = p->port; - - /* Disable port */ - STM32_I2C_CR1(port) = 0; - STM32_I2C_CR2(port) = 0; - /* Set clock frequency */ - STM32_I2C_TIMINGR(port) = timingr_regs[src][freq]; - /* Enable port */ - STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; - - pdata[port].freq = freq; -} - -/** - * Initialize on the specified I2C port. - * - * @param p the I2c port - */ -static void i2c_init_port(const struct i2c_port_t *p) -{ - int port = p->port; - uint32_t val; - enum i2c_freq freq; - enum stm32_i2c_clk_src src = I2C_CLK_SRC_16MHZ; - - /* Enable I2C clock */ - if (!(STM32_RCC_APB1ENR1 & (1 << (21 + port)))) - STM32_RCC_APB1ENR1 |= 1 << (21 + port); - - /* Select HSI 16MHz as I2C clock source */ - val = STM32_RCC_CCIPR; - val &= ~(STM32_RCC_CCIPR_I2C1SEL_MASK << (port * 2)); - val |= STM32_RCC_CCIPR_I2C_HSI16 - << (STM32_RCC_CCIPR_I2C1SEL_SHIFT + port * 2); - STM32_RCC_CCIPR = val; - - /* Configure GPIOs */ - gpio_config_module(MODULE_I2C, 1); - - /* Set clock frequency */ - switch (p->kbps) { - case 1000: - STM32_SYSCFG_CFGR1 |= STM32_SYSCFG_I2CFMP(port); - freq = I2C_FREQ_1000KHZ; - break; - case 400: - freq = I2C_FREQ_400KHZ; - break; - case 100: - freq = I2C_FREQ_100KHZ; - break; - default: /* unknown speed, defaults to 100kBps */ - CPRINTS("I2C bad speed %d kBps", p->kbps); - freq = I2C_FREQ_100KHZ; - } - - /* Set up initial bus frequencies */ - i2c_set_freq_port(p, src, freq); - - /* Set up default timeout */ - i2c_set_timeout(port, 0); -} - -/*****************************************************************************/ - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - -static void i2c_event_handler(int port) -{ - /* Variables tracking the handler state. - * TODO: Should have as many sets of these variables as the number - * of slave ports. - */ - static int rx_pending, rx_idx; - static int tx_pending, tx_idx, tx_end; - static uint8_t slave_buffer[I2C_MAX_HOST_PACKET_SIZE + 2]; - int isr = STM32_I2C_ISR(port); - - /* - * Check for error conditions. Note, arbitration loss and bus error - * are the only two errors we can get as a slave allowing clock - * stretching and in non-SMBus mode. - */ - if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) { - rx_pending = 0; - tx_pending = 0; - - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear error status bits */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF - | STM32_I2C_ICR_ARLOCF; - } - - /* Transfer matched our slave address */ - if (isr & STM32_I2C_ISR_ADDR) { - if (isr & STM32_I2C_ISR_DIR) { - /* Transmitter slave */ - /* Clear transmit buffer */ - STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE; - - if (rx_pending) - /* RESTART */ - i2c_data_received(port, slave_buffer, rx_idx); - tx_end = i2c_set_response(port, slave_buffer, rx_idx); - tx_idx = 0; - rx_pending = 0; - tx_pending = 1; - - /* Enable txis interrupt to start response */ - STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE; - } else { - /* Receiver slave */ - rx_idx = 0; - rx_pending = 1; - tx_pending = 0; - } - - /* Clear ADDR bit by writing to ADDRCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF; - /* Inhibit stop mode when addressed until STOPF flag is set */ - disable_sleep(SLEEP_MASK_I2C_PERIPHERAL); - } - - /* - * Receive buffer not empty - * - * When a master finishes sending data, it'll set STOP bit. It causes - * the slave to receive RXNE and STOP interrupt at the same time. So, - * we need to process RXNE first, then handle STOP. - */ - if (isr & STM32_I2C_ISR_RXNE) - slave_buffer[rx_idx++] = STM32_I2C_RXDR(port); - - /* Stop condition on bus */ - if (isr & STM32_I2C_ISR_STOP) { - if (rx_pending) - i2c_data_received(port, slave_buffer, rx_idx); - tx_idx = 0; - tx_end = 0; - rx_pending = 0; - tx_pending = 0; - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - - /* Clear STOPF bit by writing to STOPCF bit */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF; - - /* No longer inhibit deep sleep after stop condition */ - enable_sleep(SLEEP_MASK_I2C_PERIPHERAL); - } - - if (isr & STM32_I2C_ISR_NACK) { - /* Make sure TXIS interrupt is disabled */ - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; - /* Clear NACK */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF; - } - - /* Transmitter empty event */ - if (isr & STM32_I2C_ISR_TXIS) { - if (port == I2C_PORT_EC) { - if (tx_pending) { - if (tx_idx < tx_end) { - STM32_I2C_TXDR(port) = - slave_buffer[tx_idx++]; - } else { - STM32_I2C_TXDR(port) - = I2C_SLAVE_ERROR_CODE; - tx_idx = 0; - tx_end = 0; - tx_pending = 0; - } - } else { - STM32_I2C_TXDR(port) = I2C_SLAVE_ERROR_CODE; - } - } - } -} - -void i2c_event_interrupt(void) -{ - i2c_event_handler(I2C_PORT_EC); -} -DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2); -#endif - -/*****************************************************************************/ -/* Interface */ - -int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) -{ - int addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1; - int rv = EC_SUCCESS; - int i; - int xfer_start = flags & I2C_XFER_START; - int xfer_stop = flags & I2C_XFER_STOP; - - ASSERT(out || !out_bytes); - ASSERT(in || !in_bytes); - - /* Clear status */ - if (xfer_start) { - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - STM32_I2C_CR2(port) = 0; - } - - if (out_bytes || !in_bytes) { - /* - * Configure the write transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we are starting, then set START bit. - */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < out_bytes; i++) { - rv = wait_isr(port, STM32_I2C_ISR_TXIS); - if (rv) - goto xfer_exit; - /* Write next data byte */ - STM32_I2C_TXDR(port) = out[i]; - } - } - if (in_bytes) { - if (out_bytes) { /* wait for completion of the write */ - rv = wait_isr(port, STM32_I2C_ISR_TC); - if (rv) - goto xfer_exit; - } - /* - * Configure the read transfer: if we are stopping then set - * AUTOEND bit to automatically set STOP bit after NBYTES. - * if we are not stopping, set RELOAD bit so that we can load - * NBYTES again. if we were just transmitting, we need to - * set START bit to send (re)start and begin read transaction. - */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); - - for (i = 0; i < in_bytes; i++) { - /* Wait for receive buffer not empty */ - rv = wait_isr(port, STM32_I2C_ISR_RXNE); - if (rv) - goto xfer_exit; - - in[i] = STM32_I2C_RXDR(port); - } - } - - /* - * If we are stopping, then we already set AUTOEND and we should - * wait for the stop bit to be transmitted. Otherwise, we set - * the RELOAD bit and we should wait for transfer complete - * reload (TCR). - */ - rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); - if (rv) - goto xfer_exit; - -xfer_exit: - /* clear status */ - if (xfer_stop) - STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; - - /* On error, queue a stop condition */ - if (rv) { - /* queue a STOP condition */ - STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; - /* wait for it to take effect */ - /* Wait up to 100 us for bus idle */ - for (i = 0; i < 10; i++) { - if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) - break; - udelay(10); - } - - /* - * Allow bus to idle for at least one 100KHz clock = 10 us. - * This allows slaves on the bus to detect bus-idle before - * the next start condition. - */ - udelay(10); - /* re-initialize the controller */ - STM32_I2C_CR2(port) = 0; - STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; - udelay(10); - STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; - } - - return rv; -} - -int i2c_raw_get_scl(int port) -{ - enum gpio_signal g; - - if (get_scl_from_i2c_port(port, &g)) - /* If no SCL pin is defined, return 1 to appear idle. */ - return 1; - - return gpio_get_level(g); -} - -int i2c_raw_get_sda(int port) -{ - enum gpio_signal g; - - if (get_sda_from_i2c_port(port, &g)) - /* If no SDA pin is defined, return 1 to appear idle. */ - return 1; - - return gpio_get_level(g); -} - -int i2c_get_line_levels(int port) -{ - return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); -} - -void i2c_init(void) -{ - const struct i2c_port_t *p = i2c_ports; - int i; - - for (i = 0; i < i2c_ports_used; i++, p++) - i2c_init_port(p); - -#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); - task_enable_irq(IRQ_SLAVE); -#endif -} diff --git a/chip/stm32/i2c-stm32l5.c b/chip/stm32/i2c-stm32l5.c deleted file mode 100644 index 86cc1c6df2..0000000000 --- a/chip/stm32/i2c-stm32l5.c +++ /dev/null @@ -1,6 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "i2c-stm32l4.c" diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c deleted file mode 100644 index 916a8c364c..0000000000 --- a/chip/stm32/i2c_ite_flash_support.c +++ /dev/null @@ -1,356 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -/* STM implementation for flashing ITE-based ECs over i2c */ - -#include "i2c_ite_flash_support.h" -#include "i2c.h" -#include "registers.h" -#include "time.h" - -/* - * As of 2018-11-27 the default for both is 60 bytes. These larger values allow - * for reflashing of ITE EC chips over I2C - * (https://issuetracker.google.com/79684405) in reasonably speedy fashion. If - * the EC firmware defaults are ever raised significantly, consider removing - * these overrides. - * - * As of 2018-11-27 the actual maximum write size supported by the I2C-over-USB - * protocol is (1<<12)-1, and the maximum read size supported is - * (1<<15)-1. However compile time assertions require that these values be - * powers of 2 after overheads are included. Thus, the write limit set here - * /should/ be (1<<12)-4 and the read limit should be (1<<15)-6, however those - * ideal limits are not actually possible because stm32 lacks sufficient - * spare memory for them. With symmetrical limits, the maximum that currently - * fits is (1<<11)-4 write limit and (1<<11)-6 read limit, leaving 1404 bytes of - * RAM available. - * - * However even with a sufficiently large write value here, the maximum that - * actually works as of 2018-12-03 is 255 bytes. Additionally, ITE EC firmware - * image verification requires exactly 256 byte reads. Thus the only useful - * powers-of-2-minus-overhead limits to set here are (1<<9)-4 writes and - * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of - * RAM available with the default 60 byte limits. - */ -#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4) -#error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4) -#endif -#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6) -#error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6) -#endif - -/* - * iteflash requires 256 byte reads for verifying ITE EC firmware. Without this - * the limit is CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE which is 255 for STM32F0 due - * to an 8 bit field, per src/platform/ec/include/config.h comment. - */ -#ifndef CONFIG_I2C_XFER_LARGE_TRANSFER -#error Must define CONFIG_I2C_XFER_LARGE_TRANSFER -#endif - -#define KHz 1000 -#define MHz (1000 * KHz) - -/* - * These constants are values that one might want to try changing if - * enable_ite_dfu stops working, or does not work on a new ITE EC chip revision. - */ - -#define ITE_DFU_I2C_CMD_ADDR_FLAGS 0x5A -#define ITE_DFU_I2C_DATA_ADDR_FLAGS 0x35 - -#define SMCLK_WAVEFORM_PERIOD_HZ (100 * KHz) -#define SMDAT_WAVEFORM_PERIOD_HZ (200 * KHz) - -#define START_DELAY_MS 5 -#define SPECIAL_WAVEFORM_MS 50 -#define PLL_STABLE_MS 10 - -/* - * Digital line levels to hold before (PRE_) or after (POST_) sending the - * special waveforms. 0 for low, 1 for high. - */ -#define SMCLK_PRE_LEVEL 0 -#define SMDAT_PRE_LEVEL 0 -#define SMCLK_POST_LEVEL 0 -#define SMDAT_POST_LEVEL 0 - -/* The caller should hold the i2c_lock() for ite_dfu_config.i2c_port. */ -static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output) -{ - /* - * Ideally the write and read would be done in one I2C transaction, as - * is normally done when reading from the same I2C address that the - * write was sent to. The ITE EC is abnormal in that regard, with its - * different 7-bit addresses for writes vs reads. - * - * i2c_xfer() does not support that. Its I2C_XFER_START and - * I2C_XFER_STOP flag bits do not cleanly support that scenario, they - * are for continuing transfers without either of STOP or START - * in-between. - * - * For what it's worth, the iteflash.c FTDI-based implementation of this - * does the same thing, issuing a STOP between the write and read. This - * works, even if perhaps it should not. - */ - int ret; - /* Tell the ITE EC which register we want to read. */ - ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port, - ITE_DFU_I2C_CMD_ADDR_FLAGS, - ®ister_offset, sizeof(register_offset), - NULL, 0, I2C_XFER_SINGLE); - if (ret != EC_SUCCESS) - return ret; - /* Read in the 1 byte register value. */ - ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port, - ITE_DFU_I2C_DATA_ADDR_FLAGS, - NULL, 0, - output, sizeof(*output), I2C_XFER_SINGLE); - return ret; -} - -/* Helper function to read ITE chip ID, for verifying ITE DFU mode. */ -static int cprint_ite_chip_id(void) -{ - /* - * Per i2c_read8() implementation, use an array even for single byte - * reads to ensure alignment for DMA on STM32. - */ - uint8_t chipid1[1]; - uint8_t chipid2[1]; - uint8_t chipver[1]; - - int ret; - int chip_version; - int flash_kb; - - i2c_lock(ite_dfu_config.i2c_port, 1); - - /* Read the CHIPID1 register. */ - ret = ite_i2c_read_register(0x00, chipid1); - if (ret != EC_SUCCESS) - goto unlock; - - /* Read the CHIPID2 register. */ - ret = ite_i2c_read_register(0x01, chipid2); - if (ret != EC_SUCCESS) - goto unlock; - - /* Read the CHIPVER register. */ - ret = ite_i2c_read_register(0x02, chipver); - -unlock: - i2c_lock(ite_dfu_config.i2c_port, 0); - if (ret != EC_SUCCESS) - return ret; - - /* - * Compute chip version and embedded flash size from the CHIPVER value. - * - * Chip version is mapping from bit 3-0 - * Flash size is mapping from bit 7-4 - * - * Chip Version (bits 3-0) - * 0: AX - * 1: BX - * 2: CX - * 3: DX - * - * CX or prior flash size (bits 7-4) - * 0:128KB - * 4:192KB - * 8:256KB - * - * DX flash size (bits 7-4) - * 0:128KB - * 2:192KB - * 4:256KB - * 6:384KB - * 8:512KB - */ - chip_version = chipver[0] & 0x07; - if (chip_version < 0x3) { - /* Chip version is CX or earlier. */ - switch (chipver[0] >> 4) { - case 0: - flash_kb = 128; - break; - case 4: - flash_kb = 192; - break; - case 8: - flash_kb = 256; - break; - default: - flash_kb = -2; - } - } else if (chip_version == 0x3) { - /* Chip version is DX. */ - switch (chipver[0] >> 4) { - case 0: - flash_kb = 128; - break; - case 2: - flash_kb = 192; - break; - case 4: - flash_kb = 256; - break; - case 6: - flash_kb = 384; - break; - case 8: - flash_kb = 512; - break; - default: - flash_kb = -3; - } - } else { - /* Unrecognized chip version. */ - flash_kb = -1; - } - - ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ", - chipid1[0], chipid2[0], chipver[0]); - ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10); - - /* - * IT8320_eflash_SMBus_Programming_Guide.pdf says it is an error if - * CHIPID1 != 0x83. - */ - if (chipid1[0] != 0x83) - ret = EC_ERROR_HW_INTERNAL; - - return ret; -} - -/* Enable ITE direct firmware update (DFU) mode. */ -static int command_enable_ite_dfu(int argc, char **argv) -{ - if (argc > 1) - return EC_ERROR_PARAM_COUNT; - - /* Ensure we can perform the dfu operation */ - if (ite_dfu_config.access_allow && !ite_dfu_config.access_allow()) - return EC_ERROR_ACCESS_DENIED; - - /* Enable peripheral clocks. */ - STM32_RCC_APB2ENR |= - STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN; - - /* Reset timer registers which are not otherwise set below. */ - STM32_TIM_CR2(16) = 0x0000; - STM32_TIM_CR2(17) = 0x0000; - STM32_TIM_DIER(16) = 0x0000; - STM32_TIM_DIER(17) = 0x0000; - STM32_TIM_SR(16) = 0x0000; - STM32_TIM_SR(17) = 0x0000; - STM32_TIM_CNT(16) = 0x0000; - STM32_TIM_CNT(17) = 0x0000; - STM32_TIM_RCR(16) = 0x0000; - STM32_TIM_RCR(17) = 0x0000; - STM32_TIM_DCR(16) = 0x0000; - STM32_TIM_DCR(17) = 0x0000; - STM32_TIM_DMAR(16) = 0x0000; - STM32_TIM_DMAR(17) = 0x0000; - - /* Prescale to 1 MHz and use ARR to achieve NNN KHz periods. */ - /* This approach is seen in STM's documentation. */ - STM32_TIM_PSC(16) = (CPU_CLOCK / MHz) - 1; - STM32_TIM_PSC(17) = (CPU_CLOCK / MHz) - 1; - - /* Set the waveform periods based on 1 MHz prescale. */ - STM32_TIM_ARR(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) - 1; - STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1; - - /* Set output compare 1 mode to PWM mode 1 and enable preload. */ - STM32_TIM_CCMR1(16) = - STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE; - STM32_TIM_CCMR1(17) = - STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE; - - /* - * Enable output compare 1 (or its N counterpart). Note that if only - * OC1N is enabled, then it is not complemented. From datasheet: - * "When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented" - * - * Note: we want the rising edge of SDA to be in the middle of SCL, so - * invert the SDA (faster) signal. - */ - if (ite_dfu_config.use_complement_timer_channel) { - STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1NE; - STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1NE | - STM32_TIM_CCER_CC1NP; - } else { - STM32_TIM_CCER(16) = STM32_TIM_CCER_CC1E; - STM32_TIM_CCER(17) = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; - } - - /* Enable main output. */ - STM32_TIM_BDTR(16) = STM32_TIM_BDTR_MOE; - STM32_TIM_BDTR(17) = STM32_TIM_BDTR_MOE; - - /* Update generation (reinitialize counters). */ - STM32_TIM_EGR(16) = STM32_TIM_EGR_UG; - STM32_TIM_EGR(17) = STM32_TIM_EGR_UG; - - /* Set duty cycle to 0% or 100%, pinning each channel low or high. */ - STM32_TIM_CCR1(16) = SMCLK_PRE_LEVEL ? 0xFFFF : 0x0000; - STM32_TIM_CCR1(17) = SMDAT_PRE_LEVEL ? 0xFFFF : 0x0000; - - /* Enable timer counters. */ - STM32_TIM_CR1(16) = STM32_TIM_CR1_CEN; - STM32_TIM_CR1(17) = STM32_TIM_CR1_CEN; - - /* Set GPIO to alternate mode TIM(16|17)_CH1(N)? */ - gpio_config_pin(MODULE_I2C_TIMERS, ite_dfu_config.scl, 1); - gpio_config_pin(MODULE_I2C_TIMERS, ite_dfu_config.sda, 1); - - msleep(START_DELAY_MS); - - /* Set pulse width to half of waveform period. */ - STM32_TIM_CCR1(16) = (MHz / SMCLK_WAVEFORM_PERIOD_HZ) / 2; - STM32_TIM_CCR1(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) / 2; - - msleep(SPECIAL_WAVEFORM_MS); - - /* Set duty cycle to 0% or 100%, pinning each channel low or high. */ - STM32_TIM_CCR1(16) = SMCLK_POST_LEVEL ? 0xFFFF : 0x0000; - STM32_TIM_CCR1(17) = SMDAT_POST_LEVEL ? 0xFFFF : 0x0000; - - msleep(PLL_STABLE_MS); - - /* Set GPIO back to alternate mode I2C. */ - gpio_config_pin(MODULE_I2C, ite_dfu_config.scl, 1); - gpio_config_pin(MODULE_I2C, ite_dfu_config.sda, 1); - - /* Disable timer counters. */ - STM32_TIM_CR1(16) = 0x0000; - STM32_TIM_CR1(17) = 0x0000; - - /* Disable peripheral clocks. */ - STM32_RCC_APB2ENR &= - ~(STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN); - - return cprint_ite_chip_id(); -} -DECLARE_CONSOLE_COMMAND( - enable_ite_dfu, command_enable_ite_dfu, "", - "Enable ITE Direct Firmware Update (DFU) mode"); - -/* Read ITE chip ID. Can be used to verify ITE DFU mode. */ -static int command_get_ite_chipid(int argc, char **argv) -{ - if (argc > 1) - return EC_ERROR_PARAM_COUNT; - - /* Ensure we can perform the dfu operation */ - if (ite_dfu_config.access_allow && !ite_dfu_config.access_allow()) - return EC_ERROR_ACCESS_DENIED; - - return cprint_ite_chip_id(); -} -DECLARE_CONSOLE_COMMAND( - get_ite_chipid, command_get_ite_chipid, "", - "Read ITE EC chip ID, version, flash size (must be in DFU mode)"); diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c deleted file mode 100644 index 219676968a..0000000000 --- a/chip/stm32/keyboard_raw.c +++ /dev/null @@ -1,143 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Raw keyboard I/O layer for STM32 - * - * To make this code portable, we rely heavily on looping over the keyboard - * input and output entries in the board's gpio_list[]. Each set of inputs or - * outputs must be listed in consecutive, increasing order so that scan loops - * can iterate beginning at KB_IN00 or KB_OUT00 for however many GPIOs are - * utilized (KEYBOARD_ROWS or KEYBOARD_COLS_MAX). - */ - -#include "gpio.h" -#include "keyboard_config.h" -#include "keyboard_raw.h" -#include "keyboard_scan.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* Mask of external interrupts on input lines */ -static unsigned int irq_mask; - -static const uint32_t kb_out_ports[] = { KB_OUT_PORT_LIST }; - -static void set_irq_mask(void) -{ - int i; - - for (i = GPIO_KB_IN00; i < GPIO_KB_IN00 + KEYBOARD_ROWS; i++) - irq_mask |= gpio_list[i].mask; -} - -void keyboard_raw_init(void) -{ - /* Determine EXTI_PR mask to use for the board */ - set_irq_mask(); - - /* Ensure interrupts are disabled in EXTI_PR */ - keyboard_raw_enable_interrupt(0); -} - -void keyboard_raw_task_start(void) -{ - /* Enable interrupts for keyboard matrix inputs */ - gpio_enable_interrupt(GPIO_KB_IN00); - gpio_enable_interrupt(GPIO_KB_IN01); - gpio_enable_interrupt(GPIO_KB_IN02); - gpio_enable_interrupt(GPIO_KB_IN03); - gpio_enable_interrupt(GPIO_KB_IN04); - gpio_enable_interrupt(GPIO_KB_IN05); - gpio_enable_interrupt(GPIO_KB_IN06); - gpio_enable_interrupt(GPIO_KB_IN07); -} - -test_mockable void keyboard_raw_drive_column(int out) -{ - int i, done = 0; - - for (i = 0; i < ARRAY_SIZE(kb_out_ports); i++) { - uint32_t bsrr = 0; - int j; - - for (j = GPIO_KB_OUT00; j <= GPIO_KB_OUT12; j++) { - if (gpio_list[j].port != kb_out_ports[i]) - continue; - - if (out == KEYBOARD_COLUMN_ALL) { - /* drive low (clear bit) */ - bsrr |= gpio_list[j].mask << 16; - } else if (out == KEYBOARD_COLUMN_NONE) { - /* put output in hi-Z state (set bit) */ - bsrr |= gpio_list[j].mask; - } else if (j - GPIO_KB_OUT00 == out) { - /* - * Drive specified output low, others => hi-Z. - * - * To avoid conflict, tri-state all outputs - * first, then assert specified output. - */ - keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE); - bsrr |= gpio_list[j].mask << 16; - done = 1; - break; - } - } - - #ifdef CONFIG_KEYBOARD_COL2_INVERTED - if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 | - gpio_list[GPIO_KB_OUT02].mask)) - bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 | - gpio_list[GPIO_KB_OUT02].mask); - #endif - - if (bsrr) - STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr; - - if (done) - break; - } -} - -test_mockable int keyboard_raw_read_rows(void) -{ - int i; - unsigned int port, prev_port = 0; - int state = 0; - uint16_t port_val = 0; - - for (i = 0; i < KEYBOARD_ROWS; i++) { - port = gpio_list[GPIO_KB_IN00 + i].port; - if (port != prev_port) { - port_val = STM32_GPIO_IDR(port); - prev_port = port; - } - - if (port_val & gpio_list[GPIO_KB_IN00 + i].mask) - state |= 1 << i; - } - - /* Invert it so 0=not pressed, 1=pressed */ - return state ^ 0xff; -} - -void keyboard_raw_enable_interrupt(int enable) -{ - if (enable) { - /* - * Assert all outputs would trigger un-wanted interrupts. - * Clear them before enable interrupt. - */ - STM32_EXTI_PR |= irq_mask; - STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */ - } else { - STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */ - } -} - -void keyboard_raw_gpio_interrupt(enum gpio_signal signal) -{ - task_wake(TASK_ID_KEYSCAN); -} diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc deleted file mode 100644 index 2381c511f2..0000000000 --- a/chip/stm32/memory_regions.inc +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifdef CONFIG_USB_RAM_SIZE -REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \ - CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2) -#endif /* CONFIG_USB_RAM_SIZE */ -#ifdef CHIP_VARIANT_STM32H7X3 -REGION(itcm, wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */ -REGION(dtcm, rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */ -REGION(ahb, rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */ -REGION(ahb4, rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */ -REGION(backup, rw, 0x38800000, 0x01000) /* Backup RAM: 4kB */ -#endif /* CHIP_VARIANT_STM32H7X3 */ diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c deleted file mode 100644 index 45ce38d159..0000000000 --- a/chip/stm32/otp-stm32f4.c +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* OTP implementation for STM32F411 */ - -#include "common.h" -#include "console.h" -#include "flash.h" -#include "otp.h" -#include "registers.h" -#include "util.h" - -/* - * OTP is only used for saving the USB serial number. - */ -#ifdef CONFIG_SERIALNO_LEN -/* Which block to use */ -#define OTP_SERIAL_BLOCK 0 -#define OTP_SERIAL_ADDR \ - REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0)) - -/* Number of word used in the block */ -#define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t)) -BUILD_ASSERT(CONFIG_SERIALNO_LEN % sizeof(uint32_t) == 0); -BUILD_ASSERT(OTP_SERIAL_BLOCK_SIZE < STM32_OTP_BLOCK_SIZE); - -/* - * Write an OTP block - * - * @param block block to write. - * @param size Number of words to write. - * @param data Destination buffer for data. - */ -static int otp_write(uint8_t block, int size, const char *data) -{ - if (block >= STM32_OTP_BLOCK_NB) - return EC_ERROR_PARAM1; - if (size >= STM32_OTP_BLOCK_SIZE) - return EC_ERROR_PARAM2; - return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) - - CONFIG_PROGRAM_MEMORY_BASE, - size * sizeof(uint32_t), data); -} - -/* - * Check if an OTP block is protected. - * - * @param block protected block. - * @return non-zero if that block is read only. - */ -static int otp_get_protect(uint8_t block) -{ - uint32_t lock; - - lock = REG32(STM32_OTP_LOCK(block)); - return ((lock & STM32_OPT_LOCK_MASK(block)) == 0); -} - -/* - * Set a particular OTP block as read only. - * - * @param block block to protect. - */ -static int otp_set_protect(uint8_t block) -{ - int rv; - uint32_t lock; - - if (otp_get_protect(block)) - return EC_SUCCESS; - - lock = REG32(STM32_OTP_LOCK(block)); - lock &= ~STM32_OPT_LOCK_MASK(block); - rv = crec_flash_physical_write(STM32_OTP_LOCK(block) - - CONFIG_PROGRAM_MEMORY_BASE, - sizeof(uint32_t), (char *)&lock); - if (rv) - return rv; - else - return EC_SUCCESS; -} - -const char *otp_read_serial(void) -{ - int i; - - for (i = 0; i < OTP_SERIAL_BLOCK_SIZE; i++) { - if (OTP_SERIAL_ADDR[i] != -1) - return (char *)OTP_SERIAL_ADDR; - } - return NULL; -} - -int otp_write_serial(const char *serialno) -{ - int i, ret; - char otp_serial[CONFIG_SERIALNO_LEN]; - - if (otp_get_protect(OTP_SERIAL_BLOCK)) - return EC_ERROR_ACCESS_DENIED; - - /* Copy in serialno. */ - for (i = 0; i < CONFIG_SERIALNO_LEN - 1; i++) { - otp_serial[i] = serialno[i]; - if (serialno[i] == 0) - break; - } - for (; i < CONFIG_SERIALNO_LEN; i++) - otp_serial[i] = 0; - - ret = otp_write(OTP_SERIAL_BLOCK, OTP_SERIAL_BLOCK_SIZE, otp_serial); - if (ret == EC_SUCCESS) - return otp_set_protect(OTP_SERIAL_BLOCK); - else - return ret; -} -#endif diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c deleted file mode 100644 index 508745199f..0000000000 --- a/chip/stm32/power_led.c +++ /dev/null @@ -1,162 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Keyboard power button LED state machine. - * - * This sets up TIM_POWER_LED to drive the power button LED so that the duty - * cycle can range from 0-100%. When the lid is closed or turned off, then the - * PWM is disabled and the GPIO is reconfigured to minimize leakage voltage. - * - * In suspend mode, duty cycle transitions progressively slower from 0% - * to 100%, and progressively faster from 100% back down to 0%. This - * results in a breathing effect. It takes about 2sec for a full cycle. - */ - -#include "clock.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "power_led.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */ -#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */ -#define LED_STEP_PERCENT 4 /* Incremental value of each step */ - -static enum powerled_state led_state = POWERLED_STATE_ON; -static int power_led_percent = 100; - -void powerled_set_state(enum powerled_state new_state) -{ - led_state = new_state; - /* Wake up the task */ - task_wake(TASK_ID_POWERLED); -} - -static void power_led_set_duty(int percent) -{ - ASSERT((percent >= 0) && (percent <= 100)); - power_led_percent = percent; - pwm_set_duty(PWM_CH_POWER_LED, percent); -} - -static void power_led_use_pwm(void) -{ - pwm_enable(PWM_CH_POWER_LED, 1); - power_led_set_duty(100); -} - -static void power_led_manual_off(void) -{ - pwm_enable(PWM_CH_POWER_LED, 0); - - /* - * Reconfigure GPIO as a floating input. Alternatively we could - * configure it as an open-drain output and set it to high impedance, - * but reconfiguring as an input had better results in testing. - */ - gpio_config_module(MODULE_POWER_LED, 0); -} - -/** - * Return the timeout period (in us) for the current step. - */ -static int power_led_step(void) -{ - int state_timeout = 0; - static enum { DOWN = -1, UP = 1 } dir = UP; - - if (0 == power_led_percent) { - dir = UP; - state_timeout = LED_HOLD_TIME; - } else if (100 == power_led_percent) { - dir = DOWN; - state_timeout = LED_HOLD_TIME; - } else { - /* - * Decreases timeout as duty cycle percentage approaches - * 0%, increase as it approaches 100%. - */ - state_timeout = LED_STATE_TIMEOUT_MIN + - LED_STATE_TIMEOUT_MIN * (power_led_percent / 33); - } - - /* - * The next duty cycle will take effect after the timeout has - * elapsed for this duty cycle and the power LED task calls this - * function again. - */ - power_led_set_duty(power_led_percent); - power_led_percent += dir * LED_STEP_PERCENT; - - return state_timeout; -} - -void power_led_task(void) -{ - while (1) { - int state_timeout = -1; - - switch (led_state) { - case POWERLED_STATE_ON: - /* - * "ON" implies driving the LED using the PWM with a - * duty duty cycle of 100%. This produces a softer - * brightness than setting the GPIO to solid ON. - */ - power_led_use_pwm(); - power_led_set_duty(100); - state_timeout = -1; - break; - case POWERLED_STATE_OFF: - /* Reconfigure GPIO to disable the LED */ - power_led_manual_off(); - state_timeout = -1; - break; - case POWERLED_STATE_SUSPEND: - /* Drive using PWM with variable duty cycle */ - power_led_use_pwm(); - state_timeout = power_led_step(); - break; - default: - break; - } - - task_wait_event(state_timeout); - } -} - -#define CONFIG_CMD_POWERLED -#ifdef CONFIG_CMD_POWERLED -static int command_powerled(int argc, char **argv) -{ - enum powerled_state state; - - if (argc != 2) - return EC_ERROR_INVAL; - - if (!strcasecmp(argv[1], "off")) - state = POWERLED_STATE_OFF; - else if (!strcasecmp(argv[1], "on")) - state = POWERLED_STATE_ON; - else if (!strcasecmp(argv[1], "suspend")) - state = POWERLED_STATE_SUSPEND; - else - return EC_ERROR_INVAL; - - powerled_set_state(state); - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(powerled, command_powerled, - "[off | on | suspend]", - "Change power LED state"); -#endif diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c deleted file mode 100644 index 0b339399c9..0000000000 --- a/chip/stm32/pwm.c +++ /dev/null @@ -1,164 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* PWM control module for STM32 */ - -#include "clock.h" -#include "clock-f.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "pwm.h" -#include "pwm_chip.h" -#include "registers.h" -#include "system.h" -#include "util.h" - -/* Bitmap of currently active PWM channels. 1 bit per channel. */ -static uint32_t using_pwm; - -void pwm_set_duty(enum pwm_channel ch, int percent) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - - ASSERT((percent >= 0) && (percent <= 100)); - tim->ccr[pwm->channel] = percent; -} - -int pwm_get_duty(enum pwm_channel ch) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - return tim->ccr[pwm->channel]; -} - -static void pwm_configure(enum pwm_channel ch) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - volatile unsigned *ccmr = NULL; - /* Default frequency = 100 Hz */ - int frequency = pwm->frequency ? pwm->frequency : 100; - uint16_t ccer; - - if (using_pwm & BIT(ch)) - return; - - /* Enable timer */ - __hw_timer_enable_clock(pwm->tim.id, 1); - - /* Disable counter during setup */ - tim->cr1 = 0x0000; - - /* - * Timer clock / PSC determines how fast the counter operates. - * ARR determines the wave period, CCRn determines duty cycle. - * Thus, frequency = timer_freq / PSC / ARR. so: - * - * frequency = timer_freq / (timer_freq/10000 + 1) / (99 + 1) = 100 Hz. - */ - tim->psc = clock_get_timer_freq() / (frequency * 100) - 1; - tim->arr = 99; - - if (pwm->channel <= 2) /* Channel ID starts from 1 */ - ccmr = &tim->ccmr1; - else - ccmr = &tim->ccmr2; - - /* Output, PWM mode 1, preload enable */ - if (pwm->channel & 0x1) - *ccmr = (6 << 4) | BIT(3); - else - *ccmr = (6 << 12) | BIT(11); - - /* Output enable. Set active high/low. */ - if (pwm->flags & PWM_CONFIG_ACTIVE_LOW) - ccer = 3 << (pwm->channel * 4 - 4); - else - ccer = 1 << (pwm->channel * 4 - 4); - - /* Enable complementary output, if present. */ - if (pwm->flags & PWM_CONFIG_COMPLEMENTARY_OUTPUT) - ccer |= (ccer << 2); - - tim->ccer = ccer; - - /* - * Main output enable. - * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't - * harmful on STM32L. - */ - tim->bdtr |= BIT(15); - - /* Generate update event to force loading of shadow registers */ - tim->egr |= 1; - - /* Enable auto-reload preload, start counting */ - tim->cr1 |= BIT(7) | BIT(0); - - atomic_or(&using_pwm, 1 << ch); - - /* Prevent sleep */ - disable_sleep(SLEEP_MASK_PWM); -} - -static void pwm_disable(enum pwm_channel ch) -{ - const struct pwm_t *pwm = pwm_channels + ch; - timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - - if ((using_pwm & BIT(ch)) == 0) - return; - - /* Main output disable */ - tim->bdtr &= ~BIT(15); - - /* Disable counter */ - tim->cr1 &= ~0x1; - - /* Disable timer clock */ - __hw_timer_enable_clock(pwm->tim.id, 0); - - /* Allow sleep */ - enable_sleep(SLEEP_MASK_PWM); - - atomic_clear_bits(&using_pwm, 1 << ch); - - /* Unless another PWM is active... Then prevent sleep */ - if (using_pwm) - disable_sleep(SLEEP_MASK_PWM); -} - -void pwm_enable(enum pwm_channel ch, int enabled) -{ - if (enabled) - pwm_configure(ch); - else - pwm_disable(ch); -} - -int pwm_get_enabled(enum pwm_channel ch) -{ - return using_pwm & BIT(ch); -} - -static void pwm_reconfigure(enum pwm_channel ch) -{ - atomic_clear_bits(&using_pwm, 1 << ch); - pwm_configure(ch); -} - -/** - * Handle clock frequency change - */ -static void pwm_freq_change(void) -{ - int i; - for (i = 0; i < PWM_CH_COUNT; ++i) - if (pwm_get_enabled(i)) - pwm_reconfigure(i); -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, pwm_freq_change, HOOK_PRIO_DEFAULT); diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h deleted file mode 100644 index baa793090a..0000000000 --- a/chip/stm32/pwm_chip.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* STM32-specific PWM module for Chrome EC */ - -#ifndef __CROS_EC_PWM_CHIP_H -#define __CROS_EC_PWM_CHIP_H - -/* Data structure to define PWM channels. */ -struct pwm_t { - /* - * Timer powering the PWM channel. Must use STM32_TIM(x) to - * initialize - */ - struct { - int id; - uintptr_t base; - } tim; - /* Channel ID within the timer */ - int channel; - /* PWM channel flags. See include/pwm.h */ - uint32_t flags; - /* PWM frequency (Hz) */ - int frequency; -}; - -extern const struct pwm_t pwm_channels[]; - -/* Macro to fill in both timer ID and register base */ -#define STM32_TIM(x) {x, STM32_TIM_BASE(x)} - -/* Plain ID mapping for readability */ -#define STM32_TIM_CH(x) (x) - -#endif /* __CROS_EC_PWM_CHIP_H */ diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h deleted file mode 100644 index ee4963777b..0000000000 --- a/chip/stm32/registers-stm32f0.h +++ /dev/null @@ -1,890 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F0 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F03X - * - STM32F05X - * - STM32F070 - * - STM32F07X - * - STM32F09X - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_WAKEUP 2 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 3 -#define STM32_IRQ_RCC 4 -#define STM32_IRQ_EXTI0_1 5 -#define STM32_IRQ_EXTI2_3 6 -#define STM32_IRQ_EXTI4_15 7 -#define STM32_IRQ_TSC 8 -#define STM32_IRQ_DMA_CHANNEL_1 9 -#define STM32_IRQ_DMA_CHANNEL_2_3 10 -#define STM32_IRQ_DMA_CHANNEL_4_7 11 -#define STM32_IRQ_ADC_COMP 12 -#define STM32_IRQ_TIM1_BRK_UP_TRG 13 -#define STM32_IRQ_TIM1_CC 14 -#define STM32_IRQ_TIM2 15 -#define STM32_IRQ_TIM3 16 -#define STM32_IRQ_TIM6_DAC 17 -#define STM32_IRQ_TIM7 18 -#define STM32_IRQ_TIM14 19 -#define STM32_IRQ_TIM15 20 -#define STM32_IRQ_TIM16 21 -#define STM32_IRQ_TIM17 22 -#define STM32_IRQ_I2C1 23 -#define STM32_IRQ_I2C2 24 -#define STM32_IRQ_SPI1 25 -#define STM32_IRQ_SPI2 26 -#define STM32_IRQ_USART1 27 -#define STM32_IRQ_USART2 28 -#define STM32_IRQ_USART3_4 29 -#define STM32_IRQ_CEC_CAN 30 -#define STM32_IRQ_USB 31 -/* aliases for easier code sharing */ -#define STM32_IRQ_COMP STM32_IRQ_ADC_COMP -#define STM32_IRQ_USB_LP STM32_IRQ_USB - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - -#define STM32_COMP_BASE 0x40010000 - -#define STM32_DBGMCU_BASE 0x40015800 - -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40022000 - -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFF800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40021000 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWD_PVD_LS_MASK (0x07 << 5) -#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5) -#define STM32_PWR_PVDE BIT(4) - -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_DACEN BIT(29) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) -/* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) -/* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ - -#define STM32_RCC_HB_DMA1 BIT(0) -/* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 20 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_PVD_EVENT BIT(16) -#define EXTI_RTC_ALR_EVENT BIT(17) -#define EXTI_COMP2_EVENT BIT(22) - -/* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_ISR_ADRDY BIT(0) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_IER_AWDIE BIT(7) -#define STM32_ADC_IER_OVRIE BIT(4) -#define STM32_ADC_IER_EOSEQIE BIT(3) -#define STM32_ADC_IER_EOCIE BIT(2) -#define STM32_ADC_IER_EOSMPIE BIT(1) -#define STM32_ADC_IER_ADRDYIE BIT(0) - -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADDIS BIT(1) -#define STM32_ADC_CR_ADCAL BIT(31) -#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) -/* Analog watchdog channel selection */ -#define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26) -#define STM32_ADC_CFGR1_AWDEN BIT(23) -#define STM32_ADC_CFGR1_AWDSGL BIT(22) -/* Selects single vs continuous */ -#define STM32_ADC_CFGR1_CONT BIT(13) -/* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC_CFGR1_OVRMOD BIT(12) -/* External trigger polarity selection */ -#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) -#define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10) -#define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10) -#define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10) -#define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10) -/* External trigger selection */ -#define STM32_ADC_CFGR1_TRG0 (0 << 6) -#define STM32_ADC_CFGR1_TRG1 (1 << 6) -#define STM32_ADC_CFGR1_TRG2 (2 << 6) -#define STM32_ADC_CFGR1_TRG3 (3 << 6) -#define STM32_ADC_CFGR1_TRG4 (4 << 6) -#define STM32_ADC_CFGR1_TRG5 (5 << 6) -#define STM32_ADC_CFGR1_TRG6 (6 << 6) -#define STM32_ADC_CFGR1_TRG7 (7 << 6) -#define STM32_ADC_CFGR1_TRG_MASK (7 << 6) -/* Selects circular vs one-shot */ -#define STM32_ADC_CFGR1_DMACFG BIT(1) -#define STM32_ADC_CFGR1_DMAEN BIT(0) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) -/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308) - -/* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) - -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) - -#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) - -#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, -#if !defined(CHIP_VARIANT_STM32F03X) && !defined(CHIP_VARIANT_STM32F05X) - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH6, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH7, - - /* Only DMA1 (with 7 channels) is present on STM32L151x */ - STM32_DMAC_COUNT = 7, - -#else /* stm32f03x and stm32f05x have only 5 channels */ - STM32_DMAC_COUNT = 5, -#endif -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) - -#ifdef CHIP_VARIANT_STM32F09X -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) -#else -#define STM32_DMA_REGS(channel) STM32_DMA1_REGS -#endif - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h deleted file mode 100644 index b7e3cfc8af..0000000000 --- a/chip/stm32/registers-stm32f3.h +++ /dev/null @@ -1,1013 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F3 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F373 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_USB_HP 74 -#define STM32_IRQ_USB_LP 75 -#else -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 -#endif - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_COMP 64 -#else -#define STM32_IRQ_COMP 22 -#endif - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - -#define STM32_COMP_BASE 0x40010000 - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40022000 - -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFF800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40021000 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) -/* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) -/* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ - -#define STM32_RCC_HB_DMA1 BIT(0) -/* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 64 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) -#endif - -/* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) - -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) - -#define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_OCR (5 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM2_IC4 (4 << 24) -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_COMP_CMP2OUTSEL_TIM4_OCR (3 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM4_IC1 (2 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM16_BRK (1 << 24) -#else -#define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) -#define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) -#endif -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) - -#ifdef CHIP_VARIANT_STM32F373 -#define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM5_IC4 (6 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (3 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (2 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM15_BRK (1 << 8) -#else -#define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_OCR (5 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM2_IC4 (4 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) -#define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) -#endif -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, -#ifdef CHIP_VARIANT_STM32F373 - STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, - STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, - STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - - STM32_DMAC_COUNT = 10, -#else - STM32_DMAC_SPI2_RX = STM32_DMAC_CH6, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH7, - - /* Only DMA1 (with 7 channels) is present on STM32L151x */ - STM32_DMAC_COUNT = 7, -#endif -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h deleted file mode 100644 index 503a60cc64..0000000000 --- a/chip/stm32/registers-stm32f4.h +++ /dev/null @@ -1,1132 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F4 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F411 - * - STM32F412 - * - STM32F41X - * - STM32F446 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#if defined(CHIP_VARIANT_STM32F412) -#define STM32_IRQ_TIM9 24 /* STM32F412 only */ -#else -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#endif -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - -#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F412) -#define CHIP_VARIANT_STM32F41X -#endif - -/* - * STM32F4 introduces a concept of DMA stream to allow - * fine allocation of a stream to a channel. - */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) -/* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -#if defined(CHIP_VARIANT_STM32F446) -/* Required or recommended clocks for stm32f446 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 42000000 -#define STM32F4_USB_REQ 48000000 -#define STM32F4_VCO_CLOCK 336000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK -#define STM32F4_PLLP_DIV 4 -#define STM32F4_AHB_PRE 0x8 -#define STM32F4_APB1_PRE 0x0 -#define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) -/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 - -#elif defined(CHIP_VARIANT_STM32F412) -/* Required or recommended clocks for stm32f412 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 -#define STM32F4_USB_REQ 48000000 -#define STM32F4_VCO_CLOCK 384000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 4 -#define STM32F4_AHB_PRE 0x0 -#define STM32F4_APB1_PRE 0x4 -#define STM32F4_APB2_PRE 0x4 -#define STM32_FLASH_ACR_LATENCY (3 << 0) -/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 - -#elif defined(CHIP_VARIANT_STM32F411) -/* Required or recommended clocks for stm32f411 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 -#define STM32F4_USB_REQ 48000000 -#define STM32F4_VCO_CLOCK 384000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK -#define STM32F4_PLLP_DIV 4 -#define STM32F4_AHB_PRE 0x8 -#define STM32F4_APB1_PRE 0x0 -#define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) -/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 - -#elif defined(CHIP_VARIANT_STM32F76X) -/* Required or recommended clocks for stm32f767/769 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ -#define STM32F4_VCO_CLOCK 360000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ -#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ -#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) -/* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 - -#else -#error "No valid clocks defined" -#endif - -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) -/* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) -/* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) -/* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) - -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) -/* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) -/* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -/* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) -/* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) -/* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) -/* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) - -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) - -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) - -/* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM8 BIT(1) -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - - -/* Peripheral bits for RCC_APB/AHB regs */ -#define STM32_RCC_PB2_USART1 BIT(4) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG (BIT(30)|BIT(29)) -#define RESET_CAUSE_SFT BIT(28) -#define RESET_CAUSE_POR BIT(27) -#define RESET_CAUSE_PIN BIT(26) -#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ - BIT(27)|BIT(26)|BIT(25)) -#define RESET_CAUSE_RMVF BIT(24) -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define RESET_CAUSE_SBF BIT(1) -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF_CLR BIT(3) - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) - -/* --- Debug --- */ - -#define STM32_DBGMCU_CR_SLEEP BIT(0) -#define STM32_DBGMCU_CR_STOP BIT(1) -#define STM32_DBGMCU_CR_STBY BIT(2) -#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define STM32_DBGMCU_CR_TRACE_EN BIT(5) -#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6)|BIT(7)) -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) -#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) -#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) -#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) -#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) -#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) -#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6) -#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7) -#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8) -#define STM32_DBGMCU_APB1FZ_RTC BIT(10) -#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) -#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) -#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) -#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) -#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23) -#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24) -#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25) -#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) -#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0) -#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1) -#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16) -#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17) -#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ - FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define FLASH_OPTCR_RDP_SHIFT (8) -#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT) -/* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 -#define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * Named channel to respect older interface, but a stream can serve - * any channels, as long as they are in the same DMA controller. - * - * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMA1_STREAM0 = 0, - STM32_DMA1_STREAM1 = 1, - STM32_DMA1_STREAM2 = 2, - STM32_DMA1_STREAM3 = 3, - STM32_DMA1_STREAM4 = 4, - STM32_DMA1_STREAM5 = 5, - STM32_DMA1_STREAM6 = 6, - STM32_DMA1_STREAM7 = 7, - STM32_DMAS_COUNT = 8, - STM32_DMA2_STREAM0 = 8, - STM32_DMA2_STREAM1 = 9, - STM32_DMA2_STREAM2 = 10, - STM32_DMA2_STREAM3 = 11, - STM32_DMA2_STREAM4 = 12, - STM32_DMA2_STREAM5 = 13, - STM32_DMA2_STREAM6 = 14, - STM32_DMA2_STREAM7 = 15, - - STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7, - STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, - STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, -#ifdef CHIP_VARIANT_STM32F41X - STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6, - STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX, - STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX, -#endif - -#ifdef CHIP_VARIANT_STM32F41X - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2, -#else - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1, -#endif - - STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5, - STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2, - - /* Legacy naming for spi_master.c */ - STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */ - STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ - STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ - STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ - STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ - STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ - STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */ - STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */ -}; - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -#define STM32_DMAS_TOTAL_COUNT 16 - -/* Registers for a single stream of a DMA controller */ -struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ -}; - -/* Always use stm32_dma_stream_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_stream stm32_dma_stream_t; - -/* Common code and header file must use this */ -typedef stm32_dma_stream_t dma_chan_t; -struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; - stm32_dma_stream_t stream[STM32_DMAS_COUNT]; -}; - - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) - -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) - -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ - (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) -#define STM32_DMA_CH_GETBITS(channel, val) \ - (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h deleted file mode 100644 index 2245d6775f..0000000000 --- a/chip/stm32/registers-stm32f7.h +++ /dev/null @@ -1,1082 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32F7 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32F76X - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - -/* - * STM32F4 introduces a concept of DMA stream to allow - * fine allocation of a stream to a channel. - */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -#ifdef CHIP_VARIANT_STM32F76X -/* Required or recommended clocks for stm32f767/769 */ -#define STM32F4_PLL_REQ 2000000 -#define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ -#define STM32F4_VCO_CLOCK 360000000 -#define STM32F4_HSI_CLOCK 16000000 -#define STM32F4_LSI_CLOCK 32000 -#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ -#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ -#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) -#else -#error "No valid clocks defined" -#endif - -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) -/* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) -/* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) -/* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) - -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) -/* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) -/* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -/* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) -/* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) -/* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) -/* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) - -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) - -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) -/* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ - FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define STM32_FLASH_RDP_MASK (0xFF << 8) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 -#define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * Named channel to respect older interface, but a stream can serve - * any channels, as long as they are in the same DMA controller. - * - * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMA1_STREAM0 = 0, - STM32_DMA1_STREAM1 = 1, - STM32_DMA1_STREAM2 = 2, - STM32_DMA1_STREAM3 = 3, - STM32_DMA1_STREAM4 = 4, - STM32_DMA1_STREAM5 = 5, - STM32_DMA1_STREAM6 = 6, - STM32_DMA1_STREAM7 = 7, - STM32_DMAS_COUNT = 8, - STM32_DMA2_STREAM0 = 8, - STM32_DMA2_STREAM1 = 9, - STM32_DMA2_STREAM2 = 10, - STM32_DMA2_STREAM3 = 11, - STM32_DMA2_STREAM4 = 12, - STM32_DMA2_STREAM5 = 13, - STM32_DMA2_STREAM6 = 14, - STM32_DMA2_STREAM7 = 15, - - STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7, - STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, - STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, - STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6, - STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART2_TX = STM32_DMAS_USART2_TX, - STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX, - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM2, - STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5, - STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2, - - /* Legacy naming for spi_master.c */ - STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */ - STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ - STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ - STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ - STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ - STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ - STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */ - STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */ -}; - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -#define STM32_DMAS_TOTAL_COUNT 16 - -/* Registers for a single stream of a DMA controller */ -struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ -}; - -/* Always use stm32_dma_stream_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_stream stm32_dma_stream_t; - -/* Common code and header file must use this */ -typedef stm32_dma_stream_t dma_chan_t; -struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; - stm32_dma_stream_t stream[STM32_DMAS_COUNT]; -}; - - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) - -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) - -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ - (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) -#define STM32_DMA_CH_GETBITS(channel, val) \ - (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h deleted file mode 100644 index e3a73a0fe9..0000000000 --- a/chip/stm32/registers-stm32g4.h +++ /dev/null @@ -1,1506 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32G4 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32G431 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_ADC1 18 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 -#define STM32_IRQ_FDCAN_IT0 21 -#define STM32_IRQ_FDCAN_IT1 22 -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM15 24 -#define STM32_IRQ_TIM16 25 -#define STM32_IRQ_TIM17 26 -#define STM32_IRQ_TIM1_CC 27 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 -#define STM32_IRQ_TIM8_BREAK 43 -#define STM32_IRQ_TIM8_UP 44 -#define STM32_IRQ_TIM8_TRG_COM 45 -#define STM32_IRQ_TIM8_CC 46 -#define STM32_IRQ_LPTIM1 49 -#define STM32_IRQ_SPI3 51 -#define STM32_IRQ_USART4 52 -#define STM32_IRQ_TIM6_DAC 54 -#define STM32_IRQ_TIM7 55 -#define STM32_IRQ_DMA2_CHANNEL1 56 -#define STM32_IRQ_DMA2_CHANNEL2 57 -#define STM32_IRQ_DMA2_CHANNEL3 58 -#define STM32_IRQ_DMA2_CHANNEL4 59 -#define STM32_IRQ_DMA2_CHANNEL5 60 -#define STM32_IRQ_UCPD1 63 -#define STM32_IRQ_COMP_1_2_3 64 -#define STM32_IRQ_COMP_4 65 -#define STM32_IRQ_CRS 75 -#define STM32_IRQ_SAI1 76 -#define STM32_IRQ_FPU 81 -#define STM32_IRQ_RNG 90 -#define STM32_IRQ_LPUART 91 -#define STM32_IRQ_I2C3_EV 92 -#define STM32_IRQ_I2C3_ER 93 -#define STM32_IRQ_DMAMUX_OVR 94 -#define STM32_IRQ_DMA1_CHANNEL8 96 -#define STM32_IRQ_DMA2_CHANNEL6 97 -#define STM32_IRQ_DMA2_CHANNEL7 98 -#define STM32_IRQ_DMA2_CHANNEL8 99 -#define STM32_IRQ_CORDIC 100 -#define STM32_IRQ_FMAC 101 - -/* LPUART gets accessed as UART9 in STM32 uart driver */ -#define STM32_IRQ_USART9 STM32_IRQ_LPUART - -/* To simplify code generation, define DMA channel 13 - 14 */ -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - -#ifdef CHIP_VARIANT_STM32G431 -#define CHIP_VARIANT_STM32G431X -#endif - -/* Embedded flash option bytes base address */ -#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL -#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL - -/* Peripheral base addresses */ -#define STM32_PERIPH_BASE (0x40000000UL) -/* Peripheral memory map */ -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL) -#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL) - -/* APB1 peripherals */ -#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset) -#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL) -#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL) -#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL) -#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL) -#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL) -#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL) -#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL) -#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL) -#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL) -#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL) -#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL) -#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL) -#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL) -#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL) -#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL) -#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL) -#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL) -/* USB_IP Peripheral Registers base address */ -#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL) -/* USB_IP Packet Memory Area base address */ -#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL) -#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL) -/* FDCAN configuration registers base address */ -#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL) -#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL) -#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL) -#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL) -#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL) -#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) -/* UART9 is used as link to LPUART in STM32 uart.c implementation */ -#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL) -#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) -#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL) -#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL) - -/* APB2 peripherals */ -#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset) -#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL) -#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL) -#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL) -#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL) -#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL) -#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL) -#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL) -#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL) -#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL) -#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL) -#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL) -#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL) -#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL) -#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL) -#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL) -#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL) -#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL) -#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL) -#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL) -#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) - -/* AHB1 peripherals */ -#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset) -#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL) -#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL) -#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL) -#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL) -#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL) -#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL) -#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL) -#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL) - -#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset) -#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL) -#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL) -#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL) -#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL) -#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL) -#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL) - -#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset) -#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL) -#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL) -#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL) -#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL) -#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL) -#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL) - -#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset) -#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL) -#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL) -#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL) -#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL) -#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL) -#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL) -#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL) -#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL) -#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL) -#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL) -#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL) -#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL) -#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL) -#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL) -#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL) -#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL) -#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL) -#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL) - -/* AHB2 peripherals */ -#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset) -#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL) -#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL) -#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL) -#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL) -#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL) -#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL) -#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL) -#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL) -#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL) -#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL) -#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL) -#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL) -#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL) -#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL) - -#define STM32_UNIQUE_ID_BASE 0x1FFF7590 -#define STM32_DBGMCU_BASE 0xE0042000 - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- UCPD --- */ -#define STM32_UCPD_REG(port, offset) \ - REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset))) - -#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00) -#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04) -#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c) -#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10) -#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14) -#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18) -#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c) -#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20) -#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24) -#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28) -#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c) -#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30) -#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34) -#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38) - -/* --- UCPD CFGR1 Bit Definitions --- */ -#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0 -#define STM32_UCPD_CFGR1_HBITCLKD_MASK ((0x3f) << \ - (STM32_UCPD_CFGR1_HBITCLKD_SHIFT)) -#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_HBITCLKD_SHIFT) -#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6 -#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << \ - (STM32_UCPD_CFGR1_IFRGAP_SHIFT)) -#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_IFRGAP_SHIFT) -#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11 -#define STM32_UCPD_CFGR1_TRANSWIN_MASK ((0x1f) << \ - (STM32_UCPD_CFGR1_TRANSWIN_SHIFT)) -#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_TRANSWIN_SHIFT) -#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17 -#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << \ - STM32_UCPD_CFGR1_PSC_CLK_SHIFT) -#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_PSC_CLK_SHIFT) -#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20 -#define STM32_UCPD_CFGR1_RXORDSETEN_MASK ((0x1ff) << \ - STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) -#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) -#define STM32_UCPD_CFGR1_TXDMAEN BIT(29) -#define STM32_UCPD_CFGR1_RXDMAEN BIT(30) -#define STM32_UCPD_CFGR1_UCPDEN BIT(31) - -/* --- UCPD CFGR2 Bit Definitions --- */ -#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0) -#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1) -#define STM32_UCPD_CFGR2_FORCECLK BIT(2) -#define STM32_UCPD_CFGR2_WUPEN BIT(3) - -/* --- UCPD CR Bit Definitions --- */ -#define STM32_UCPD_CR_TXMODE_SHIFT 0 -#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << \ - (STM32_UCPD_CR_TXMODE_SHIFT)) -#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT) -#define STM32_UCPD_CR_TXSEND BIT(2) -#define STM32_UCPD_CR_TXHRST BIT(3) -#define STM32_UCPD_CR_RXMODE BIT(4) -#define STM32_UCPD_CR_PHYRXEN BIT(5) -#define STM32_UCPD_CR_PHYCCSEL BIT(6) -#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7 -#define STM32_UCPD_CR_ANASUBMODE_MASK ((0x3) << \ - (STM32_UCPD_CR_ANASUBMODE_SHIFT)) -#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << \ - STM32_UCPD_CR_ANASUBMODE_SHIFT) -#define STM32_UCPD_CR_ANAMODE BIT(9) -#define STM32_UCPD_CR_CCENABLE_SHIFT 10 -#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << \ - (STM32_UCPD_CR_CCENABLE_SHIFT)) -#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << \ - STM32_UCPD_CR_CCENABLE_SHIFT) -#define STM32_UCPD_CR_FRSRXEN BIT(16) -#define STM32_UCPD_CR_FRSTX BIT(17) -#define STM32_UCPD_CR_RDCH BIT(18) -#define STM32_UCPD_CR_CC1TCDIS BIT(20) -#define STM32_UCPD_CR_CC2TCDIS BIT(21) - -/* TX mode message types */ -#define STM32_UCPD_CR_TXMODE_DEF 0 -#define STM32_UCPD_CR_TXMODE_CBL_RST 1 -#define STM32_UCPD_CR_TXMODE_BIST 2 - -/* --- UCPD IMR Bit Definitions --- */ -#define STM32_UCPD_IMR_TXISIE BIT(0) -#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1) -#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2) -#define STM32_UCPD_IMR_TXMSGABTIE BIT(3) -#define STM32_UCPD_IMR_HRSTDISCIE BIT(4) -#define STM32_UCPD_IMR_HRSTSENTIE BIT(5) -#define STM32_UCPD_IMR_TXUNDIE BIT(6) -#define STM32_UCPD_IMR_RXNEIE BIT(8) -#define STM32_UCPD_IMR_RXORDDETIE BIT(9) -#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10) -#define STM32_UCPD_IMR_RXOVRIE BIT(11) -#define STM32_UCPD_IMR_RXMSGENDIE BIT(12) -#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14) -#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15) -#define STM32_UCPD_IMR_FRSEVTIE BIT(20) - -/* --- UCPD SR Bit Definitions --- */ -#define STM32_UCPD_SR_TXIS BIT(0) -#define STM32_UCPD_SR_TXMSGDISC BIT(1) -#define STM32_UCPD_SR_TXMSGSENT BIT(2) -#define STM32_UCPD_SR_TXMSGABT BIT(3) -#define STM32_UCPD_SR_HRSTDISC BIT(4) -#define STM32_UCPD_SR_HRSTSENT BIT(5) -#define STM32_UCPD_SR_TXUND BIT(6) -#define STM32_UCPD_SR_RXNE BIT(8) -#define STM32_UCPD_SR_RXORDDET BIT(9) -#define STM32_UCPD_SR_RXHRSTDET BIT(10) -#define STM32_UCPD_SR_RXOVR BIT(11) -#define STM32_UCPD_SR_RXMSGEND BIT(12) -#define STM32_UCPD_SR_RXERR BIT(13) -#define STM32_UCPD_SR_TYPECEVT1 BIT(14) -#define STM32_UCPD_SR_TYPECEVT2 BIT(15) -#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16 -#define STM32_UCPD_SR_VSTATE_CC1_MASK ((0x3) << \ - (STM32_UCPD_SR_VSTATE_CC1_SHIFT)) -#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << \ - STM32_UCPD_SR_VSTATE_CC1_SHIFT) -#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18 -#define STM32_UCPD_SR_VSTATE_CC2_MASK ((0x3) << \ - (STM32_UCPD_SR_VSTATE_CC2_SHIFT)) -#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << \ - STM32_UCPD_SR_VSTATE_CC2_SHIFT) -#define STM32_UCPD_SR_FRSEVT BIT(20) - -#define STM32_UCPD_SR_VSTATE_OPEN 3 -#define STM32_UCPD_SR_VSTATE_RA 0 - -/* --- UCPD ICR Bit Definitions --- */ -#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1) -#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2) -#define STM32_UCPD_ICR_TXMSGABTCF BIT(3) -#define STM32_UCPD_ICR_HRSTDISCCF BIT(4) -#define STM32_UCPD_ICR_HRSTSENTCF BIT(5) -#define STM32_UCPD_ICR_TXUNDCF BIT(6) -#define STM32_UCPD_ICR_RXORDDETCF BIT(9) -#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10) -#define STM32_UCPD_ICR_RXOVRCF BIT(11) -#define STM32_UCPD_ICR_RXMSGENDCF BIT(12) -#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14) -#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15) -#define STM32_UCPD_ICR_FRSEVTCF BIT(20) - - -/* --- UCPD TX_ORDSETR Bit Definitions --- */ -#define STM32_UCPD_TX_ORDSETR_SHIFT 0 -#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << \ - (STM32_UCPD_TX_ORDSETR_SHIFT)) -#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT) - -/* --- UCPD TX_PAYSZR Bit Definitions --- */ -#define STM32_UCPD_TX_PAYSZR_SHIFT 0 -#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << \ - (STM32_UCPD_TX_PAYSZR_SHIFT)) -#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT) - -/* --- UCPD TXDR Bit Definitions --- */ -#define STM32_UCPD_TXDR_SHIFT 0 -#define STM32_UCPD_TXDR_MASK ((0xff) << \ - (STM32_UCPD_TXDR_SHIFT)) -#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT) - -/* --- UCPD RX_ORDSETR Bit Definitions --- */ -#define STM32_UCPD_RXORDSETR_SHIFT 0 -#define STM32_UCPD_RXORDSETR_MASK ((0x7) << \ - (STM32_UCPD_RXORDSETR_SHIFT)) -#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT) -#define STM32_UCPD_RXSOP3OF4 BIT(3) -#define STM32_UCPD_RXSOPKINVALID_SHIFT 4 -#define STM32_UCPD_RXSOPKINVALID_MASK ((0x7) << \ - (STM32_UCPD_RXSOPKINVALID_SHIFT)) -#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << \ - STM32_UCPD_RXSOPKINVALID_SHIFT) - -/* --- UCPD RX_PAYSZR Bit Definitions --- */ -#define STM32_UCPD_RX_PAYSZR_SHIFT 0 -#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << \ - (STM32_UCPD_RX_PAYSZR_SHIFT)) -#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT) - -/* --- UCPD TXDR Bit Definitions --- */ -#define STM32_UCPD_RXDR_SHIFT 0 -#define STM32_UCPD_RXDR_MASK ((0xff) << \ - (STM32_UCPD_RXDR_SHIFT)) -#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT) - - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) - -/* --- USART bit definitions -- */ -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) - - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_I2C3 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_LPUART 0xC -#define GPIO_ALT_SAI1 0xD -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset))) - -#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00)) -#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04)) -#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08)) -#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C)) -#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10)) -#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14)) -#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18)) -#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C)) -#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20)) -#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24)) -#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28)) - -/* --- I2C CR1 Bit Definitions --- */ -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) - -/* --- I2C CR2 Bit Definitions --- */ -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) - -/* --- I2C ISR Bit Definitions --- */ -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) - -/* --- I2C ICR Bit Definitions --- */ -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 - -/* --- I2C TIMINGR bit Definitions --- */ -#define STM32_I2C_TIMINGR_SCLL_OFF 0 -#define STM32_I2C_TIMINGR_SCLH_OFF 8 -#define STM32_I2C_TIMINGR_SDADEL_OFF 16 -#define STM32_I2C_TIMINGR_SCLDEL_OFF 20 -#define STM32_I2C_TIMINGR_PRESC_OFF 28 - -/* --- Power / Reset / Clocks --- */ - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) -#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) - -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 -#define STM32_RCC_AHBENR STM32_RCC_APB1ENR - -/* --- RCC CR Bit Definitions --- */ -#define STM32_RCC_CR_HSION BIT(8) -#define STM32_RCC_CR_HSIRDY BIT(10) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) - -/* --- RCC PLLCFGR Bit Definitions --- */ -#define PLLCFGR_PLLSRC_OFF 0 -#define PLLCFGR_PLLSRC(val) (((val) & 0x3) << PLLCFGR_PLLSRC_OFF) -#define PLLCFGR_PLLSRC_HSI 2 -#define PLLCFGR_PLLSRC_HSE 3 -/* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 4 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) -/* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 8 -#define PLLCFGR_PLLN(val) (((val) & 0x7f) << PLLCFGR_PLLN_OFF) -#define PLLCFGR_PLLQ_EN BIT(20) -#define PLLCFGR_PLLQ_OFF 21 -#define PLLCFGR_PLLQ(val) (((val) & 0x3) << PLLCFGR_PLLQ_OFF) -/* System and main CPU clock */ -#define PLLCFGR_PLLR_EN BIT(24) -#define PLLCFGR_PLLR_OFF 25 -#define PLLCFGR_PLLR(val) (((val) & 0x3) << PLLCFGR_PLLR_OFF) -#define PLLCFGR_PLLP_OFF 27 -#define PLLCFGR_PLLP(val) (((val) & 0x1f) << PLLCFGR_PLLP_OFF) - -/* --- RCC CFGR Bit Definitions --- */ -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -/* AHB Prescalar: */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) -/* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 8 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) -/* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 11 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) -/* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -/* --- RCC AHB1ENR Bit Definitions --- */ -#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) -#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2) - -/* --- RCC AHB2ENR Bit Definitions --- */ -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0) -#define STM32_RCC_AHB2ENR_ADC12EN BIT(13) -#define STM32_RCC_APB2ENR_ADC345EN BIT(14) -#define STM32_RCC_AHB2ENR_RNGEN BIT(26) - -/* --- RCC APB1ENR1 Bit Definitions --- */ -#define STM32_RCC_APB1ENR1_TIM2EN BIT(0) -#define STM32_RCC_APB1ENR1_TIM3EN BIT(1) -#define STM32_RCC_APB1ENR1_TIM4EN BIT(2) -#define STM32_RCC_APB1ENR1_TIM5EN BIT(3) -#define STM32_RCC_APB1ENR1_TIM6EN BIT(4) -#define STM32_RCC_APB1ENR1_TIM7EN BIT(5) -#define STM32_RCC_APB1ENR1_WWDGEN BIT(11) -#define STM32_RCC_APB1ENR1_USART2 BIT(17) -#define STM32_RCC_APB1ENR1_USART3 BIT(18) -#define STM32_RCC_APB1ENR1_UART4 BIT(19) -#define STM32_RCC_APB1ENR1_UART5 BIT(20) -#define STM32_RCC_APB1ENR1_I2C1EN BIT(21) -#define STM32_RCC_APB1ENR1_I2C2EN BIT(22) -#define STM32_RCC_APB1ENR1_USBEN BIT(23) -#define STM32_RCC_APB1ENR1_PWREN BIT(28) -#define STM32_RCC_APB1ENR1_I2C3EN BIT(30) - -#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN - -/* --- RCC APB1ENR2 Bit Definitions --- */ -#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) -#define STM32_RCC_APB1ENR2_I2C4EN BIT(1) -#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8) - -/* --- RCC APB2ENR Bit Definitions --- */ -#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0) -#define STM32_RCC_APB2ENR_TIM1 BIT(11) -#define STM32_RCC_APB2ENR_SPI1EN BIT(12) -#define STM32_RCC_APB2ENR_TIM8 BIT(13) -#define STM32_RCC_APB2ENR_USART1 BIT(14) -#define STM32_RCC_APB2ENR_SPI4EN BIT(15) -#define STM32_RCC_APB2ENR_TIM15 BIT(16) -#define STM32_RCC_APB2ENR_TIM16 BIT(17) -#define STM32_RCC_APB2ENR_TIM17 BIT(18) -#define STM32_RCC_APB2ENR_TIM20 BIT(20) - -#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1 - -/* gpio.c needs STM32_RCC_SYSCFGEN */ -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN - -/* --- RCC APB1RSTR1 Bit Definitions --- */ -#define STM32_RCC_APB1RSTR1_USB_RST BIT(23) -#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1 -#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST - -/* --- RCC CSR Bit Definitions --- */ -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -/* --- RCC CCIPR Bit Definitions --- */ -#define STM32_RCC_CCIPR_UART_SYSCLK 0x1 -#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0 -#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10 -#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12 -#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14 -#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16 - -#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3 - -#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2) -#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2 -/* --- RCC CRRCR Bit Definitions */ -#define RCC_CRRCR_HSI48O BIT(0) -#define RCC_CRRCR_HSIRDY BIT(1) - -/* Reset causes definitions */ -/* - * Reset causes in RCC CSR register. The generic names are required - */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define STM32_RCC_CSR_RMVF BIT(24) -#define STM32_RCC_CSR_BORRS BIT(25) -#define STM32_RCC_CSR_PIN BIT(26) -#define STM32_RCC_CSR_POR BIT(27) -#define STM32_RCC_CSR_SFT BIT(28) -#define STM32_RCC_CSR_IWDG BIT(29) -#define STM32_RCC_CSR_WWDG BIT(30) -#define STM32_RCC_CSR_LPWR BIT(31) - - -#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | \ - STM32_RCC_CSR_IWDG) -#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT -#define RESET_CAUSE_POR STM32_RCC_CSR_POR -#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN -#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF -#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | \ - STM32_RCC_CSR_BORRS) -/* Power cause in PWR CSR register */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_SCR_CSBF BIT(8) -#define STM32_PWR_SR1_SBF BIT(8) - -#define STM32_PWR_RESET_CAUSE STM32_PWR_SR1 -#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF - -#define STM32_PWR_CR1_DBP BIT(8) - -#define STM32_PWR_CR3_UCPD1_STDBY BIT(13) -#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14) - -/* --- System Config Registers --- */ -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18) - - -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38) - -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48) -#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44) - -/* --- RTC CR Bit Definitions --- */ -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -/* --- RTC ICSR Bit Definitions --- */ -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -/* --- RTC PRER Bit Definitions --- */ -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) - - -/* --- Tamper and Backup --- */ -#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n)) -#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n) -#define STM32_BKP_BYTES 64 - - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned int crcpr; - unsigned int rxcrcr; - unsigned int txcrcr; - unsigned int i2scfgr; - unsigned int i2spr; -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) - -/* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- DBGMCU CR Bit Definitions --- */ -#define STM32_DBGMCU_CR_SLEEP BIT(0) -#define STM32_DBGMCU_CR_STOP BIT(1) -#define STM32_DBGMCU_CR_STBY BIT(2) -#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define STM32_DBGMCU_CR_TRACE_EN BIT(5) -#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6)|BIT(7)) -/* --- DBGMCU APB1FZ Bit Definitions --- */ -#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) -#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) -#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) -#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) -#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) -#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) -#define STM32_DBGMCU_APB1FZ_RTC BIT(10) -#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) -#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) -#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) -#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) -#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30) -/* --- DBGMCU APB2FZ Bit Definitions --- */ -#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11) -#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13) -#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16) -#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17) -#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18) -#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20) - -/* --- Flash --- */ -#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off)) -#define STM32_FLASH_ACR STM32_FLASH_REG(0x00) -#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04) -#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08) -#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c) -#define STM32_FLASH_SR STM32_FLASH_REG(0x10) -#define STM32_FLASH_CR STM32_FLASH_REG(0x14) -#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18) -/* - * Bank 1 Option Byte Copy Registers. These registers are loaded from the option - * bytes location in flash at reset, assuming that option byte loading has not - * been disabled. - */ -#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20) -#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24) -#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28) -#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C) -#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30) -/* - * Bank 2 Option Byte Copy Registers. These will only exist for category 3 - * devices. - */ -#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44) -#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48) -#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C) -#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50) - -#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70) -#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74) - -/* --- FLASH CR Bit Definitions --- */ -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) - -/* --- FLASH KEYR Bit Definitions --- */ -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -/* --- FLASH OPTKEYR Bit Definitions --- */ -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F - -/* --- FLASH SR Bit Definitions --- */ -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_OPTVERR BIT(15) -#define FLASH_SR_RDERR BIT(14) -#define FLASH_SR_FASTERR BIT(9) -#define FLASH_SR_MISERR BIT(8) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_SIZERR BIT(6) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PROGERR BIT(3) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_ERR_MASK (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \ - FLASH_SR_FASTERR | FLASH_SR_PGSERR | \ - FLASH_SR_SIZERR | FLASH_SR_PGAERR | \ - FLASH_SR_WRPERR | FLASH_SR_PROGERR | \ - FLASH_SR_OPERR) - -/* --- FLASH CR Bit Definitions --- */ -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0x7f) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f) - -#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2) - -/* --- FLASH Option bytes --- */ -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00) -#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08) -#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20) -#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28) - -#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00) -#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08) -#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10) -#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18) -#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20) -#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28) - -/* Read option bytes from flash memory for Bank 1 */ -#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8)) -#define STM32_OPTB_BANK1_COMP_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8) + 0x4) -#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8)) -#define STM32_OPTB_BANK2_COMP_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8) + 0x4) - -#define STM32_OPTB_USER_DBANK BIT(22) -#define STM32_OPTB_USER_nBOOT1 BIT(23) -#define STM32_OPTB_USER_nSWBOOT0 BIT(26) -#define STM32_OPTB_USER_nBOOT0 BIT(27) -#define STM32_OPTB_ENTRY_NUM 6 - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(17) - -/* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4) - - -/* --- ADC CR Bit Definitions --- */ -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADSTART BIT(2) -#define STM32_ADC_CR_ADVREGEN BIT(28) -#define STM32_ADC_CR_CAL BIT(31) - -#define STM32_ADC_CFGR_CONT BIT(13) -#define STM32_ADC_CR2_ALIGN BIT(15) - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * - * Channels 0 - 5 are managed by controller DMA1, 6 - 11 by DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_RX = STM32_DMAC_CH10, - STM32_DMAC_USART1_TX = STM32_DMAC_CH11, - STM32_DMAC_USART3_RX = STM32_DMAC_CH12, - STM32_DMAC_USART3_TX = STM32_DMAC_CH13, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH5, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH6, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, - STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, - STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - STM32_DMAC_LPUART_RX = STM32_DMAC_CH9, - STM32_DMAC_LPUART_TX = STM32_DMAC_CH10, - STM32_DMAC_COUNT = 14, -}; - -#define STM32_DMAC_PER_CTLR 8 - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - -/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */ -/* DMAMUX registers */ -#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) -#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) -#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) -#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) -#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) -#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) - -enum dmamux1_request { - DMAMUX_REQ_ADC1 = 5, - DMAMUX_REQ_DAC1_CH1 = 6, - DMAMUX_REQ_DAC1_CH2 = 7, - DMAMUX_REQ_TIM6_UP = 8, - DMAMUX_REQ_TIM7_UP = 9, - DMAMUX_REQ_SPI1_RX = 10, - DMAMUX_REQ_SPI1_TX = 11, - DMAMUX_REQ_SPI2_RX = 12, - DMAMUX_REQ_SPI2_TX = 13, - DMAMUX_REQ_SPI3_RX = 14, - DMAMUX_REQ_SPI3_TX = 15, - DMAMUX_REQ_I2C1_RX = 16, - DMAMUX_REQ_I2C1_TX = 17, - DMAMUX_REQ_I2C2_RX = 18, - DMAMUX_REQ_I2C2_TX = 19, - DMAMUX_REQ_I2C3_RX = 20, - DMAMUX_REQ_I2C3_TX = 21, - DMAMUX_REQ_I2C4_RX = 22, - DMAMUX_REQ_I2C4_TX = 23, - DMAMUX_REQ_USART1_RX = 24, - DMAMUX_REQ_USART1_TX = 25, - DMAMUX_REQ_USART2_RX = 26, - DMAMUX_REQ_USART2_TX = 27, - DMAMUX_REQ_USART3_RX = 28, - DMAMUX_REQ_USART3_TX = 29, - DMAMUX_REQ_UART4_RX = 30, - DMAMUX_REQ_UART4_TX = 31, - DMAMUX_REQ_USART5_RX = 32, - DMAMUX_REQ_UART5_TX = 33, - DMAMUX_REQ_LPUART1_RX = 34, - DMAMUX_REQ_LPUART1_TX = 35, - DMAMUX_REQ_ADC2 = 36, - DMAMUX_REQ_ADC3 = 37, - DMAMUX_REQ_ADC4 = 38, - DMAMUX_REQ_ADC5 = 39, - DMAMUX_REQ_QUADSPI = 40, - DMAMUX_REQ_DAC2_CH1 = 41, - DMAMUX_REQ_TIM1_CH1 = 42, - DMAMUX_REQ_TIM1_CH2 = 43, - DMAMUX_REQ_TIM1_CH3 = 44, - DMAMUX_REQ_TIM1_CH4 = 45, - DMAMUX_REQ_TIM1_UP = 46, - DMAMUX_REQ_TIM1_TRIG = 47, - DMAMUX_REQ_TIM1_COM = 48, - DMAMUX_REQ_TIM8_CH1 = 49, - DMAMUX_REQ_TIM8_CH2 = 50, - DMAMUX_REQ_TIM8_CH3 = 51, - DMAMUX_REQ_TIM8_CH4 = 52, - DMAMUX_REQ_TIM8_UP = 53, - DMAMUX_REQ_TIM8_TRIG = 54, - DMAMUX_REQ_TIM8_COM = 55, - DMAMUX_REQ_TIM2_CH1 = 56, - DMAMUX_REQ_TIM2_CH2 = 57, - DMAMUX_REQ_TIM2_CH3 = 58, - DMAMUX_REQ_TIM2_CH4 = 59, - DMAMUX_REQ_TIM2_UP = 60, - DMAMUX_REQ_TIM3_CH1 = 61, - DMAMUX_REQ_TIM3_CH2 = 62, - DMAMUX_REQ_TIM3_CH3 = 63, - DMAMUX_REQ_TIM3_CH4 = 64, - DMAMUX_REQ_TIM3_UP = 65, - DMAMUX_REQ_TIM3_TRIG = 66, - DMAMUX_REQ_TIM4_CH1 = 67, - DMAMUX_REQ_TIM4_CH2 = 68, - DMAMUX_REQ_TIM4_CH3 = 69, - DMAMUX_REQ_TIM4_CH4 = 70, - DMAMUX_REQ_TIM4_UP = 71, - DMAMUX_REQ_TIM5_CH1 = 72, - DMAMUX_REQ_TIM5_CH2 = 73, - DMAMUX_REQ_TIM5_CH3 = 74, - DMAMUX_REQ_TIM5_CH4 = 75, - DMAMUX_REQ_TIM5_UP = 76, - DMAMUX_REQ_TIM5_TRIG = 77, - DMAMUX_REQ_TIM15_CH1 = 78, - DMAMUX_REQ_TIM15_UP = 79, - DMAMUX_REQ_TIM15_TRIG = 80, - DMAMUX_REQ_TIM15_COM = 81, - DMAMUX_REQ_TIM16_CH1 = 82, - DMAMUX_REQ_TIM16_UP = 83, - DMAMUX_REQ_TIM17_CH1 = 84, - DMAMUX_REQ_TIM17_UP = 85, - DMAMUX_REQ_TIM20_CH1 = 86, - DMAMUX_REQ_TIM20_CH2 = 87, - DMAMUX_REQ_TIM20_CH3 = 88, - DMAMUX_REQ_TIM20_CH4 = 89, - DMAMUX_REQ_TIM20_UP = 90, - DMAMUX_REQ_AES_IN = 91, - DMAMUX_REQ_AES_OUT = 92, - DMAMUX_REQ_TIM20_TRIG = 93, - DMAMUX_REQ_TIM20_COM = 94, - DMAMUX_REQ_DAC3_CH1 = 102, - DMAMUX_REQ_DAC3_CH2 = 103, - DMAMUX_REQ_DAC4_CH1 = 104, - DMAMUX_REQ_DAC4_CH2 = 105, - DMAMUX_REQ_SPI4_RX = 106, - DMAMUX_REQ_SPI4_TX = 107, - DMAMUX_REQ_SAI1_A = 108, - DMAMUX_REQ_SAI1_B = 109, -}; -/* LPUART gets accessed as UART9 in STM32 uart module */ -#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX -#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) -#define STM32_USB_BCDR_DPPU BIT(15) - -/* --- USB Endpoint bit definitions --- */ -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- RNG CR Bit Definitions --- */ -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -/* --- RNG SR_DRDY Bit Definitions --- */ -#define STM32_RNG_SR_DRDY BIT(0) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ - diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h deleted file mode 100644 index d02aaf1249..0000000000 --- a/chip/stm32/registers-stm32h7.h +++ /dev/null @@ -1,1228 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32H7 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32H7X3 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - -#define STM32_IRQ_LPTIM1 93 -#define STM32_IRQ_TIM15 116 -#define STM32_IRQ_TIM16 117 -#define STM32_IRQ_TIM17 118 -#define STM32_IRQ_LPTIM2 138 -#define STM32_IRQ_LPTIM3 139 -#define STM32_IRQ_LPTIM4 140 -#define STM32_IRQ_LPTIM5 141 - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - -/* - * STM32F4 introduces a concept of DMA stream to allow - * fine allocation of a stream to a channel. - */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 - -/* Peripheral base addresses */ - -#define STM32_GPV_BASE 0x51000000 - -#define STM32_DBGMCU_BASE 0x5C001000 - -#define STM32_BDMA_BASE 0x58025400 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 -#define STM32_DMA2D_BASE 0x52001000 -#define STM32_DMAMUX1_BASE 0x40020800 -#define STM32_DMAMUX2_BASE 0x58025800 -#define STM32_MDMA_BASE 0x52000000 - -#define STM32_EXTI_BASE 0x58000000 - -#define STM32_FLASH_REGS_BASE 0x52002000 - -#define STM32_GPIOA_BASE 0x58020000 -#define STM32_GPIOB_BASE 0x58020400 -#define STM32_GPIOC_BASE 0x58020800 -#define STM32_GPIOD_BASE 0x58020C00 -#define STM32_GPIOE_BASE 0x58021000 -#define STM32_GPIOF_BASE 0x58021400 -#define STM32_GPIOG_BASE 0x58021800 -#define STM32_GPIOH_BASE 0x58021C00 -#define STM32_GPIOI_BASE 0x58022000 -#define STM32_GPIOJ_BASE 0x58022400 -#define STM32_GPIOK_BASE 0x58022800 - -#define STM32_IWDG_BASE 0x58004800 - -#define STM32_LPTIM1_BASE 0x40002400 -#define STM32_LPTIM2_BASE 0x58002400 -#define STM32_LPTIM3_BASE 0x58002800 -#define STM32_LPTIM4_BASE 0x58002C00 -#define STM32_LPTIM5_BASE 0x58003000 - -#define STM32_PWR_BASE 0x58024800 -#define STM32_RCC_BASE 0x58024400 -#define STM32_RNG_BASE 0x48021800 -#define STM32_RTC_BASE 0x58004000 - -#define STM32_SYSCFG_BASE 0x58000400 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 -#define STM32_SPI4_BASE 0x40013400 -#define STM32_SPI5_BASE 0x40015000 - -#define STM32_TIM1_BASE 0x40010000 -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM8_BASE 0x40010400 -#define STM32_TIM12_BASE 0x40001800 -#define STM32_TIM13_BASE 0x40001c00 -#define STM32_TIM14_BASE 0x40002000 -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 - -#define STM32_UNIQUE_ID_BASE 0x1ff1e800 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 -#define STM32_USART7_BASE 0x40007800 -#define STM32_USART8_BASE 0x40007C00 - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ - - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_CR3_BYPASS BIT(0) -#define STM32_PWR_CR3_LDOEN BIT(1) -#define STM32_PWR_CR3_SCUEN BIT(2) -#define STM32_PWR_CR3_VBE BIT(8) -#define STM32_PWR_CR3_VBRS BIT(9) -#define STM32_PWR_CR3_USB33DEN BIT(24) -#define STM32_PWR_CR3_USBREGEN BIT(25) -#define STM32_PWR_CR3_USB33RDY BIT(26) -#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) -#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) -#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) -#define STM32_PWR_CPUCR_STOPF BIT(5) -#define STM32_PWR_CPUCR_SBF BIT(6) -#define STM32_PWR_CPUCR_SBF_D1 BIT(7) -#define STM32_PWR_CPUCR_SBF_D2 BIT(8) -#define STM32_PWR_CPUCR_CSSF BIT(9) -#define STM32_PWR_CPUCR_RUN_D3 BIT(11) -#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_D3CR_VOS1 (3 << 14) -#define STM32_PWR_D3CR_VOS2 (2 << 14) -#define STM32_PWR_D3CR_VOS3 (1 << 14) -#define STM32_PWR_D3CR_VOSMASK (3 << 14) -#define STM32_PWR_D3CR_VOSRDY (1 << 13) -#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) -#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) -#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010) -#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018) -#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C) -#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020) -#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C) -#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030) -#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034) -#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038) -#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C) -#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040) -#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044) -#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C) -#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050) -#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054) -#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074) - -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098) - -#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_HASHEN BIT(5) -#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) -#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) -#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff -#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) -#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8) -#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) -#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) -#define STM32_RCC_SYSCFGEN BIT(1) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) -#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108) -#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C) -#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110) -#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118) -#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C) -/* Aliases */ -#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR - -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(2) -#define STM32_RCC_CR_CSION BIT(7) -#define STM32_RCC_CR_CSIRDY BIT(8) -#define STM32_RCC_CR_HSI48ON BIT(12) -#define STM32_RCC_CR_HSI48RDY BIT(13) -#define STM32_RCC_CR_PLL1ON BIT(24) -#define STM32_RCC_CR_PLL1RDY BIT(25) -#define STM32_RCC_CR_PLL2ON BIT(26) -#define STM32_RCC_CR_PLL2RDY BIT(27) -#define STM32_RCC_CR_PLL3ON BIT(28) -#define STM32_RCC_CR_PLL3RDY BIT(29) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_CSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL1 (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 3) -#define STM32_RCC_CFGR_SWS_CSI (1 << 3) -#define STM32_RCC_CFGR_SWS_HSE (2 << 3) -#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) -#define STM32_RCC_CFGR_SWS_MASK (3 << 3) -#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) -#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) -#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0) -#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) -#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) -#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) -#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) -#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) -#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) -#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) -#define STM32_RCC_PLLDIV_DIVN(n) (((n) - 1) << 0) -#define STM32_RCC_PLLDIV_DIVP(p) (((p) - 1) << 9) -#define STM32_RCC_PLLDIV_DIVQ(q) (((q) - 1) << 16) -#define STM32_RCC_PLLDIV_DIVR(r) (((r) - 1) << 24) -#define STM32_RCC_PLLFRAC(n) ((n) << 3) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) -#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) -#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0) -#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3) -#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - -/* Peripheral bits for APB1ENR regs */ -#define STM32_RCC_PB1_LPTIM1 BIT(9) - -/* Peripheral bits for APB2ENR regs */ -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM2 BIT(1) -#define STM32_RCC_PB2_USART1 BIT(4) -#define STM32_RCC_PB2_SPI1 BIT(12) -#define STM32_RCC_PB2_SPI4 BIT(13) -#define STM32_RCC_PB2_TIM15 BIT(16) -#define STM32_RCC_PB2_TIM16 BIT(17) -#define STM32_RCC_PB2_TIM17 BIT(18) - -/* Peripheral bits for AHB1/2/3/4ENR regs */ -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB3_MDMA BIT(0) -#define STM32_RCC_HB4_BDMA BIT(21) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) - -/* Reset causes definitions */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_RSR -#define RESET_CAUSE_WDG (BIT(28)|BIT(26)) -#define RESET_CAUSE_SFT BIT(24) -#define RESET_CAUSE_POR BIT(23) -#define RESET_CAUSE_PIN BIT(22) -#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ - BIT(27)|BIT(26)|BIT(25)|BIT(24)| \ - BIT(23)|BIT(22)|BIT(21)|BIT(20)| \ - BIT(19)|BIT(18)|BIT(17)) -#define RESET_CAUSE_RMVF BIT(16) - -/* Power cause in PWR CPUCR register (Standby&Stop modes) */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR -#define RESET_CAUSE_SBF BIT(6) -#define RESET_CAUSE_SBF_CLR BIT(9) - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint32_t cr1; - uint32_t cr2; - uint32_t cfg1; - uint32_t cfg2; - uint32_t ier; - uint32_t sr; - uint32_t ifcr; - uint32_t _pad0; - uint32_t txdr; - uint32_t _pad1[3]; - uint32_t rxdr; - uint32_t _pad2[3]; - uint32_t crcpoly; - uint32_t rxcrcr; - uint32_t txcrcr; - uint32_t udrdr; -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_SPE BIT(0) -#define STM32_SPI_CR1_CSTART BIT(9) -#define STM32_SPI_CR1_SSI BIT(12) -#define STM32_SPI_CR1_DIV(div) ((div) << 28) -#define STM32_SPI_CFG1_DATASIZE(n) (((n) - 1) << 0) -#define STM32_SPI_CFG1_FTHLV(n) (((n) - 1) << 5) -#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9) -#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) -#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) -#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) -#define STM32_SPI_CFG1_RXDMAEN BIT(14) -#define STM32_SPI_CFG1_TXDMAEN BIT(15) -#define STM32_SPI_CFG1_CRCSIZE(n) (((n) - 1) << 16) -#define STM32_SPI_CFG2_MSTR BIT(22) -#define STM32_SPI_CFG2_SSM BIT(26) -#define STM32_SPI_CFG2_AFCNTR BIT(31) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_UDR BIT(5) -#define STM32_SPI_SR_FRLVL (3 << 13) -#define STM32_SPI_SR_TXC BIT(12) - -/* --- Debug --- */ -#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34) -#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C) -#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C) -#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54) -/* Alias */ -#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ - -/* --- Flash --- */ -#define STM32_FLASH_REG(bank, offset) REG32(((bank) ? 0x100 : 0) + \ - STM32_FLASH_REGS_BASE + (offset)) - -#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4) -#define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4) -#define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4) -#define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4) - -#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) -#define FLASH_CR_LOCK BIT(0) -#define FLASH_CR_PG BIT(1) -#define FLASH_CR_SER BIT(2) -#define FLASH_CR_BER BIT(3) -#define FLASH_CR_PSIZE_BYTE (0 << 4) -#define FLASH_CR_PSIZE_HWORD (1 << 4) -#define FLASH_CR_PSIZE_WORD (2 << 4) -#define FLASH_CR_PSIZE_DWORD (3 << 4) -#define FLASH_CR_PSIZE_MASK (3 << 4) -#define FLASH_CR_FW BIT(6) -#define FLASH_CR_STRT BIT(7) -#define FLASH_CR_SNB(sec) (((sec) & 0x7) << 8) -#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) -#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_WBNE BIT(1) -#define FLASH_SR_QW BIT(2) -#define FLASH_SR_CRC_BUSY BIT(3) -#define FLASH_SR_EOP BIT(16) -#define FLASH_SR_WRPERR BIT(17) -#define FLASH_SR_PGSERR BIT(18) -#define FLASH_SR_STRBERR BIT(19) -#define FLASH_SR_INCERR BIT(21) -#define FLASH_SR_OPERR BIT(22) -#define FLASH_SR_RDPERR BIT(23) -#define FLASH_SR_RDSERR BIT(24) -#define FLASH_SR_SNECCERR BIT(25) -#define FLASH_SR_DBECCERR BIT(26) -#define FLASH_SR_CRCEND BIT(27) -#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) -#define FLASH_CCR_ERR_MASK (FLASH_SR_WRPERR | FLASH_SR_PGSERR \ - | FLASH_SR_STRBERR | FLASH_SR_INCERR \ - | FLASH_SR_OPERR | FLASH_SR_RDPERR \ - | FLASH_SR_RDSERR | FLASH_SR_SNECCERR \ - | FLASH_SR_DBECCERR) -#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) -#define FLASH_OPTCR_OPTLOCK BIT(0) -#define FLASH_OPTCR_OPTSTART BIT(1) -#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) -#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) -#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ -#define FLASH_OPTSR_RDP_MASK (0xFF << 8) -#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) -/* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) -#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) -#define FLASH_OPTSR_RSS1 BIT(26) -#define FLASH_OPTSR_RSS2 BIT(27) -#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) -#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) -#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) -#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30) -#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34) -#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38) -#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C) -#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40) -#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44) -#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50) -#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54) -#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58) -#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C) -#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60) - -/* --- External Interrupts --- */ -#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C) -#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14) -#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) -#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) -#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) -#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C) -#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30) -#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34) -#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40) -#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44) -#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48) -#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C) -#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50) -#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54) -#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80) -#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84) -#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88) -#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90) -#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94) -#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98) -#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0) -#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4) -#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8) -/* Aliases */ -#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_RTSR STM32_EXTI_RTSR1 -#define STM32_EXTI_FTSR STM32_EXTI_FTSR1 -#define STM32_EXTI_SWIER STM32_EXTI_SWIER1 -#define STM32_EXTI_PR STM32_EXTI_CPUPR1 - - -/* --- ADC --- */ - -/* --- Comparators --- */ - - -/* --- DMA --- */ -/* - * Available DMA streams, numbered from 0. - * - * Named channel to respect older interface, but a stream can serve - * any channels, as long as they are in the same DMA controller. - * - * Stream 0 - 7 are managed by controller DMA1, 8 - 15 DMA2. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMA1_STREAM0 = 0, - STM32_DMA1_STREAM1 = 1, - STM32_DMA1_STREAM2 = 2, - STM32_DMA1_STREAM3 = 3, - STM32_DMA1_STREAM4 = 4, - STM32_DMA1_STREAM5 = 5, - STM32_DMA1_STREAM6 = 6, - STM32_DMA1_STREAM7 = 7, - STM32_DMAS_COUNT = 8, - STM32_DMA2_STREAM0 = 8, - STM32_DMA2_STREAM1 = 9, - STM32_DMA2_STREAM2 = 10, - STM32_DMA2_STREAM3 = 11, - STM32_DMA2_STREAM4 = 12, - STM32_DMA2_STREAM5 = 13, - STM32_DMA2_STREAM6 = 14, - STM32_DMA2_STREAM7 = 15, - - STM32_DMAS_USART1_TX = STM32_DMA2_STREAM7, - STM32_DMAS_USART1_RX = STM32_DMA2_STREAM5, - - /* Legacy naming for uart.c */ - STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX, - STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX, - - STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM6, - STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0, - - STM32_DMAC_I2C2_TX = STM32_DMA1_STREAM7, - STM32_DMAC_I2C2_RX = STM32_DMA1_STREAM3, - - STM32_DMAC_I2C3_TX = STM32_DMA1_STREAM4, - STM32_DMAC_I2C3_RX = STM32_DMA1_STREAM1, - - STM32_DMAC_FMPI2C4_TX = STM32_DMA1_STREAM5, - STM32_DMAC_FMPI2C4_RX = STM32_DMA1_STREAM2, - - /* Legacy naming for spi_master.c */ - STM32_DMAC_SPI1_TX = STM32_DMA2_STREAM3, /* REQ 3 */ - STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */ - STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */ - STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */ - STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */ - STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */ - STM32_DMAC_SPI4_TX = STM32_DMA2_STREAM1, /* STM32H7 */ - STM32_DMAC_SPI4_RX = STM32_DMA2_STREAM4, /* STM32H7 */ -}; - -#define STM32_REQ_USART1_TX 4 -#define STM32_REQ_USART1_RX 4 - -#define STM32_REQ_USART2_TX 4 -#define STM32_REQ_USART2_RX 4 - -#define STM32_I2C1_TX_REQ_CH 1 -#define STM32_I2C1_RX_REQ_CH 1 - -#define STM32_I2C2_TX_REQ_CH 7 -#define STM32_I2C2_RX_REQ_CH 7 - -#define STM32_I2C3_TX_REQ_CH 3 -#define STM32_I2C3_RX_REQ_CH 1 - -#define STM32_FMPI2C4_TX_REQ_CH 2 -#define STM32_FMPI2C4_RX_REQ_CH 2 - -#define STM32_SPI1_TX_REQ_CH 3 -#define STM32_SPI1_RX_REQ_CH 3 -#define STM32_SPI2_TX_REQ_CH 0 -#define STM32_SPI2_RX_REQ_CH 0 -#define STM32_SPI3_TX_REQ_CH 0 -#define STM32_SPI3_RX_REQ_CH 0 - -#define STM32_DMAS_TOTAL_COUNT 16 - -/* Registers for a single stream of a DMA controller */ -struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ -}; - -/* Always use stm32_dma_stream_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_stream stm32_dma_stream_t; - -/* Common code and header file must use this */ -typedef stm32_dma_stream_t dma_chan_t; -struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; - stm32_dma_stream_t stream[STM32_DMAS_COUNT]; -}; - - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) - -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) - -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ - (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) -#define STM32_DMA_CH_GETBITS(channel, val) \ - (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - -/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */ -/* DMAMUX1/2 registers */ -#define DMAMUX1 0 -#define DMAMUX2 1 -#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE \ - : STM32_DMAMUX1_BASE) -#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off)) -#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x)) -#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80) -#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84) -#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x)) -#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140) -#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144) - -enum dmamux1_request { - DMAMUX1_REQ_ADC1 = 9, - DMAMUX1_REQ_ADC2 = 10, - DMAMUX1_REQ_TIM1_CH1 = 11, - DMAMUX1_REQ_TIM1_CH2 = 12, - DMAMUX1_REQ_TIM1_CH3 = 13, - DMAMUX1_REQ_TIM1_CH4 = 14, - DMAMUX1_REQ_TIM1_UP = 15, - DMAMUX1_REQ_TIM1_TRIG = 16, - DMAMUX1_REQ_TIM1_COM = 17, - DMAMUX1_REQ_TIM2_CH1 = 18, - DMAMUX1_REQ_TIM2_CH2 = 19, - DMAMUX1_REQ_TIM2_CH3 = 20, - DMAMUX1_REQ_TIM2_CH4 = 21, - DMAMUX1_REQ_TIM2_UP = 22, - DMAMUX1_REQ_TIM3_CH1 = 23, - DMAMUX1_REQ_TIM3_CH2 = 24, - DMAMUX1_REQ_TIM3_CH3 = 25, - DMAMUX1_REQ_TIM3_CH4 = 26, - DMAMUX1_REQ_TIM3_UP = 27, - DMAMUX1_REQ_TIM3_TRIG = 28, - DMAMUX1_REQ_TIM4_CH1 = 29, - DMAMUX1_REQ_TIM4_CH2 = 30, - DMAMUX1_REQ_TIM4_CH3 = 31, - DMAMUX1_REQ_TIM4_UP = 32, - DMAMUX1_REQ_I2C1_RX = 33, - DMAMUX1_REQ_I2C1_TX = 34, - DMAMUX1_REQ_I2C2_RX = 35, - DMAMUX1_REQ_I2C2_TX = 36, - DMAMUX1_REQ_SPI1_RX = 37, - DMAMUX1_REQ_SPI1_TX = 38, - DMAMUX1_REQ_SPI2_RX = 39, - DMAMUX1_REQ_SPI2_TX = 40, - DMAMUX1_REQ_USART1_RX = 41, - DMAMUX1_REQ_USART1_TX = 42, - DMAMUX1_REQ_USART2_RX = 43, - DMAMUX1_REQ_USART2_TX = 44, - DMAMUX1_REQ_USART3_RX = 45, - DMAMUX1_REQ_USART3_TX = 46, - DMAMUX1_REQ_TIM8_CH1 = 47, - DMAMUX1_REQ_TIM8_CH2 = 48, - DMAMUX1_REQ_TIM8_CH3 = 49, - DMAMUX1_REQ_TIM8_CH4 = 50, - DMAMUX1_REQ_TIM8_UP = 51, - DMAMUX1_REQ_TIM8_TRIG = 52, - DMAMUX1_REQ_TIM8_COM = 53, - DMAMUX1_REQ_TIM5_CH1 = 55, - DMAMUX1_REQ_TIM5_CH2 = 56, - DMAMUX1_REQ_TIM5_CH3 = 57, - DMAMUX1_REQ_TIM5_CH4 = 58, - DMAMUX1_REQ_TIM5_UP = 59, - DMAMUX1_REQ_TIM5_TRIG = 60, - DMAMUX1_REQ_SPI3_RX = 61, - DMAMUX1_REQ_SPI3_TX = 62, - DMAMUX1_REQ_UART4_RX = 63, - DMAMUX1_REQ_UART4_TX = 64, - DMAMUX1_REQ_USART5_RX = 65, - DMAMUX1_REQ_UART5_TX = 66, - DMAMUX1_REQ_DAC1 = 67, - DMAMUX1_REQ_DAC2 = 68, - DMAMUX1_REQ_TIM6_UP = 69, - DMAMUX1_REQ_TIM7_UP = 70, - DMAMUX1_REQ_USART6_RX = 71, - DMAMUX1_REQ_USART6_TX = 72, - DMAMUX1_REQ_I2C3_RX = 73, - DMAMUX1_REQ_I2C3_TX = 74, - DMAMUX1_REQ_DCMI = 75, - DMAMUX1_REQ_CRYP_IN = 76, - DMAMUX1_REQ_CRYP_OUT = 77, - DMAMUX1_REQ_HASH_IN = 78, - DMAMUX1_REQ_UART7_RX = 79, - DMAMUX1_REQ_UART7_TX = 80, - DMAMUX1_REQ_UART8_RX = 81, - DMAMUX1_REQ_UART8_TX = 82, - DMAMUX1_REQ_SPI4_RX = 83, - DMAMUX1_REQ_SPI4_TX = 84, - DMAMUX1_REQ_SPI5_RX = 85, - DMAMUX1_REQ_SPI5_TX = 86, - DMAMUX1_REQ_SAI1_A = 87, - DMAMUX1_REQ_SAI1_B = 88, - DMAMUX1_REQ_SAI2_A = 89, - DMAMUX1_REQ_SAI2_B = 90, - DMAMUX1_REQ_SWPMI_RX = 91, - DMAMUX1_REQ_SWPMI_TX = 92, - DMAMUX1_REQ_SPDIFRX_DT = 93, - DMAMUX1_REQ_SPDIFRX_CS = 94, - DMAMUX1_REQ_TIM15_CH1 = 105, - DMAMUX1_REQ_TIM15_UP = 106, - DMAMUX1_REQ_TIM15_TRIG = 107, - DMAMUX1_REQ_TIM15_COM = 108, - DMAMUX1_REQ_TIM16_CH1 = 109, - DMAMUX1_REQ_TIM16_UP = 110, - DMAMUX1_REQ_TIM17_CH1 = 111, - DMAMUX1_REQ_TIM17_UP = 112, - DMAMUX1_REQ_SAI3_A = 113, - DMAMUX1_REQ_SAI3_B = 114, - DMAMUX1_REQ_ADC3 = 115, -}; - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h deleted file mode 100644 index 37b31ac302..0000000000 --- a/chip/stm32/registers-stm32l.h +++ /dev/null @@ -1,871 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32L family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32L100 - * - STM32L15X - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ -/* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - - -/* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - -#define STM32_COMP_BASE 0x40007C00 - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 - -#define STM32_EXTI_BASE 0x40010400 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ -#define STM32_GPIOG_BASE 0x40021C00 -#define STM32_GPIOH_BASE 0x40021400 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1ff80000 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40010000 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ -#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ -#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac - -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) -/* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) - -/* --- GPIO --- */ - - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_MSION BIT(8) -#define STM32_RCC_CR_MSIRDY BIT(9) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_MSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_MSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) - -#define STM32_RCC_HB_DMA1 BIT(24) -#define STM32_RCC_PB2_TIM9 BIT(2) -#define STM32_RCC_PB2_TIM10 BIT(3) -#define STM32_RCC_PB2_TIM11 BIT(4) -#define STM32_RCC_PB1_USB BIT(23) - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - - -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned crcpr; - unsigned rxcrcr; - unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(1) -#define STM32_FLASH_ACR_ACC64 BIT(2) -#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_PECR_PE_LOCK BIT(0) -#define STM32_FLASH_PECR_PRG_LOCK BIT(1) -#define STM32_FLASH_PECR_OPT_LOCK BIT(2) -#define STM32_FLASH_PECR_PROG BIT(3) -#define STM32_FLASH_PECR_ERASE BIT(9) -#define STM32_FLASH_PECR_FPRG BIT(10) -#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF -#define STM32_FLASH_PEKEYR_KEY2 0x02030405 -#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF -#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 -#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP 0x00 -#define STM32_OPTB_USER 0x04 -#define STM32_OPTB_WRP1L 0x08 -#define STM32_OPTB_WRP1H 0x0c -#define STM32_OPTB_WRP2L 0x10 -#define STM32_OPTB_WRP2H 0x14 -#define STM32_OPTB_WRP3L 0x18 -#define STM32_OPTB_WRP3H 0x1c - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - - -/* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) -#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) -#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) -#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) -#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) - -#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) - -/* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00) - -#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21) -#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21) -#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21) -#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21) -#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21) -#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21) -#define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21) -#define STM32_COMP_OUTSEL_NONE (7 << 21) - -#define STM32_COMP_INSEL_NONE (0 << 18) -#define STM32_COMP_INSEL_PB3 (1 << 18) -#define STM32_COMP_INSEL_VREF (2 << 18) -#define STM32_COMP_INSEL_VREF34 (3 << 18) -#define STM32_COMP_INSEL_VREF12 (4 << 18) -#define STM32_COMP_INSEL_VREF14 (5 << 18) -#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) -#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) - -#define STM32_COMP_WNDWE BIT(17) -#define STM32_COMP_VREFOUTEN BIT(16) -#define STM32_COMP_CMP2OUT BIT(13) -#define STM32_COMP_SPEED_FAST BIT(12) - -#define STM32_COMP_CMP1OUT BIT(7) -#define STM32_COMP_CMP1EN BIT(4) - -#define STM32_COMP_400KPD BIT(3) -#define STM32_COMP_10KPD BIT(2) -#define STM32_COMP_400KPU BIT(1) -#define STM32_COMP_10KPU BIT(0) - - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - - /* Channel functions */ - STM32_DMAC_ADC = STM32_DMAC_CH1, - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_DAC_CH1 = STM32_DMAC_CH2, - STM32_DMAC_DAC_CH2 = STM32_DMAC_CH3, - STM32_DMAC_I2C2_TX = STM32_DMAC_CH4, - STM32_DMAC_I2C2_RX = STM32_DMAC_CH5, - STM32_DMAC_USART1_TX = STM32_DMAC_CH4, - STM32_DMAC_USART1_RX = STM32_DMAC_CH5, - STM32_DMAC_USART2_RX = STM32_DMAC_CH6, - STM32_DMAC_USART2_TX = STM32_DMAC_CH7, - STM32_DMAC_I2C1_TX = STM32_DMAC_CH6, - STM32_DMAC_I2C1_RX = STM32_DMAC_CH7, - STM32_DMAC_PMSE_ROW = STM32_DMAC_CH6, - STM32_DMAC_PMSE_COL = STM32_DMAC_CH7, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH6, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH7, - /* Only DMA1 (with 7 channels) is present on STM32L151x */ - STM32_DMAC_COUNT = 7, -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) - -#define STM32_DMA_REGS(channel) STM32_DMA1_REGS - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - - -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h deleted file mode 100644 index 29965fe2ee..0000000000 --- a/chip/stm32/registers-stm32l4.h +++ /dev/null @@ -1,2114 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32L4 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32L442 - * - STM32L476 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/****** STM32 specific Interrupt Numbers ********/ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD_PVM 1 -#define STM32_IRQ_TAMP_STAMP 2 -#define STM32_IRQ_RTC_WKUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_ADC1 18 -#define STM32_IRQ_CAN1_TX 19 -#define STM32_IRQ_CAN1_RX0 20 -#define STM32_IRQ_CAN1_RX1 21 -#define STM32_IRQ_CAN1_SCE 22 -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM1_BRK_TIM15 24 -#define STM32_IRQ_TIM1_UP_TIM16 25 -#define STM32_IRQ_TIM1_TRG_COM 26 -#define STM32_IRQ_TIM1_CC 27 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_SDMMC1 49 -#define STM32_IRQ_TIM5 50 -#define STM32_IRQ_SPI3 51 -#define STM32_IRQ_TIM6_DAC 54 -#define STM32_IRQ_TIM7 55 -#define STM32_IRQ_DMA2_CHANNEL1 56 -#define STM32_IRQ_DMA2_CHANNEL2 57 -#define STM32_IRQ_DMA2_CHANNEL3 58 -#define STM32_IRQ_DMA2_CHANNEL4 59 -#define STM32_IRQ_DMA2_CHANNEL5 60 -#define STM32_IRQ_COMP 64 -#define LSTM32_IRQ_PTIM1 65 -#define STM32_IRQ_LPTIM2 66 -#define STM32_IRQ_DMA2_CHANNEL6 68 -#define STM32_IRQ_DMA2_CHANNEL7 69 -#define STM32_IRQ_LPUART1 70 -#define STM32_IRQ_QUADSPI 71 -#define STM32_IRQ_I2C3_EV 72 -#define STM32_IRQ_I2C3_ER 73 -#define STM32_IRQ_SAI1 74 -#define STM32_IRQ_SWPMI1 76 -#define STM32_IRQ_TSC 77 -#define STM32_IRQ_RNG 80 -#define STM32_IRQ_FPU 81 -#define STM32_IRQ_CRS 82 - -/* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 -#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 -#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 - - -/* Peripheral base addresses */ -#define FLASH_BASE 0x08000000UL -#define FLASH_END 0x0803FFFFUL -#define FLASH_BANK1_END 0x0803FFFFUL -#define SRAM1_BASE 0x20000000UL -#define SRAM2_BASE 0x10000000UL -#define PERIPH_BASE 0x40000000UL -#define QSPI_BASE 0x90000000UL -#define QSPI_R_BASE 0xA0001000UL -#define SRAM1_BB_BASE 0x22000000UL -#define PERIPH_BB_BASE 0x42000000UL - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX 0x0000C000UL -#define SRAM2_SIZE 0x00004000UL -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) -#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \ - & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ - (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \ - (0x0000FFFFU)) << 10U)) - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) - -/*!< APB1 peripherals */ -#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) -#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) -#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) -#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) -#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) -#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) - -#define STM32_USART9_BASE STM32_LPUART1_BASE - -/*!< APB2 peripherals */ -#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) -#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL) -#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) -#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) -#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) -#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) -#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) -#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) - -/*!< AHB1 peripherals */ -#define STM32_DMA1_BASE (AHB1PERIPH_BASE) -#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) - -/*!< AHB2 peripherals */ -#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) -#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) -#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) -#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) -#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) -#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) -#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */ -#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) -#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) - -/* Debug MCU registers base address */ -#define STM32_DBGMCU_BASE 0xE0042000UL -#define STM32_PACKAGE_BASE 0x1FFF7500UL -#define STM32_UID_BASE 0x1FFF7590UL -#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL - -#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE -#define STM32_UNIQUE_ID_BASE STM32_UID_BASE -#define STM32_OPTB_BASE 0x1FFF7800 - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) - -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) - -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) - -#define PWR_CR1_LPMS_POS 0U -#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) -#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK -#define PWR_CR1_LPMS_STOP0 (0x00000000UL) -#define PWR_CR1_LPMS_STOP1_POS 0U -#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) -#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK -#define PWR_CR1_LPMS_STOP2_POS 1U -#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) -#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK -#define PWR_CR1_LPMS_STANDBY_POS 0U -#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) -#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK -#define PWR_CR1_LPMS_SHUTDOWN_POS 2U -#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) -#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK -#define PWR_CR1_VOS_POS 9U -#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS PWR_CR1_VOS_MSK -#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) - - -/* --- Macro usage in ec code --- */ -#define STM32_RCC_AHB2ENR_GPIOMASK \ - (STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \ - STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \ - STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN - -#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN -#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN -#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN -#ifndef CHIP_VARIANT_STM32L431X -#define STM32_RCC_PB2_TIM8 BIT(13) -#endif -#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN - -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) -#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) -#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) -#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) -#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) -#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) -#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) -#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) -#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) -#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) -#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) -#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) -#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) -#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) -#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) -/* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) - -#define STM32_RCC_PLLSAI1_SUPPORT -#define STM32_RCC_PLLP_SUPPORT -#define STM32_RCC_HSI48_SUPPORT -#define STM32_RCC_PLLP_DIV_2_31_SUPPORT -#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT - -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 - -/******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ -#define STM32_RCC_CR_MSION_POS 0U -#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) -#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK -#define STM32_RCC_CR_MSIRDY_POS 1U -#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) -#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK -#define STM32_RCC_CR_MSIPLLEN_POS 2U -#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) -#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK -#define STM32_RCC_CR_MSIRGSEL_POS 3U -#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) -#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK - -/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ -#define STM32_RCC_CR_MSIRANGE_POS 4U -#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) - -#define STM32_RCC_CR_HSION_POS 8U -#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) -#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK -#define STM32_RCC_CR_HSIKERON_POS 9U -#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) -#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK -#define STM32_RCC_CR_HSIRDY_POS 10U -#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) -#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK -#define STM32_RCC_CR_HSIASFS_POS 11U -#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) -#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK - -#define STM32_RCC_CR_HSEON_POS 16U -#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) -#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK -#define STM32_RCC_CR_HSERDY_POS 17U -#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) -#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK -#define STM32_RCC_CR_HSEBYP_POS 18U -#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) -#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK -#define STM32_RCC_CR_CSSON_POS 19U -#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) -#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK - -#define STM32_RCC_CR_PLLON_POS 24U -#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) -#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK -#define STM32_RCC_CR_PLLRDY_POS 25U -#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) -#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK -#define STM32_RCC_CR_PLLSAI1ON_POS 26U -#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) -#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK -#define STM32_RCC_CR_PLLSAI1RDY_POS 27U -#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) -#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK - -/******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ -/*!< MSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_MSICAL_POS 0U -#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK -#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) - -/*!< MSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_MSITRIM_POS 8U -#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK -#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) - -/*!< HSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_HSICAL_POS 16U -#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK -#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) - -/*!< HSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_HSITRIM_POS 24U -#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK -#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) - -/**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ -/*!< SW CONFIGURATION */ -#define STM32_RCC_CFGR_SW_POS 0U -#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK -#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) - -#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) -#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) -#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) - -/*!< SWS CONFIGURATION */ -#define STM32_RCC_CFGR_SWS_POS 2U -#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK -#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) - -#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) -#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) -#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) - -/*!< HPRE CONFIGURATION */ -#define STM32_RCC_CFGR_HPRE_POS 4U -#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK -#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) - -#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) -#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) -#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) -#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) -#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) -#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) -#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) -#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) - -/*!< PPRE1 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE1_POS 8U -#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK -#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) - -#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) -#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) -#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) -#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) - -/*!< PPRE2 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE2_POS 11U -#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK -#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) - -#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) -#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) -#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) -#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) - -#define STM32_RCC_CFGR_STOPWUCK_POS 15U -#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) -#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK - -/*!< MCOSEL CONFIGURATION */ -#define STM32_RCC_CFGR_MCOSEL_POS 24U -#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK -#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) - -#define STM32_RCC_CFGR_MCOPRE_POS 28U -#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK -#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) - -#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) - -/* LEGACY ALIASES */ -#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE -#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 -#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 -#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 -#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 -#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 - -/**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ -#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U -#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) -#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK - -#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U -#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \ - (0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK -#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U -#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \ - (0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK -#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U -#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ - (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK - -#define STM32_RCC_PLLCFGR_PLLM_POS 4U -#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK -#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) - -#define STM32_RCC_PLLCFGR_PLLN_POS 8U -#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK -#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) - -#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U -#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) -#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK -#define STM32_RCC_PLLCFGR_PLLP_POS 17U -#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) -#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK -#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U -#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) -#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK - -#define STM32_RCC_PLLCFGR_PLLQ_POS 21U -#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK -#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) - -#define STM32_RCC_PLLCFGR_PLLREN_POS 24U -#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) -#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK -#define STM32_RCC_PLLCFGR_PLLR_POS 25U -#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK -#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) - -#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U -#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK -#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) - -/**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \ - (0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \ - (0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \ - (0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \ - (0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \ - (0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \ - (0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \ - (0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ - (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \ - (0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \ - (0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \ - (0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \ - (0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \ - (0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \ - (0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \ - (0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \ - (0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \ - (0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \ - (0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) - -/************** BIT DEFINITION FOR STM32_RCC_CIER REGISTER ******************/ -#define STM32_RCC_CIER_LSIRDYIE_POS 0U -#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS) -#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK -#define STM32_RCC_CIER_LSERDYIE_POS 1U -#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS) -#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK -#define STM32_RCC_CIER_MSIRDYIE_POS 2U -#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS) -#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK -#define STM32_RCC_CIER_HSIRDYIE_POS 3U -#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS) -#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK -#define STM32_RCC_CIER_HSERDYIE_POS 4U -#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS) -#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK -#define STM32_RCC_CIER_PLLRDYIE_POS 5U -#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS) -#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK -#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U -#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \ - (0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS) -#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK -#define STM32_RCC_CIER_LSECSSIE_POS 9U -#define STM32_RCC_CIER_LSECSSIE_MSK (0x1UL << STM32_RCC_CIER_LSECSSIE_POS) -#define STM32_RCC_CIER_LSECSSIE STM32_RCC_CIER_LSECSSIE_MSK -#define STM32_RCC_CIER_HSI48RDYIE_POS 10U -#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS) -#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK - -/************** BIT DEFINITION FOR STM32_RCC_CIFR REGISTER ******************/ -#define STM32_RCC_CIFR_LSIRDYF_POS 0U -#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS) -#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK -#define STM32_RCC_CIFR_LSERDYF_POS 1U -#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS) -#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK -#define STM32_RCC_CIFR_MSIRDYF_POS 2U -#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS) -#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK -#define STM32_RCC_CIFR_HSIRDYF_POS 3U -#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS) -#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK -#define STM32_RCC_CIFR_HSERDYF_POS 4U -#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS) -#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK -#define STM32_RCC_CIFR_PLLRDYF_POS 5U -#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS) -#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK -#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U -#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS) -#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK -#define STM32_RCC_CIFR_CSSF_POS 8U -#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS) -#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK -#define STM32_RCC_CIFR_LSECSSF_POS 9U -#define STM32_RCC_CIFR_LSECSSF_MSK (0x1UL << STM32_RCC_CIFR_LSECSSF_POS) -#define STM32_RCC_CIFR_LSECSSF STM32_RCC_CIFR_LSECSSF_MSK -#define STM32_RCC_CIFR_HSI48RDYF_POS 10U -#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS) -#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK - -/************** BIT DEFINITION FOR STM32_RCC_CICR REGISTER ******************/ -#define STM32_RCC_CICR_LSIRDYC_POS 0U -#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS) -#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK -#define STM32_RCC_CICR_LSERDYC_POS 1U -#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS) -#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK -#define STM32_RCC_CICR_MSIRDYC_POS 2U -#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS) -#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK -#define STM32_RCC_CICR_HSIRDYC_POS 3U -#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS) -#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK -#define STM32_RCC_CICR_HSERDYC_POS 4U -#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS) -#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK -#define STM32_RCC_CICR_PLLRDYC_POS 5U -#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS) -#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK -#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U -#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS) -#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK -#define STM32_RCC_CICR_CSSC_POS 8U -#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS) -#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK -#define STM32_RCC_CICR_LSECSSC_POS 9U -#define STM32_RCC_CICR_LSECSSC_MSK (0x1UL << STM32_RCC_CICR_LSECSSC_POS) -#define STM32_RCC_CICR_LSECSSC STM32_RCC_CICR_LSECSSC_MSK -#define STM32_RCC_CICR_HSI48RDYC_POS 10U -#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS) -#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER **************/ -#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U -#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS) -#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK -#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U -#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS) -#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK -#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U -#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \ - (0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS) -#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK -#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U -#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS) -#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK -#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U -#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS) -#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER **************/ -#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U -#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS) -#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK -#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U -#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK -#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U -#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK -#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U -#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS) -#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK -#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U -#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS) -#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK -#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U -#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK -#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U -#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS) -#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK -#define STM32_RCC_AHB2RSTR_AESRST_POS 16U -#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS) -#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK -#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U -#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS) -#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK - -/************* BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER **************/ -#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U -#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS) -#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER **************/ -#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U -#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS) -#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK -#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U -#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS) -#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK -#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U -#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS) -#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK -#define STM32_RCC_APB1RSTR1_LCDRST_POS 9U -#define STM32_RCC_APB1RSTR1_LCDRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_LCDRST_POS) -#define STM32_RCC_APB1RSTR1_LCDRST STM32_RCC_APB1RSTR1_LCDRST_MSK -#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U -#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS) -#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK -#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U -#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS) -#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK -#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U -#define STM32_RCC_APB1RSTR1_USART2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS) -#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK -#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U -#define STM32_RCC_APB1RSTR1_USART3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS) -#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK -#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U -#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS) -#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK -#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U -#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS) -#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK -#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U -#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS) -#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK -#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U -#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS) -#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK -#define STM32_RCC_APB1RSTR1_CAN1RST_POS 25U -#define STM32_RCC_APB1RSTR1_CAN1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_CAN1RST_POS) -#define STM32_RCC_APB1RSTR1_CAN1RST STM32_RCC_APB1RSTR1_CAN1RST_MSK -#define STM32_RCC_APB1RSTR1_USBFSRST_POS 26U -#define STM32_RCC_APB1RSTR1_USBFSRST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USBFSRST_POS) -#define STM32_RCC_APB1RSTR1_USBFSRST STM32_RCC_APB1RSTR1_USBFSRST_MSK -#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U -#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS) -#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK -#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U -#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS) -#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK -#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U -#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS) -#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK -#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U -#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS) -#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER **************/ -#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U -#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS) -#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK -#define STM32_RCC_APB1RSTR2_SWPMI1RST_POS 2U -#define STM32_RCC_APB1RSTR2_SWPMI1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_SWPMI1RST_POS) -#define STM32_RCC_APB1RSTR2_SWPMI1RST STM32_RCC_APB1RSTR2_SWPMI1RST_MSK -#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U -#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS) -#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK - -/************** BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER **************/ -#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U -#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS) -#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK -#define STM32_RCC_APB2RSTR_SDMMC1RST_POS 10U -#define STM32_RCC_APB2RSTR_SDMMC1RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_SDMMC1RST_POS) -#define STM32_RCC_APB2RSTR_SDMMC1RST STM32_RCC_APB2RSTR_SDMMC1RST_MSK -#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U -#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS) -#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK -#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U -#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS) -#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK -#define STM32_RCC_APB2RSTR_USART1RST_POS 14U -#define STM32_RCC_APB2RSTR_USART1RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS) -#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK -#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U -#define STM32_RCC_APB2RSTR_TIM15RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS) -#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK -#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U -#define STM32_RCC_APB2RSTR_TIM16RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS) -#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK -#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U -#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS) -#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER ***************/ -#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U -#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS) -#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK -#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U -#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS) -#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK -#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U -#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS) -#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK -#define STM32_RCC_AHB1ENR_CRCEN_POS 12U -#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS) -#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK -#define STM32_RCC_AHB1ENR_TSCEN_POS 16U -#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS) -#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK - -/*************** BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER *********/ -#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U -#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS) -#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK -#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U -#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS) -#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK -#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U -#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS) -#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK -#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U -#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS) -#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK -#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U -#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS) -#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK -#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U -#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS) -#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK -#define STM32_RCC_AHB2ENR_ADCEN_POS 13U -#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS) -#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK -#define STM32_RCC_AHB2ENR_AESEN_POS 16U -#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS) -#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK -#define STM32_RCC_AHB2ENR_RNGEN_POS 18U -#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS) -#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER ***************/ -#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U -#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS) -#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER **************/ -#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U -#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS) -#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK -#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U -#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS) -#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK -#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U -#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS) -#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK -#define STM32_RCC_APB1ENR1_LCDEN_POS 9U -#define STM32_RCC_APB1ENR1_LCDEN_MSK (0x1UL << STM32_RCC_APB1ENR1_LCDEN_POS) -#define STM32_RCC_APB1ENR1_LCDEN STM32_RCC_APB1ENR1_LCDEN_MSK -#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U -#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS) -#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK -#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U -#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS) -#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK -#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U -#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS) -#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK -#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U -#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS) -#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK -#define STM32_RCC_APB1ENR1_USART2EN_POS 17U -#define STM32_RCC_APB1ENR1_USART2EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS) -#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK -#define STM32_RCC_APB1ENR1_USART3EN_POS 18U -#define STM32_RCC_APB1ENR1_USART3EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS) -#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK -#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U -#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS) -#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK -#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U -#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS) -#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK -#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U -#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS) -#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK -#define STM32_RCC_APB1ENR1_CRSEN_POS 24U -#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS) -#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK -#define STM32_RCC_APB1ENR1_CAN1EN_POS 25U -#define STM32_RCC_APB1ENR1_CAN1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_CAN1EN_POS) -#define STM32_RCC_APB1ENR1_CAN1EN STM32_RCC_APB1ENR1_CAN1EN_MSK -#define STM32_RCC_APB1ENR1_USBFSEN_POS 26U -#define STM32_RCC_APB1ENR1_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_USBFSEN_POS) -#define STM32_RCC_APB1ENR1_USBFSEN STM32_RCC_APB1ENR1_USBFSEN_MSK -#define STM32_RCC_APB1ENR1_PWREN_POS 28U -#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS) -#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK -#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U -#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS) -#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK -#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U -#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS) -#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK -#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U -#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS) -#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK - -/************ BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER **************/ -#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U -#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS) -#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK -#define STM32_RCC_APB1ENR2_SWPMI1EN_POS 2U -#define STM32_RCC_APB1ENR2_SWPMI1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_SWPMI1EN_POS) -#define STM32_RCC_APB1ENR2_SWPMI1EN STM32_RCC_APB1ENR2_SWPMI1EN_MSK -#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U -#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS) -#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER ***************/ -#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U -#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS) -#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK -#define STM32_RCC_APB2ENR_FWEN_POS 7U -#define STM32_RCC_APB2ENR_FWEN_MSK (0x1UL << STM32_RCC_APB2ENR_FWEN_POS) -#define STM32_RCC_APB2ENR_FWEN STM32_RCC_APB2ENR_FWEN_MSK -#define STM32_RCC_APB2ENR_SDMMC1EN_POS 10U -#define STM32_RCC_APB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SDMMC1EN_POS) -#define STM32_RCC_APB2ENR_SDMMC1EN STM32_RCC_APB2ENR_SDMMC1EN_MSK -#define STM32_RCC_APB2ENR_TIM1EN_POS 11U -#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS) -#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK -#define STM32_RCC_APB2ENR_SPI1EN_POS 12U -#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS) -#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK -#define STM32_RCC_APB2ENR_USART1EN_POS 14U -#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS) -#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK -#define STM32_RCC_APB2ENR_TIM15EN_POS 16U -#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS) -#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK -#define STM32_RCC_APB2ENR_TIM16EN_POS 17U -#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS) -#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK -#define STM32_RCC_APB2ENR_SAI1EN_POS 21U -#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS) -#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK - -/************ BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER ***************/ -#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U -#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS) -#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK -#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U -#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS) -#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK -#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U -#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS) -#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK -#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U -#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS) -#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK -#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U -#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS) -#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK -#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U -#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS) -#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER *************/ -#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U -#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U -#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U -#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U -#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U -#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U -#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK -#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U -#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS) -#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK -#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U -#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS) -#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK -#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U -#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS) -#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK -#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U -#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS) -#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER *************/ -#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U -#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \ - (0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS) -#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER *************/ -#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U -#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U -#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U -#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK -#define STM32_RCC_APB1SMENR1_LCDSMEN_POS 9U -#define STM32_RCC_APB1SMENR1_LCDSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_LCDSMEN_POS) -#define STM32_RCC_APB1SMENR1_LCDSMEN STM32_RCC_APB1SMENR1_LCDSMEN_MSK -#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U -#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS) -#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK -#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U -#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS) -#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK -#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U -#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS) -#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK -#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U -#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS) -#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK -#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U -#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS) -#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK -#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U -#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS) -#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK -#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U -#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS) -#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK -#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U -#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS) -#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK -#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U -#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS) -#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK -#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U -#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS) -#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK -#define STM32_RCC_APB1SMENR1_CAN1SMEN_POS 25U -#define STM32_RCC_APB1SMENR1_CAN1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_CAN1SMEN_POS) -#define STM32_RCC_APB1SMENR1_CAN1SMEN STM32_RCC_APB1SMENR1_CAN1SMEN_MSK -#define STM32_RCC_APB1SMENR1_USBFSSMEN_POS 26U -#define STM32_RCC_APB1SMENR1_USBFSSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USBFSSMEN_POS) -#define STM32_RCC_APB1SMENR1_USBFSSMEN STM32_RCC_APB1SMENR1_USBFSSMEN_MSK -#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U -#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS) -#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK -#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U -#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS) -#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK -#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U -#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS) -#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK -#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U -#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS) -#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER *************/ -#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U -#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS) -#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK -#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS 2U -#define STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_SWPMI1SMEN_POS) -#define STM32_RCC_APB1SMENR2_SWPMI1SMEN STM32_RCC_APB1SMENR2_SWPMI1SMEN_MSK -#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U -#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS) -#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK - -/************ BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER *************/ -#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U -#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS) -#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK -#define STM32_RCC_APB2SMENR_SDMMC1SMEN_POS 10U -#define STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SDMMC1SMEN_POS) -#define STM32_RCC_APB2SMENR_SDMMC1SMEN STM32_RCC_APB2SMENR_SDMMC1SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U -#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK -#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U -#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS) -#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK -#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U -#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS) -#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U -#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U -#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK -#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U -#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS) -#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK - -/************* BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER ******************/ -#define STM32_RCC_CCIPR_USART1SEL_POS 0U -#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS) -#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK -#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS) -#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS) - -#define STM32_RCC_CCIPR_USART2SEL_POS 2U -#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS) -#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK -#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS) -#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS) - -#define STM32_RCC_CCIPR_USART3SEL_POS 4U -#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS) -#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK -#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS) -#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS) - -#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U -#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS) -#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK -#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS) -#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS) - -#define STM32_RCC_CCIPR_I2C1SEL_POS 12U -#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS) -#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK -#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS) -#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS) - -#define STM32_RCC_CCIPR_I2C2SEL_POS 14U -#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS) -#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK -#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS) -#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS) - -#define STM32_RCC_CCIPR_I2C3SEL_POS 16U -#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS) -#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK -#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS) -#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U -#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) -#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK -#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) -#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U -#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) -#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK -#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) -#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) - -#define STM32_RCC_CCIPR_SAI1SEL_POS 22U -#define STM32_RCC_CCIPR_SAI1SEL_MSK (0x3UL << STM32_RCC_CCIPR_SAI1SEL_POS) -#define STM32_RCC_CCIPR_SAI1SEL STM32_RCC_CCIPR_SAI1SEL_MSK -#define STM32_RCC_CCIPR_SAI1SEL_0 (0x1UL << STM32_RCC_CCIPR_SAI1SEL_POS) -#define STM32_RCC_CCIPR_SAI1SEL_1 (0x2UL << STM32_RCC_CCIPR_SAI1SEL_POS) - -#define STM32_RCC_CCIPR_CLK48SEL_POS 26U -#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS) -#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK -#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS) -#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS) - -#define STM32_RCC_CCIPR_ADCSEL_POS 28U -#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS) -#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK -#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS) -#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS) - -#define STM32_RCC_CCIPR_SWPMI1SEL_POS 30U -#define STM32_RCC_CCIPR_SWPMI1SEL_MSK (0x1UL << STM32_RCC_CCIPR_SWPMI1SEL_POS) -#define STM32_RCC_CCIPR_SWPMI1SEL STM32_RCC_CCIPR_SWPMI1SEL_MSK - -/************** BIT DEFINITION FOR STM32_RCC_BDCR REGISTER ******************/ -#define STM32_RCC_BDCR_LSEBYP_POS 2U -#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS) -#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK - -#define STM32_RCC_BDCR_LSEDRV_POS 3U -#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS) -#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK -#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS) -#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS) - -#define STM32_RCC_BDCR_LSECSSON_POS 5U -#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS) -#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK -#define STM32_RCC_BDCR_LSECSSD_POS 6U -#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS) -#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK - -#define STM32_RCC_BDCR_RTCSEL_POS 8U -#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS) -#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK -#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS) -#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS) - -#define STM32_RCC_BDCR_LSCOEN_POS 24U -#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS) -#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK -#define STM32_RCC_BDCR_LSCOSEL_POS 25U -#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS) -#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK - -/************** BIT DEFINITION FOR STM32_RCC_CSR REGISTER *******************/ -#define STM32_RCC_CSR_LSION_POS 0U -#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS) -#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK -#define STM32_RCC_CSR_LSIRDY_POS 1U -#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS) -#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK - -#define STM32_RCC_CSR_MSISRANGE_POS 8U -#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK -#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS) - -#define STM32_RCC_CSR_RMVF_POS 23U -#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS) -#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK -#define STM32_RCC_CSR_FWRSTF_POS 24U -#define STM32_RCC_CSR_FWRSTF_MSK (0x1UL << STM32_RCC_CSR_FWRSTF_POS) -#define STM32_RCC_CSR_FWRSTF STM32_RCC_CSR_FWRSTF_MSK -#define STM32_RCC_CSR_OBLRSTF_POS 25U -#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS) -#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK -#define STM32_RCC_CSR_PINRSTF_POS 26U -#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS) -#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK -#define STM32_RCC_CSR_BORRSTF_POS 27U -#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS) -#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK -#define STM32_RCC_CSR_SFTRSTF_POS 28U -#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS) -#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK -#define STM32_RCC_CSR_IWDGRSTF_POS 29U -#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS) -#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK -#define STM32_RCC_CSR_WWDGRSTF_POS 30U -#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS) -#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK -#define STM32_RCC_CSR_LPWRRSTF_POS 31U -#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS) -#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK - -/************** Bit definition for STM32_RCC_CRRCR register *****************/ -#define STM32_RCC_CRRCR_HSI48ON_POS 0U -#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS) -#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK -#define STM32_RCC_CRRCR_HSI48RDY_POS 1U -#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS) -#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK - -/*!< HSI48CAL configuration */ -#define STM32_RCC_CRRCR_HSI48CAL_POS 7U -#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK -#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) - -/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_PWREN BIT(28) - -#define STM32_RCC_PB2_SYSCFGEN BIT(0) -#define STM32_RCC_PB2_USART1 BIT(14) - -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) - -#define STM32_RCC_HB2_GPIOA BIT(0) -#define STM32_RCC_HB2_GPIOB BIT(1) -#define STM32_RCC_HB2_GPIOC BIT(2) -#define STM32_RCC_HB2_GPIOD BIT(3) -#define STM32_RCC_HB2_GPIOE BIT(4) -#define STM32_RCC_HB2_GPIOH BIT(7) -#define STM32_RCC_HB2_ADC1 BIT(13) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xff000000 -#define RESET_CAUSE_RMVF BIT(23) -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF BIT(8) -#define RESET_CAUSE_SBF_CLR BIT(8) - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_WUTE BIT(10) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_CR_WUTIE BIT(14) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_WUTWF BIT(2) -#define STM32_RTC_ISR_INITS BIT(4) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_ISR_WUTF BIT(9) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_RTC_CLEAR_FLAG(x) \ - (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ - (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -#define RTC_TR_PM_POS 22U -#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) -#define RTC_TR_PM RTC_TR_PM_MSK -#define RTC_TR_HT_POS 20U -#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) -#define RTC_TR_HT RTC_TR_HT_MSK -#define RTC_TR_HU_POS 16U -#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) -#define RTC_TR_HU RTC_TR_HU_MSK -#define RTC_TR_MNT_POS 12U -#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) -#define RTC_TR_MNT RTC_TR_MNT_MSK -#define RTC_TR_MNU_POS 8U -#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) -#define RTC_TR_MNU RTC_TR_MNU_MSK -#define RTC_TR_ST_POS 4U -#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) -#define RTC_TR_ST RTC_TR_ST_MSK -#define RTC_TR_SU_POS 0U -#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) -#define RTC_TR_SU RTC_TR_SU_MSK - - - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned int sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned int crcpr; - unsigned int rxcrcr; - unsigned int txcrcr; - unsigned int i2scfgr; /* STM32L only */ - unsigned int i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) -#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) -/* Minimum number of bytes that can be written to flash */ -#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE - -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(18) - -/* --- ADC --- */ -#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC1_ISR_ADRDY BIT(0) -#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC1_IER_AWDIE BIT(7) -#define STM32_ADC1_IER_OVRIE BIT(4) -#define STM32_ADC1_IER_EOSEQIE BIT(3) -#define STM32_ADC1_IER_EOCIE BIT(2) -#define STM32_ADC1_IER_EOSMPIE BIT(1) -#define STM32_ADC1_IER_ADRDYIE BIT(0) - -#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC1_CR_ADEN BIT(0) -#define STM32_ADC1_CR_ADDIS BIT(1) -#define STM32_ADC1_CR_ADSTP BIT(4) -#define STM32_ADC1_CR_ADVREGEN BIT(28) -#define STM32_ADC1_CR_DEEPPWD BIT(29) -#define STM32_ADC1_CR_ADCAL BIT(31) -#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) -/* Analog watchdog channel selection */ -#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) -#define STM32_ADC1_CFGR_AWDEN BIT(23) -#define STM32_ADC1_CFGR_AWDSGL BIT(22) -#define STM32_ADC1_CFGR_AUTDLY BIT(14) -/* Selects single vs continuous */ -#define STM32_ADC1_CFGR_CONT BIT(13) -/* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC1_CFGR_OVRMOD BIT(12) -/* External trigger polarity selection */ -#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) -#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) -#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) -#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) -#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) -#define STM32_ADC1_CFGR_ALIGN BIT(5) -/* External trigger selection */ -#define STM32_ADC1_CFGR_TRG0 (0 << 6) -#define STM32_ADC1_CFGR_TRG1 (1 << 6) -#define STM32_ADC1_CFGR_TRG2 (2 << 6) -#define STM32_ADC1_CFGR_TRG3 (3 << 6) -#define STM32_ADC1_CFGR_TRG4 (4 << 6) -#define STM32_ADC1_CFGR_TRG5 (5 << 6) -#define STM32_ADC1_CFGR_TRG6 (6 << 6) -#define STM32_ADC1_CFGR_TRG7 (7 << 6) -#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) -/* Selects circular vs one-shot */ -#define STM32_ADC1_CFGR_DMACFG BIT(1) -#define STM32_ADC1_CFGR_DMAEN BIT(0) -#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) -/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) -#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) -#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) -#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) -#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - STM32_DMAC_CH15 = 14, - - /* Channel functions */ - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_USART1_TX = STM32_DMAC_CH14, - STM32_DMAC_USART1_RX = STM32_DMAC_CH15, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, - STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, - STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - STM32_DMAC_COUNT = 15, -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - -#endif /* !__ASSEMBLER__ */ - diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h deleted file mode 100644 index d418362fce..0000000000 --- a/chip/stm32/registers-stm32l5.h +++ /dev/null @@ -1,2388 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32L5 family of chips - * - * This header file should not be included directly. - * Please include registers.h instead. - * - * Known Chip Variants - * - STM32L552 - */ - -#ifndef __CROS_EC_REGISTERS_H -#error "This header file should not be included directly." -#endif - -/****** STM32 specific Interrupt Numbers ********/ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 6 -#define STM32_IRQ_FLASH_S 7 -#define STM32_IRQ_RCC 9 -#define STM32_IRQ_RCC_S 10 -#define STM32_IRQ_EXTI0 11 -#define STM32_IRQ_EXTI1 12 -#define STM32_IRQ_EXTI2 13 -#define STM32_IRQ_EXTI3 14 -#define STM32_IRQ_EXTI4 15 -#define STM32_IRQ_EXTI5 16 -#define STM32_IRQ_EXTI6 17 -#define STM32_IRQ_EXTI7 18 -#define STM32_IRQ_EXTI8 19 -#define STM32_IRQ_EXTI9 20 -#define STM32_IRQ_EXTI10 21 -#define STM32_IRQ_EXTI11 22 -#define STM32_IRQ_EXTI12 23 -#define STM32_IRQ_EXTI13 24 -#define STM32_IRQ_EXTI14 25 -#define STM32_IRQ_EXTI15 26 -#define STM32_IRQ_DMAMUX_OVR 27 -#define STM32_IRQ_DMAMUX_OVR_S 28 -#define STM32_IRQ_DMA_CHANNEL_1 29 -#define STM32_IRQ_DMA_CHANNEL_2 30 -#define STM32_IRQ_DMA_CHANNEL_3 31 -#define STM32_IRQ_DMA_CHANNEL_4 32 -#define STM32_IRQ_DMA_CHANNEL_5 33 -#define STM32_IRQ_DMA_CHANNEL_6 34 -#define STM32_IRQ_DMA_CHANNEL_7 35 -#define STM32_IRQ_DMA_CHANNEL_8 36 -#define STM32_IRQ_ADC1 37 -#define STM32_IRQ_TIM1_BRK 41 -#define STM32_IRQ_TIM1_UP 42 -#define STM32_IRQ_TIM1_TRG_COM 43 -#define STM32_IRQ_TIM1_CC 44 -#define STM32_IRQ_TIM2 45 -#define STM32_IRQ_TIM3 46 -#define STM32_IRQ_TIM4 47 -#define STM32_IRQ_TIM5 48 -#define STM32_IRQ_TIM6 49 -#define STM32_IRQ_TIM7 50 -#define STM32_IRQ_TIM8_BRK 51 -#define STM32_IRQ_TIM8_UP 52 -#define STM32_IRQ_TIM8_TRG_COM 53 -#define STM32_IRQ_TIM8_CC 54 -#define STM32_IRQ_I2C1_EV 55 -#define STM32_IRQ_I2C1_ER 56 -#define STM32_IRQ_I2C2_EV 57 -#define STM32_IRQ_I2C2_ER 58 -#define STM32_IRQ_SPI1 59 -#define STM32_IRQ_SPI2 60 -#define STM32_IRQ_USART1 61 -#define STM32_IRQ_USART2 62 -#define STM32_IRQ_USART3 63 -#define STM32_IRQ_USART4 64 -#define STM32_IRQ_USART5 65 -#define STM32_IRQ_LPUART 66 -#define STM32_IRQ_LPTIM1 67 -#define STM32_IRQ_LPTIM2 68 -#define STM32_IRQ_TIM15 69 -#define STM32_IRQ_TIM16 70 -#define STM32_IRQ_TIM17 71 -#define STM32_IRQ_COMP 72 -#define STM32_IRQ_USB_FS 73 -#define STM32_IRQ_CRS 74 -#define STM32_IRQ_FMC 75 -#define STM32_IRQ_DMA2_CHANNEL1 80 -#define STM32_IRQ_DMA2_CHANNEL2 81 -#define STM32_IRQ_DMA2_CHANNEL3 82 -#define STM32_IRQ_DMA2_CHANNEL4 83 -#define STM32_IRQ_DMA2_CHANNEL5 84 -#define STM32_IRQ_DMA2_CHANNEL6 85 -#define STM32_IRQ_DMA2_CHANNEL7 86 -#define STM32_IRQ_DMA2_CHANNEL8 87 - -/* To simplify code generation, define DMA channel 9..16 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 -#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 -#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8 - -/* aliases for easier code sharing */ -#define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV -#define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV -#define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV -#define STM32_IRQ_USB_LP STM32_IRQ_USB_FS - - -#define PERIPH_BASE 0x40000000UL - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) - -/*!< APB1 peripherals */ -#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) -#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL) -#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL) -#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL) -#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL) - -/*!< APB2 peripherals */ -#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL) -#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) -#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) - -/*!< AHB1 peripherals */ -#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL) -#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) - -/*!< AHB2 peripherals */ -#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL) -#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL) -#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL) -#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL) -#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL) -#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL) -#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL) -#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL) -#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL) - -/* Debug MCU registers base address */ -#define STM32_PACKAGE_BASE 0x0BFA0500UL -#define STM32_UID_BASE 0x0BFA0590UL -#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL - -#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE -#define STM32_UNIQUE_ID_BASE STM32_UID_BASE - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) - -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) - -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) -/* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -/* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF - -/* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) - -#define PWR_CR1_LPMS_POS 0U -#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) -#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK -#define PWR_CR1_LPMS_STOP0 (0x00000000UL) -#define PWR_CR1_LPMS_STOP1_POS 0U -#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) -#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK -#define PWR_CR1_LPMS_STOP2_POS 1U -#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) -#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK -#define PWR_CR1_LPMS_STANDBY_POS 0U -#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) -#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK -#define PWR_CR1_LPMS_SHUTDOWN_POS 2U -#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) -#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK -#define PWR_CR1_VOS_POS 9U -#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS PWR_CR1_VOS_MSK -#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) - - -/* --- Macro usage in ec code --- */ -#define STM32_RCC_AHB2ENR_GPIOMASK \ - (STM32_RCC_AHB2ENR_GPIOAEN | STM32_RCC_AHB2ENR_GPIOBEN | \ - STM32_RCC_AHB2ENR_GPIOCEN | STM32_RCC_AHB2ENR_GPIODEN | \ - STM32_RCC_AHB2ENR_GPIOEEN | STM32_RCC_AHB2ENR_GPIOHEN) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN - -#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN -#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN -#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN -#ifndef CHIP_VARIANT_STM32L431X -#define STM32_RCC_PB2_TIM8 BIT(13) -#endif -#define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN - -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) -#define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) -#define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) -#define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) -#define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) -#define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) -#define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) -#define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) -#define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) -#define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) -#define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) -#define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) -#define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) -#define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) -#define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) -#define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) -/* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) - -#define STM32_RCC_PLLSAI1_SUPPORT -#define STM32_RCC_PLLP_SUPPORT -#define STM32_RCC_HSI48_SUPPORT -#define STM32_RCC_PLLP_DIV_2_31_SUPPORT -#define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT - -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 - -/******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ -#define STM32_RCC_CR_MSION_POS 0U -#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) -#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK -#define STM32_RCC_CR_MSIRDY_POS 1U -#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) -#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK -#define STM32_RCC_CR_MSIPLLEN_POS 2U -#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) -#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK -#define STM32_RCC_CR_MSIRGSEL_POS 3U -#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) -#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK - -/*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ -#define STM32_RCC_CR_MSIRANGE_POS 4U -#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) - -#define STM32_RCC_CR_HSION_POS 8U -#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) -#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK -#define STM32_RCC_CR_HSIKERON_POS 9U -#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) -#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK -#define STM32_RCC_CR_HSIRDY_POS 10U -#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) -#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK -#define STM32_RCC_CR_HSIASFS_POS 11U -#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) -#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK - -#define STM32_RCC_CR_HSEON_POS 16U -#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) -#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK -#define STM32_RCC_CR_HSERDY_POS 17U -#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) -#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK -#define STM32_RCC_CR_HSEBYP_POS 18U -#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) -#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK -#define STM32_RCC_CR_CSSON_POS 19U -#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) -#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK - -#define STM32_RCC_CR_PLLON_POS 24U -#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) -#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK -#define STM32_RCC_CR_PLLRDY_POS 25U -#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) -#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK -#define STM32_RCC_CR_PLLSAI1ON_POS 26U -#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) -#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK -#define STM32_RCC_CR_PLLSAI1RDY_POS 27U -#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) -#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK - -/******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ -/*!< MSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_MSICAL_POS 0U -#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK -#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) - -/*!< MSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_MSITRIM_POS 8U -#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK -#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) - -/*!< HSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_HSICAL_POS 16U -#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK -#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) - -/*!< HSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_HSITRIM_POS 24U -#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK -#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) - -/**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ -/*!< SW CONFIGURATION */ -#define STM32_RCC_CFGR_SW_POS 0U -#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK -#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) - -#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) -#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) -#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) - -/*!< SWS CONFIGURATION */ -#define STM32_RCC_CFGR_SWS_POS 2U -#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK -#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) - -#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) -#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) -#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) - -/*!< HPRE CONFIGURATION */ -#define STM32_RCC_CFGR_HPRE_POS 4U -#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK -#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) - -#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) -#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) -#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) -#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) -#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) -#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) -#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) -#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) - -/*!< PPRE1 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE1_POS 8U -#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK -#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) - -#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) -#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) -#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) -#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) - -/*!< PPRE2 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE2_POS 11U -#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK -#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) - -#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) -#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) -#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) -#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) - -#define STM32_RCC_CFGR_STOPWUCK_POS 15U -#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) -#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK - -/*!< MCOSEL CONFIGURATION */ -#define STM32_RCC_CFGR_MCOSEL_POS 24U -#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK -#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) - -#define STM32_RCC_CFGR_MCOPRE_POS 28U -#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK -#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) - -#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) - -/* LEGACY ALIASES */ -#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE -#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 -#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 -#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 -#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 -#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 - -/**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ -#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U -#define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) -#define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK - -#define STM32_RCC_PLLCFGR_PLLSRC_MSI_POS 0U -#define STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK \ - (0x1UL << STM32_RCC_PLLCFGR_PLLSRC_MSI_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_MSI STM32_RCC_PLLCFGR_PLLSRC_MSI_MSK -#define STM32_RCC_PLLCFGR_PLLSRC_HSI_POS 1U -#define STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK \ - (0x1UL << STM32_RCC_PLLCFGR_PLLSRC_HSI_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSI STM32_RCC_PLLCFGR_PLLSRC_HSI_MSK -#define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U -#define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ - (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK - -#define STM32_RCC_PLLCFGR_PLLM_POS 4U -#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK -#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) - -#define STM32_RCC_PLLCFGR_PLLN_POS 8U -#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK -#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) - -#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U -#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) -#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK -#define STM32_RCC_PLLCFGR_PLLP_POS 17U -#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) -#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK -#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U -#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) -#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK - -#define STM32_RCC_PLLCFGR_PLLQ_POS 21U -#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK -#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) - -#define STM32_RCC_PLLCFGR_PLLREN_POS 24U -#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) -#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK -#define STM32_RCC_PLLCFGR_PLLR_POS 25U -#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK -#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) - -#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U -#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK -#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) - -/**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK \ - (0x7FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N STM32_RCC_PLLSAI1CFGR_PLLSAI1N_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_0 \ - (0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_1 \ - (0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_2 \ - (0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_3 \ - (0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_4 \ - (0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_5 \ - (0x20UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ - (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS 17U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1P_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1P STM32_RCC_PLLSAI1CFGR_PLLSAI1P_MSK - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS 20U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN STM32_RCC_PLLSAI1CFGR_PLLSAI1QEN_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS 21U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK \ - (0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_0 \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_1 \ - (0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1Q_POS) - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS 24U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1REN STM32_RCC_PLLSAI1CFGR_PLLSAI1REN_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS 25U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK \ - (0x3UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R STM32_RCC_PLLSAI1CFGR_PLLSAI1R_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_0 \ - (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1R_1 \ - (0x2UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1R_POS) - -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS 27U -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK \ - (0x1FUL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_MSK -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 \ - (0x01UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 \ - (0x02UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 \ - (0x04UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 \ - (0x08UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 \ - (0x10UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PDIV_POS) - -/************** BIT DEFINITION FOR STM32_RCC_CIER REGISTER ******************/ -#define STM32_RCC_CIER_LSIRDYIE_POS 0U -#define STM32_RCC_CIER_LSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_LSIRDYIE_POS) -#define STM32_RCC_CIER_LSIRDYIE STM32_RCC_CIER_LSIRDYIE_MSK -#define STM32_RCC_CIER_LSERDYIE_POS 1U -#define STM32_RCC_CIER_LSERDYIE_MSK (0x1UL << STM32_RCC_CIER_LSERDYIE_POS) -#define STM32_RCC_CIER_LSERDYIE STM32_RCC_CIER_LSERDYIE_MSK -#define STM32_RCC_CIER_MSIRDYIE_POS 2U -#define STM32_RCC_CIER_MSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_MSIRDYIE_POS) -#define STM32_RCC_CIER_MSIRDYIE STM32_RCC_CIER_MSIRDYIE_MSK -#define STM32_RCC_CIER_HSIRDYIE_POS 3U -#define STM32_RCC_CIER_HSIRDYIE_MSK (0x1UL << STM32_RCC_CIER_HSIRDYIE_POS) -#define STM32_RCC_CIER_HSIRDYIE STM32_RCC_CIER_HSIRDYIE_MSK -#define STM32_RCC_CIER_HSERDYIE_POS 4U -#define STM32_RCC_CIER_HSERDYIE_MSK (0x1UL << STM32_RCC_CIER_HSERDYIE_POS) -#define STM32_RCC_CIER_HSERDYIE STM32_RCC_CIER_HSERDYIE_MSK -#define STM32_RCC_CIER_PLLRDYIE_POS 5U -#define STM32_RCC_CIER_PLLRDYIE_MSK (0x1UL << STM32_RCC_CIER_PLLRDYIE_POS) -#define STM32_RCC_CIER_PLLRDYIE STM32_RCC_CIER_PLLRDYIE_MSK -#define STM32_RCC_CIER_PLLSAI1RDYIE_POS 6U -#define STM32_RCC_CIER_PLLSAI1RDYIE_MSK \ - (0x1UL << STM32_RCC_CIER_PLLSAI1RDYIE_POS) -#define STM32_RCC_CIER_PLLSAI1RDYIE STM32_RCC_CIER_PLLSAI1RDYIE_MSK -#define STM32_RCC_CIER_PLLSAI2RDYIE_POS 7U -#define STM32_RCC_CIER_PLLSAI2RDYIE_MSK \ - (0x1UL << STM32_RCC_CIER_PLLSAI2RDYIE_POS) -#define STM32_RCC_CIER_PLLSAI2RDYIE STM32_RCC_CIER_PLLSAI2RDYIE_MSK -#define STM32_RCC_CIER_HSI48RDYIE_POS 10U -#define STM32_RCC_CIER_HSI48RDYIE_MSK (0x1UL << STM32_RCC_CIER_HSI48RDYIE_POS) -#define STM32_RCC_CIER_HSI48RDYIE STM32_RCC_CIER_HSI48RDYIE_MSK - -/************** BIT DEFINITION FOR STM32_RCC_CIFR REGISTER ******************/ -#define STM32_RCC_CIFR_LSIRDYF_POS 0U -#define STM32_RCC_CIFR_LSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_LSIRDYF_POS) -#define STM32_RCC_CIFR_LSIRDYF STM32_RCC_CIFR_LSIRDYF_MSK -#define STM32_RCC_CIFR_LSERDYF_POS 1U -#define STM32_RCC_CIFR_LSERDYF_MSK (0x1UL << STM32_RCC_CIFR_LSERDYF_POS) -#define STM32_RCC_CIFR_LSERDYF STM32_RCC_CIFR_LSERDYF_MSK -#define STM32_RCC_CIFR_MSIRDYF_POS 2U -#define STM32_RCC_CIFR_MSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_MSIRDYF_POS) -#define STM32_RCC_CIFR_MSIRDYF STM32_RCC_CIFR_MSIRDYF_MSK -#define STM32_RCC_CIFR_HSIRDYF_POS 3U -#define STM32_RCC_CIFR_HSIRDYF_MSK (0x1UL << STM32_RCC_CIFR_HSIRDYF_POS) -#define STM32_RCC_CIFR_HSIRDYF STM32_RCC_CIFR_HSIRDYF_MSK -#define STM32_RCC_CIFR_HSERDYF_POS 4U -#define STM32_RCC_CIFR_HSERDYF_MSK (0x1UL << STM32_RCC_CIFR_HSERDYF_POS) -#define STM32_RCC_CIFR_HSERDYF STM32_RCC_CIFR_HSERDYF_MSK -#define STM32_RCC_CIFR_PLLRDYF_POS 5U -#define STM32_RCC_CIFR_PLLRDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLRDYF_POS) -#define STM32_RCC_CIFR_PLLRDYF STM32_RCC_CIFR_PLLRDYF_MSK -#define STM32_RCC_CIFR_PLLSAI1RDYF_POS 6U -#define STM32_RCC_CIFR_PLLSAI1RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI1RDYF_POS) -#define STM32_RCC_CIFR_PLLSAI1RDYF STM32_RCC_CIFR_PLLSAI1RDYF_MSK -#define STM32_RCC_CIFR_PLLSAI2RDYF_POS 7U -#define STM32_RCC_CIFR_PLLSAI2RDYF_MSK (0x1UL << STM32_RCC_CIFR_PLLSAI2RDYF_POS) -#define STM32_RCC_CIFR_PLLSAI2RDYF STM32_RCC_CIFR_PLLSAI2RDYF_MSK -#define STM32_RCC_CIFR_CSSF_POS 8U -#define STM32_RCC_CIFR_CSSF_MSK (0x1UL << STM32_RCC_CIFR_CSSF_POS) -#define STM32_RCC_CIFR_CSSF STM32_RCC_CIFR_CSSF_MSK -#define STM32_RCC_CIFR_HSI48RDYF_POS 10U -#define STM32_RCC_CIFR_HSI48RDYF_MSK (0x1UL << STM32_RCC_CIFR_HSI48RDYF_POS) -#define STM32_RCC_CIFR_HSI48RDYF STM32_RCC_CIFR_HSI48RDYF_MSK - -/************** BIT DEFINITION FOR STM32_RCC_CICR REGISTER ******************/ -#define STM32_RCC_CICR_LSIRDYC_POS 0U -#define STM32_RCC_CICR_LSIRDYC_MSK (0x1UL << STM32_RCC_CICR_LSIRDYC_POS) -#define STM32_RCC_CICR_LSIRDYC STM32_RCC_CICR_LSIRDYC_MSK -#define STM32_RCC_CICR_LSERDYC_POS 1U -#define STM32_RCC_CICR_LSERDYC_MSK (0x1UL << STM32_RCC_CICR_LSERDYC_POS) -#define STM32_RCC_CICR_LSERDYC STM32_RCC_CICR_LSERDYC_MSK -#define STM32_RCC_CICR_MSIRDYC_POS 2U -#define STM32_RCC_CICR_MSIRDYC_MSK (0x1UL << STM32_RCC_CICR_MSIRDYC_POS) -#define STM32_RCC_CICR_MSIRDYC STM32_RCC_CICR_MSIRDYC_MSK -#define STM32_RCC_CICR_HSIRDYC_POS 3U -#define STM32_RCC_CICR_HSIRDYC_MSK (0x1UL << STM32_RCC_CICR_HSIRDYC_POS) -#define STM32_RCC_CICR_HSIRDYC STM32_RCC_CICR_HSIRDYC_MSK -#define STM32_RCC_CICR_HSERDYC_POS 4U -#define STM32_RCC_CICR_HSERDYC_MSK (0x1UL << STM32_RCC_CICR_HSERDYC_POS) -#define STM32_RCC_CICR_HSERDYC STM32_RCC_CICR_HSERDYC_MSK -#define STM32_RCC_CICR_PLLRDYC_POS 5U -#define STM32_RCC_CICR_PLLRDYC_MSK (0x1UL << STM32_RCC_CICR_PLLRDYC_POS) -#define STM32_RCC_CICR_PLLRDYC STM32_RCC_CICR_PLLRDYC_MSK -#define STM32_RCC_CICR_PLLSAI1RDYC_POS 6U -#define STM32_RCC_CICR_PLLSAI1RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI1RDYC_POS) -#define STM32_RCC_CICR_PLLSAI1RDYC STM32_RCC_CICR_PLLSAI1RDYC_MSK -#define STM32_RCC_CICR_PLLSAI2RDYC_POS 7U -#define STM32_RCC_CICR_PLLSAI2RDYC_MSK (0x1UL << STM32_RCC_CICR_PLLSAI2RDYC_POS) -#define STM32_RCC_CICR_PLLSAI2RDYC STM32_RCC_CICR_PLLSAI2RDYC_MSK -#define STM32_RCC_CICR_CSSC_POS 8U -#define STM32_RCC_CICR_CSSC_MSK (0x1UL << STM32_RCC_CICR_CSSC_POS) -#define STM32_RCC_CICR_CSSC STM32_RCC_CICR_CSSC_MSK -#define STM32_RCC_CICR_HSI48RDYC_POS 10U -#define STM32_RCC_CICR_HSI48RDYC_MSK (0x1UL << STM32_RCC_CICR_HSI48RDYC_POS) -#define STM32_RCC_CICR_HSI48RDYC STM32_RCC_CICR_HSI48RDYC_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB1RSTR REGISTER **************/ -#define STM32_RCC_AHB1RSTR_DMA1RST_POS 0U -#define STM32_RCC_AHB1RSTR_DMA1RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA1RST_POS) -#define STM32_RCC_AHB1RSTR_DMA1RST STM32_RCC_AHB1RSTR_DMA1RST_MSK -#define STM32_RCC_AHB1RSTR_DMA2RST_POS 1U -#define STM32_RCC_AHB1RSTR_DMA2RST_MSK (0x1UL << STM32_RCC_AHB1RSTR_DMA2RST_POS) -#define STM32_RCC_AHB1RSTR_DMA2RST STM32_RCC_AHB1RSTR_DMA2RST_MSK -#define STM32_RCC_AHB1RSTR_DMAMUX1RST_POS 2U -#define STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK \ - (0x1UL << STM32_RCC_AHB1RSTR_DMAMUX1RST_POS) -#define STM32_RCC_AHB1RSTR_DMAMUX1RST STM32_RCC_AHB1RSTR_DMAMUX1RST_MSK -#define STM32_RCC_AHB1RSTR_FLASHRST_POS 8U -#define STM32_RCC_AHB1RSTR_FLASHRST_MSK \ - (0x1UL << STM32_RCC_AHB1RSTR_FLASHRST_POS) -#define STM32_RCC_AHB1RSTR_FLASHRST STM32_RCC_AHB1RSTR_FLASHRST_MSK -#define STM32_RCC_AHB1RSTR_CRCRST_POS 12U -#define STM32_RCC_AHB1RSTR_CRCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_CRCRST_POS) -#define STM32_RCC_AHB1RSTR_CRCRST STM32_RCC_AHB1RSTR_CRCRST_MSK -#define STM32_RCC_AHB1RSTR_TSCRST_POS 16U -#define STM32_RCC_AHB1RSTR_TSCRST_MSK (0x1UL << STM32_RCC_AHB1RSTR_TSCRST_POS) -#define STM32_RCC_AHB1RSTR_TSCRST STM32_RCC_AHB1RSTR_TSCRST_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB2RSTR REGISTER **************/ -#define STM32_RCC_AHB2RSTR_GPIOARST_POS 0U -#define STM32_RCC_AHB2RSTR_GPIOARST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOARST_POS) -#define STM32_RCC_AHB2RSTR_GPIOARST STM32_RCC_AHB2RSTR_GPIOARST_MSK -#define STM32_RCC_AHB2RSTR_GPIOBRST_POS 1U -#define STM32_RCC_AHB2RSTR_GPIOBRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOBRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOBRST STM32_RCC_AHB2RSTR_GPIOBRST_MSK -#define STM32_RCC_AHB2RSTR_GPIOCRST_POS 2U -#define STM32_RCC_AHB2RSTR_GPIOCRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOCRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOCRST STM32_RCC_AHB2RSTR_GPIOCRST_MSK -#define STM32_RCC_AHB2RSTR_GPIODRST_POS 3U -#define STM32_RCC_AHB2RSTR_GPIODRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIODRST_POS) -#define STM32_RCC_AHB2RSTR_GPIODRST STM32_RCC_AHB2RSTR_GPIODRST_MSK -#define STM32_RCC_AHB2RSTR_GPIOERST_POS 4U -#define STM32_RCC_AHB2RSTR_GPIOERST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOERST_POS) -#define STM32_RCC_AHB2RSTR_GPIOERST STM32_RCC_AHB2RSTR_GPIOERST_MSK -#define STM32_RCC_AHB2RSTR_GPIOFRST_POS 5U -#define STM32_RCC_AHB2RSTR_GPIOFRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOFRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOFRST STM32_RCC_AHB2RSTR_GPIOFRST_MSK -#define STM32_RCC_AHB2RSTR_GPIOGRST_POS 6U -#define STM32_RCC_AHB2RSTR_GPIOGRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOGRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOGRST STM32_RCC_AHB2RSTR_GPIOGRST_MSK -#define STM32_RCC_AHB2RSTR_GPIOHRST_POS 7U -#define STM32_RCC_AHB2RSTR_GPIOHRST_MSK \ - (0x1UL << STM32_RCC_AHB2RSTR_GPIOHRST_POS) -#define STM32_RCC_AHB2RSTR_GPIOHRST STM32_RCC_AHB2RSTR_GPIOHRST_MSK -#define STM32_RCC_AHB2RSTR_ADCRST_POS 13U -#define STM32_RCC_AHB2RSTR_ADCRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_ADCRST_POS) -#define STM32_RCC_AHB2RSTR_ADCRST STM32_RCC_AHB2RSTR_ADCRST_MSK -#define STM32_RCC_AHB2RSTR_AESRST_POS 16U -#define STM32_RCC_AHB2RSTR_AESRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_AESRST_POS) -#define STM32_RCC_AHB2RSTR_AESRST STM32_RCC_AHB2RSTR_AESRST_MSK -#define STM32_RCC_AHB2RSTR_HASHRST_POS 17U -#define STM32_RCC_AHB2RSTR_HASHRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_HASHRST_POS) -#define STM32_RCC_AHB2RSTR_HASHRST STM32_RCC_AHB2RSTR_HASHRST_MSK -#define STM32_RCC_AHB2RSTR_RNGRST_POS 18U -#define STM32_RCC_AHB2RSTR_RNGRST_MSK (0x1UL << STM32_RCC_AHB2RSTR_RNGRST_POS) -#define STM32_RCC_AHB2RSTR_RNGRST STM32_RCC_AHB2RSTR_RNGRST_MSK - -/************* BIT DEFINITION FOR STM32_RCC_AHB3RSTR REGISTER **************/ -#define STM32_RCC_AHB3RSTR_FMCRST_POS 0U -#define STM32_RCC_AHB3RSTR_FMCRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_FMCRST_POS) -#define STM32_RCC_AHB3RSTR_FMCRST STM32_RCC_AHB3RSTR_FMCRST_MSK -#define STM32_RCC_AHB3RSTR_QSPIRST_POS 8U -#define STM32_RCC_AHB3RSTR_QSPIRST_MSK (0x1UL << STM32_RCC_AHB3RSTR_QSPIRST_POS) -#define STM32_RCC_AHB3RSTR_QSPIRST STM32_RCC_AHB3RSTR_QSPIRST_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1RSTR1 REGISTER **************/ -#define STM32_RCC_APB1RSTR1_TIM2RST_POS 0U -#define STM32_RCC_APB1RSTR1_TIM2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM2RST_POS) -#define STM32_RCC_APB1RSTR1_TIM2RST STM32_RCC_APB1RSTR1_TIM2RST_MSK -#define STM32_RCC_APB1RSTR1_TIM3RST_POS 1U -#define STM32_RCC_APB1RSTR1_TIM3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM3RST_POS) -#define STM32_RCC_APB1RSTR1_TIM3RST STM32_RCC_APB1RSTR1_TIM3RST_MSK -#define STM32_RCC_APB1RSTR1_TIM4RST_POS 2U -#define STM32_RCC_APB1RSTR1_TIM4RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM4RST_POS) -#define STM32_RCC_APB1RSTR1_TIM4RST STM32_RCC_APB1RSTR1_TIM4RST_MSK -#define STM32_RCC_APB1RSTR1_TIM5RST_POS 3U -#define STM32_RCC_APB1RSTR1_TIM5RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM5RST_POS) -#define STM32_RCC_APB1RSTR1_TIM5RST STM32_RCC_APB1RSTR1_TIM5RST_MSK -#define STM32_RCC_APB1RSTR1_TIM6RST_POS 4U -#define STM32_RCC_APB1RSTR1_TIM6RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM6RST_POS) -#define STM32_RCC_APB1RSTR1_TIM6RST STM32_RCC_APB1RSTR1_TIM6RST_MSK -#define STM32_RCC_APB1RSTR1_TIM7RST_POS 5U -#define STM32_RCC_APB1RSTR1_TIM7RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_TIM7RST_POS) -#define STM32_RCC_APB1RSTR1_TIM7RST STM32_RCC_APB1RSTR1_TIM7RST_MSK -#define STM32_RCC_APB1RSTR1_SPI2RST_POS 14U -#define STM32_RCC_APB1RSTR1_SPI2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_SPI2RST_POS) -#define STM32_RCC_APB1RSTR1_SPI2RST STM32_RCC_APB1RSTR1_SPI2RST_MSK -#define STM32_RCC_APB1RSTR1_SPI3RST_POS 15U -#define STM32_RCC_APB1RSTR1_SPI3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_SPI3RST_POS) -#define STM32_RCC_APB1RSTR1_SPI3RST STM32_RCC_APB1RSTR1_SPI3RST_MSK -#define STM32_RCC_APB1RSTR1_USART2RST_POS 17U -#define STM32_RCC_APB1RSTR1_USART2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USART2RST_POS) -#define STM32_RCC_APB1RSTR1_USART2RST STM32_RCC_APB1RSTR1_USART2RST_MSK -#define STM32_RCC_APB1RSTR1_USART3RST_POS 18U -#define STM32_RCC_APB1RSTR1_USART3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USART3RST_POS) -#define STM32_RCC_APB1RSTR1_USART3RST STM32_RCC_APB1RSTR1_USART3RST_MSK -#define STM32_RCC_APB1RSTR1_USART4RST_POS 19U -#define STM32_RCC_APB1RSTR1_USART4RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USART4RST_POS) -#define STM32_RCC_APB1RSTR1_USART4RST STM32_RCC_APB1RSTR1_USART4RST_MSK -#define STM32_RCC_APB1RSTR1_USART5RST_POS 20U -#define STM32_RCC_APB1RSTR1_USART5RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_USART5RST_POS) -#define STM32_RCC_APB1RSTR1_USART5RST STM32_RCC_APB1RSTR1_USART5RST_MSK -#define STM32_RCC_APB1RSTR1_I2C1RST_POS 21U -#define STM32_RCC_APB1RSTR1_I2C1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_I2C1RST_POS) -#define STM32_RCC_APB1RSTR1_I2C1RST STM32_RCC_APB1RSTR1_I2C1RST_MSK -#define STM32_RCC_APB1RSTR1_I2C2RST_POS 22U -#define STM32_RCC_APB1RSTR1_I2C2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_I2C2RST_POS) -#define STM32_RCC_APB1RSTR1_I2C2RST STM32_RCC_APB1RSTR1_I2C2RST_MSK -#define STM32_RCC_APB1RSTR1_I2C3RST_POS 23U -#define STM32_RCC_APB1RSTR1_I2C3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_I2C3RST_POS) -#define STM32_RCC_APB1RSTR1_I2C3RST STM32_RCC_APB1RSTR1_I2C3RST_MSK -#define STM32_RCC_APB1RSTR1_CRSRST_POS 24U -#define STM32_RCC_APB1RSTR1_CRSRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_CRSRST_POS) -#define STM32_RCC_APB1RSTR1_CRSRST STM32_RCC_APB1RSTR1_CRSRST_MSK -#define STM32_RCC_APB1RSTR1_PWRRST_POS 28U -#define STM32_RCC_APB1RSTR1_PWRRST_MSK (0x1UL << STM32_RCC_APB1RSTR1_PWRRST_POS) -#define STM32_RCC_APB1RSTR1_PWRRST STM32_RCC_APB1RSTR1_PWRRST_MSK -#define STM32_RCC_APB1RSTR1_DAC1RST_POS 29U -#define STM32_RCC_APB1RSTR1_DAC1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_DAC1RST_POS) -#define STM32_RCC_APB1RSTR1_DAC1RST STM32_RCC_APB1RSTR1_DAC1RST_MSK -#define STM32_RCC_APB1RSTR1_OPAMPRST_POS 30U -#define STM32_RCC_APB1RSTR1_OPAMPRST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_OPAMPRST_POS) -#define STM32_RCC_APB1RSTR1_OPAMPRST STM32_RCC_APB1RSTR1_OPAMPRST_MSK -#define STM32_RCC_APB1RSTR1_LPTIM1RST_POS 31U -#define STM32_RCC_APB1RSTR1_LPTIM1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR1_LPTIM1RST_POS) -#define STM32_RCC_APB1RSTR1_LPTIM1RST STM32_RCC_APB1RSTR1_LPTIM1RST_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER **************/ -#define STM32_RCC_APB1RSTR2_LPUART1RST_POS 0U -#define STM32_RCC_APB1RSTR2_LPUART1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_LPUART1RST_POS) -#define STM32_RCC_APB1RSTR2_LPUART1RST STM32_RCC_APB1RSTR2_LPUART1RST_MSK -#define STM32_RCC_APB1RSTR2_I2C4RST_POS 1U -#define STM32_RCC_APB1RSTR2_I2C4RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_I2C4RST_POS) -#define STM32_RCC_APB1RSTR2_I2C4RST STM32_RCC_APB1RSTR2_I2C4RST_MSK -#define STM32_RCC_APB1RSTR2_LPTIM2RST_POS 5U -#define STM32_RCC_APB1RSTR2_LPTIM2RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_LPTIM2RST_POS) -#define STM32_RCC_APB1RSTR2_LPTIM2RST STM32_RCC_APB1RSTR2_LPTIM2RST_MSK -#define STM32_RCC_APB1RSTR2_LPTIM3RST_POS 6U -#define STM32_RCC_APB1RSTR2_LPTIM3RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_LPTIM3RST_POS) -#define STM32_RCC_APB1RSTR2_LPTIM3RST STM32_RCC_APB1RSTR2_LPTIM3RST_MSK -#define STM32_RCC_APB1RSTR2_FDCAN1RST_POS 9U -#define STM32_RCC_APB1RSTR2_FDCAN1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_FDCAN1RST_POS) -#define STM32_RCC_APB1RSTR2_FDCAN1RST STM32_RCC_APB1RSTR2_FDCAN1RST_MSK -#define STM32_RCC_APB1RSTR2_USBFSRST_POS 21U -#define STM32_RCC_APB1RSTR2_USBFSRST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_USBFSRST_POS) -#define STM32_RCC_APB1RSTR2_USBFSRST STM32_RCC_APB1RSTR2_USBFSRST_MSK -#define STM32_RCC_APB1RSTR2_UCPD1RST_POS 23U -#define STM32_RCC_APB1RSTR2_UCPD1RST_MSK \ - (0x1UL << STM32_RCC_APB1RSTR2_UCPD1RST_POS) -#define STM32_RCC_APB1RSTR2_UCPD1RST STM32_RCC_APB1RSTR2_UCPD1RST_MSK - -/************** BIT DEFINITION FOR STM32_RCC_APB2RSTR REGISTER **************/ -#define STM32_RCC_APB2RSTR_SYSCFGRST_POS 0U -#define STM32_RCC_APB2RSTR_SYSCFGRST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_SYSCFGRST_POS) -#define STM32_RCC_APB2RSTR_SYSCFGRST STM32_RCC_APB2RSTR_SYSCFGRST_MSK -#define STM32_RCC_APB2RSTR_TIM1RST_POS 11U -#define STM32_RCC_APB2RSTR_TIM1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM1RST_POS) -#define STM32_RCC_APB2RSTR_TIM1RST STM32_RCC_APB2RSTR_TIM1RST_MSK -#define STM32_RCC_APB2RSTR_SPI1RST_POS 12U -#define STM32_RCC_APB2RSTR_SPI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SPI1RST_POS) -#define STM32_RCC_APB2RSTR_SPI1RST STM32_RCC_APB2RSTR_SPI1RST_MSK -#define STM32_RCC_APB2RSTR_TIM8RST_POS 13U -#define STM32_RCC_APB2RSTR_TIM8RST_MSK (0x1UL << STM32_RCC_APB2RSTR_TIM8RST_POS) -#define STM32_RCC_APB2RSTR_TIM8RST STM32_RCC_APB2RSTR_TIM8RST_MSK -#define STM32_RCC_APB2RSTR_USART1RST_POS 14U -#define STM32_RCC_APB2RSTR_USART1RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_USART1RST_POS) -#define STM32_RCC_APB2RSTR_USART1RST STM32_RCC_APB2RSTR_USART1RST_MSK -#define STM32_RCC_APB2RSTR_TIM15RST_POS 16U -#define STM32_RCC_APB2RSTR_TIM15RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_TIM15RST_POS) -#define STM32_RCC_APB2RSTR_TIM15RST STM32_RCC_APB2RSTR_TIM15RST_MSK -#define STM32_RCC_APB2RSTR_TIM16RST_POS 17U -#define STM32_RCC_APB2RSTR_TIM16RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_TIM16RST_POS) -#define STM32_RCC_APB2RSTR_TIM16RST STM32_RCC_APB2RSTR_TIM16RST_MSK -#define STM32_RCC_APB2RSTR_TIM17RST_POS 18U -#define STM32_RCC_APB2RSTR_TIM17RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_TIM17RST_POS) -#define STM32_RCC_APB2RSTR_TIM17RST STM32_RCC_APB2RSTR_TIM17RST_MSK -#define STM32_RCC_APB2RSTR_SAI1RST_POS 21U -#define STM32_RCC_APB2RSTR_SAI1RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI1RST_POS) -#define STM32_RCC_APB2RSTR_SAI1RST STM32_RCC_APB2RSTR_SAI1RST_MSK -#define STM32_RCC_APB2RSTR_SAI2RST_POS 22U -#define STM32_RCC_APB2RSTR_SAI2RST_MSK (0x1UL << STM32_RCC_APB2RSTR_SAI2RST_POS) -#define STM32_RCC_APB2RSTR_SAI2RST STM32_RCC_APB2RSTR_SAI2RST_MSK -#define STM32_RCC_APB2RSTR_DFSDM1RST_POS 24U -#define STM32_RCC_APB2RSTR_DFSDM1RST_MSK \ - (0x1UL << STM32_RCC_APB2RSTR_DFSDM1RST_POS) -#define STM32_RCC_APB2RSTR_DFSDM1RST STM32_RCC_APB2RSTR_DFSDM1RST_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB1ENR REGISTER ***************/ -#define STM32_RCC_AHB1ENR_DMA1EN_POS 0U -#define STM32_RCC_AHB1ENR_DMA1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA1EN_POS) -#define STM32_RCC_AHB1ENR_DMA1EN STM32_RCC_AHB1ENR_DMA1EN_MSK -#define STM32_RCC_AHB1ENR_DMA2EN_POS 1U -#define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS) -#define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK -#define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U -#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS) -#define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK -#define STM32_RCC_AHB1ENR_FLASHEN_POS 8U -#define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS) -#define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK -#define STM32_RCC_AHB1ENR_CRCEN_POS 12U -#define STM32_RCC_AHB1ENR_CRCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_CRCEN_POS) -#define STM32_RCC_AHB1ENR_CRCEN STM32_RCC_AHB1ENR_CRCEN_MSK -#define STM32_RCC_AHB1ENR_TSCEN_POS 16U -#define STM32_RCC_AHB1ENR_TSCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_TSCEN_POS) -#define STM32_RCC_AHB1ENR_TSCEN STM32_RCC_AHB1ENR_TSCEN_MSK -#define STM32_RCC_AHB1ENR_GTZCEN_POS 22U -#define STM32_RCC_AHB1ENR_GTZCEN_MSK (0x1UL << STM32_RCC_AHB1ENR_GTZCEN_POS) -#define STM32_RCC_AHB1ENR_GTZCEN STM32_RCC_AHB1ENR_GTZCEN_MSK - -/*************** BIT DEFINITION FOR STM32_RCC_AHB2ENR REGISTER *********/ -#define STM32_RCC_AHB2ENR_GPIOAEN_POS 0U -#define STM32_RCC_AHB2ENR_GPIOAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOAEN_POS) -#define STM32_RCC_AHB2ENR_GPIOAEN STM32_RCC_AHB2ENR_GPIOAEN_MSK -#define STM32_RCC_AHB2ENR_GPIOBEN_POS 1U -#define STM32_RCC_AHB2ENR_GPIOBEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOBEN_POS) -#define STM32_RCC_AHB2ENR_GPIOBEN STM32_RCC_AHB2ENR_GPIOBEN_MSK -#define STM32_RCC_AHB2ENR_GPIOCEN_POS 2U -#define STM32_RCC_AHB2ENR_GPIOCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOCEN_POS) -#define STM32_RCC_AHB2ENR_GPIOCEN STM32_RCC_AHB2ENR_GPIOCEN_MSK -#define STM32_RCC_AHB2ENR_GPIODEN_POS 3U -#define STM32_RCC_AHB2ENR_GPIODEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIODEN_POS) -#define STM32_RCC_AHB2ENR_GPIODEN STM32_RCC_AHB2ENR_GPIODEN_MSK -#define STM32_RCC_AHB2ENR_GPIOEEN_POS 4U -#define STM32_RCC_AHB2ENR_GPIOEEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOEEN_POS) -#define STM32_RCC_AHB2ENR_GPIOEEN STM32_RCC_AHB2ENR_GPIOEEN_MSK -#define STM32_RCC_AHB2ENR_GPIOFEN_POS 5U -#define STM32_RCC_AHB2ENR_GPIOFEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOFEN_POS) -#define STM32_RCC_AHB2ENR_GPIOFEN STM32_RCC_AHB2ENR_GPIOFEN_MSK -#define STM32_RCC_AHB2ENR_GPIOGEN_POS 6U -#define STM32_RCC_AHB2ENR_GPIOGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOGEN_POS) -#define STM32_RCC_AHB2ENR_GPIOGEN STM32_RCC_AHB2ENR_GPIOGEN_MSK -#define STM32_RCC_AHB2ENR_GPIOHEN_POS 7U -#define STM32_RCC_AHB2ENR_GPIOHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_GPIOHEN_POS) -#define STM32_RCC_AHB2ENR_GPIOHEN STM32_RCC_AHB2ENR_GPIOHEN_MSK -#define STM32_RCC_AHB2ENR_ADCEN_POS 13U -#define STM32_RCC_AHB2ENR_ADCEN_MSK (0x1UL << STM32_RCC_AHB2ENR_ADCEN_POS) -#define STM32_RCC_AHB2ENR_ADCEN STM32_RCC_AHB2ENR_ADCEN_MSK -#define STM32_RCC_AHB2ENR_AESEN_POS 16U -#define STM32_RCC_AHB2ENR_AESEN_MSK (0x1UL << STM32_RCC_AHB2ENR_AESEN_POS) -#define STM32_RCC_AHB2ENR_AESEN STM32_RCC_AHB2ENR_AESEN_MSK -#define STM32_RCC_AHB2ENR_HASHEN_POS 17U -#define STM32_RCC_AHB2ENR_HASHEN_MSK (0x1UL << STM32_RCC_AHB2ENR_HASHEN_POS) -#define STM32_RCC_AHB2ENR_HASHEN STM32_RCC_AHB2ENR_HASHEN_MSK -#define STM32_RCC_AHB2ENR_RNGEN_POS 18U -#define STM32_RCC_AHB2ENR_RNGEN_MSK (0x1UL << STM32_RCC_AHB2ENR_RNGEN_POS) -#define STM32_RCC_AHB2ENR_RNGEN STM32_RCC_AHB2ENR_RNGEN_MSK -#define STM32_RCC_AHB2ENR_PKAEN_POS 19U -#define STM32_RCC_AHB2ENR_PKAEN_MSK (0x1UL << STM32_RCC_AHB2ENR_PKAEN_POS) -#define STM32_RCC_AHB2ENR_PKAEN STM32_RCC_AHB2ENR_PKAEN_MSK -#define STM32_RCC_AHB2ENR_OTFDEC1EN_POS 21U -#define STM32_RCC_AHB2ENR_OTFDEC1EN_MSK \ - (0x1UL << STM32_RCC_AHB2ENR_OTFDEC1EN_POS) -#define STM32_RCC_AHB2ENR_OTFDEC1EN STM32_RCC_AHB2ENR_OTFDEC1EN_MSK -#define STM32_RCC_AHB2ENR_SDMMC1EN_POS 22U -#define STM32_RCC_AHB2ENR_SDMMC1EN_MSK (0x1UL << STM32_RCC_AHB2ENR_SDMMC1EN_POS) -#define STM32_RCC_AHB2ENR_SDMMC1EN STM32_RCC_AHB2ENR_SDMMC1EN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB3ENR REGISTER ***************/ -#define STM32_RCC_AHB3ENR_FMCEN_POS 0U -#define STM32_RCC_AHB3ENR_FMCEN_MSK (0x1UL << STM32_RCC_AHB3ENR_FMCEN_POS) -#define STM32_RCC_AHB3ENR_FMCEN STM32_RCC_AHB3ENR_FMCEN_MSK -#define STM32_RCC_AHB3ENR_QSPIEN_POS 8U -#define STM32_RCC_AHB3ENR_QSPIEN_MSK (0x1UL << STM32_RCC_AHB3ENR_QSPIEN_POS) -#define STM32_RCC_AHB3ENR_QSPIEN STM32_RCC_AHB3ENR_QSPIEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_APB1ENR1 REGISTER **************/ -#define STM32_RCC_APB1ENR1_TIM2EN_POS 0U -#define STM32_RCC_APB1ENR1_TIM2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM2EN_POS) -#define STM32_RCC_APB1ENR1_TIM2EN STM32_RCC_APB1ENR1_TIM2EN_MSK -#define STM32_RCC_APB1ENR1_TIM3EN_POS 1U -#define STM32_RCC_APB1ENR1_TIM3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM3EN_POS) -#define STM32_RCC_APB1ENR1_TIM3EN STM32_RCC_APB1ENR1_TIM3EN_MSK -#define STM32_RCC_APB1ENR1_TIM4EN_POS 2U -#define STM32_RCC_APB1ENR1_TIM4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM4EN_POS) -#define STM32_RCC_APB1ENR1_TIM4EN STM32_RCC_APB1ENR1_TIM4EN_MSK -#define STM32_RCC_APB1ENR1_TIM5EN_POS 3U -#define STM32_RCC_APB1ENR1_TIM5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM5EN_POS) -#define STM32_RCC_APB1ENR1_TIM5EN STM32_RCC_APB1ENR1_TIM5EN_MSK -#define STM32_RCC_APB1ENR1_TIM6EN_POS 4U -#define STM32_RCC_APB1ENR1_TIM6EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM6EN_POS) -#define STM32_RCC_APB1ENR1_TIM6EN STM32_RCC_APB1ENR1_TIM6EN_MSK -#define STM32_RCC_APB1ENR1_TIM7EN_POS 5U -#define STM32_RCC_APB1ENR1_TIM7EN_MSK (0x1UL << STM32_RCC_APB1ENR1_TIM7EN_POS) -#define STM32_RCC_APB1ENR1_TIM7EN STM32_RCC_APB1ENR1_TIM7EN_MSK -#define STM32_RCC_APB1ENR1_RTCAPBEN_POS 10U -#define STM32_RCC_APB1ENR1_RTCAPBEN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_RTCAPBEN_POS) -#define STM32_RCC_APB1ENR1_RTCAPBEN STM32_RCC_APB1ENR1_RTCAPBEN_MSK -#define STM32_RCC_APB1ENR1_WWDGEN_POS 11U -#define STM32_RCC_APB1ENR1_WWDGEN_MSK (0x1UL << STM32_RCC_APB1ENR1_WWDGEN_POS) -#define STM32_RCC_APB1ENR1_WWDGEN STM32_RCC_APB1ENR1_WWDGEN_MSK -#define STM32_RCC_APB1ENR1_SPI2EN_POS 14U -#define STM32_RCC_APB1ENR1_SPI2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI2EN_POS) -#define STM32_RCC_APB1ENR1_SPI2EN STM32_RCC_APB1ENR1_SPI2EN_MSK -#define STM32_RCC_APB1ENR1_SPI3EN_POS 15U -#define STM32_RCC_APB1ENR1_SPI3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_SPI3EN_POS) -#define STM32_RCC_APB1ENR1_SPI3EN STM32_RCC_APB1ENR1_SPI3EN_MSK -#define STM32_RCC_APB1ENR1_USART2EN_POS 17U -#define STM32_RCC_APB1ENR1_USART2EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_USART2EN_POS) -#define STM32_RCC_APB1ENR1_USART2EN STM32_RCC_APB1ENR1_USART2EN_MSK -#define STM32_RCC_APB1ENR1_USART3EN_POS 18U -#define STM32_RCC_APB1ENR1_USART3EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS) -#define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK -#define STM32_RCC_APB1ENR1_UART4EN_POS 19U -#define STM32_RCC_APB1ENR1_UART4EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS) -#define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK -#define STM32_RCC_APB1ENR1_UART5EN_POS 20U -#define STM32_RCC_APB1ENR1_UART5EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS) -#define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK -#define STM32_RCC_APB1ENR1_I2C1EN_POS 21U -#define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS) -#define STM32_RCC_APB1ENR1_I2C1EN STM32_RCC_APB1ENR1_I2C1EN_MSK -#define STM32_RCC_APB1ENR1_I2C2EN_POS 22U -#define STM32_RCC_APB1ENR1_I2C2EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C2EN_POS) -#define STM32_RCC_APB1ENR1_I2C2EN STM32_RCC_APB1ENR1_I2C2EN_MSK -#define STM32_RCC_APB1ENR1_I2C3EN_POS 23U -#define STM32_RCC_APB1ENR1_I2C3EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C3EN_POS) -#define STM32_RCC_APB1ENR1_I2C3EN STM32_RCC_APB1ENR1_I2C3EN_MSK -#define STM32_RCC_APB1ENR1_CRSEN_POS 24U -#define STM32_RCC_APB1ENR1_CRSEN_MSK (0x1UL << STM32_RCC_APB1ENR1_CRSEN_POS) -#define STM32_RCC_APB1ENR1_CRSEN STM32_RCC_APB1ENR1_CRSEN_MSK -#define STM32_RCC_APB1ENR1_PWREN_POS 28U -#define STM32_RCC_APB1ENR1_PWREN_MSK (0x1UL << STM32_RCC_APB1ENR1_PWREN_POS) -#define STM32_RCC_APB1ENR1_PWREN STM32_RCC_APB1ENR1_PWREN_MSK -#define STM32_RCC_APB1ENR1_DAC1EN_POS 29U -#define STM32_RCC_APB1ENR1_DAC1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_DAC1EN_POS) -#define STM32_RCC_APB1ENR1_DAC1EN STM32_RCC_APB1ENR1_DAC1EN_MSK -#define STM32_RCC_APB1ENR1_OPAMPEN_POS 30U -#define STM32_RCC_APB1ENR1_OPAMPEN_MSK (0x1UL << STM32_RCC_APB1ENR1_OPAMPEN_POS) -#define STM32_RCC_APB1ENR1_OPAMPEN STM32_RCC_APB1ENR1_OPAMPEN_MSK -#define STM32_RCC_APB1ENR1_LPTIM1EN_POS 31U -#define STM32_RCC_APB1ENR1_LPTIM1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_LPTIM1EN_POS) -#define STM32_RCC_APB1ENR1_LPTIM1EN STM32_RCC_APB1ENR1_LPTIM1EN_MSK - -/************ BIT DEFINITION FOR STM32_RCC_APB1RSTR2 REGISTER **************/ -#define STM32_RCC_APB1ENR2_LPUART1EN_POS 0U -#define STM32_RCC_APB1ENR2_LPUART1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS) -#define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK -#define STM32_RCC_APB1ENR2_I2C4EN_POS 1U -#define STM32_RCC_APB1ENR2_I2C4EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS) -#define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK -#define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U -#define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_LPTIM2EN_POS) -#define STM32_RCC_APB1ENR2_LPTIM2EN STM32_RCC_APB1ENR2_LPTIM2EN_MSK -#define STM32_RCC_APB1ENR2_LPTIM3EN_POS 6U -#define STM32_RCC_APB1ENR2_LPTIM3EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_LPTIM3EN_POS) -#define STM32_RCC_APB1ENR2_LPTIM3EN STM32_RCC_APB1ENR2_LPTIM3EN_MSK -#define STM32_RCC_APB1ENR2_FDCAN1EN_POS 9U -#define STM32_RCC_APB1ENR2_FDCAN1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS) -#define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK -#define STM32_RCC_APB1ENR2_USBFSEN_POS 21U -#define STM32_RCC_APB1ENR2_USBFSEN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS) -#define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK -#define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U -#define STM32_RCC_APB1ENR2_UCPD1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS) -#define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER ***************/ -#define STM32_RCC_APB2ENR_SYSCFGEN_POS 0U -#define STM32_RCC_APB2ENR_SYSCFGEN_MSK (0x1UL << STM32_RCC_APB2ENR_SYSCFGEN_POS) -#define STM32_RCC_APB2ENR_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN_MSK -#define STM32_RCC_APB2ENR_TIM1EN_POS 11U -#define STM32_RCC_APB2ENR_TIM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM1EN_POS) -#define STM32_RCC_APB2ENR_TIM1EN STM32_RCC_APB2ENR_TIM1EN_MSK -#define STM32_RCC_APB2ENR_SPI1EN_POS 12U -#define STM32_RCC_APB2ENR_SPI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SPI1EN_POS) -#define STM32_RCC_APB2ENR_SPI1EN STM32_RCC_APB2ENR_SPI1EN_MSK -#define STM32_RCC_APB2ENR_TIM8EN_POS 13U -#define STM32_RCC_APB2ENR_TIM8EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM8EN_POS) -#define STM32_RCC_APB2ENR_TIM8EN STM32_RCC_APB2ENR_TIM8EN_MSK -#define STM32_RCC_APB2ENR_USART1EN_POS 14U -#define STM32_RCC_APB2ENR_USART1EN_MSK (0x1UL << STM32_RCC_APB2ENR_USART1EN_POS) -#define STM32_RCC_APB2ENR_USART1EN STM32_RCC_APB2ENR_USART1EN_MSK -#define STM32_RCC_APB2ENR_TIM15EN_POS 16U -#define STM32_RCC_APB2ENR_TIM15EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM15EN_POS) -#define STM32_RCC_APB2ENR_TIM15EN STM32_RCC_APB2ENR_TIM15EN_MSK -#define STM32_RCC_APB2ENR_TIM16EN_POS 17U -#define STM32_RCC_APB2ENR_TIM16EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM16EN_POS) -#define STM32_RCC_APB2ENR_TIM16EN STM32_RCC_APB2ENR_TIM16EN_MSK -#define STM32_RCC_APB2ENR_TIM17EN_POS 18U -#define STM32_RCC_APB2ENR_TIM17EN_MSK (0x1UL << STM32_RCC_APB2ENR_TIM17EN_POS) -#define STM32_RCC_APB2ENR_TIM17EN STM32_RCC_APB2ENR_TIM17EN_MSK -#define STM32_RCC_APB2ENR_SAI1EN_POS 21U -#define STM32_RCC_APB2ENR_SAI1EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI1EN_POS) -#define STM32_RCC_APB2ENR_SAI1EN STM32_RCC_APB2ENR_SAI1EN_MSK -#define STM32_RCC_APB2ENR_SAI2EN_POS 22U -#define STM32_RCC_APB2ENR_SAI2EN_MSK (0x1UL << STM32_RCC_APB2ENR_SAI2EN_POS) -#define STM32_RCC_APB2ENR_SAI2EN STM32_RCC_APB2ENR_SAI2EN_MSK -#define STM32_RCC_APB2ENR_DFSDM1EN_POS 24U -#define STM32_RCC_APB2ENR_DFSDM1EN_MSK (0x1UL << STM32_RCC_APB2ENR_DFSDM1EN_POS) -#define STM32_RCC_APB2ENR_DFSDM1EN STM32_RCC_APB2ENR_DFSDM1EN_MSK - -/************ BIT DEFINITION FOR STM32_RCC_AHB1SMENR REGISTER ***************/ -#define STM32_RCC_AHB1SMENR_DMA1SMEN_POS 0U -#define STM32_RCC_AHB1SMENR_DMA1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_DMA1SMEN_POS) -#define STM32_RCC_AHB1SMENR_DMA1SMEN STM32_RCC_AHB1SMENR_DMA1SMEN_MSK -#define STM32_RCC_AHB1SMENR_DMA2SMEN_POS 1U -#define STM32_RCC_AHB1SMENR_DMA2SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_DMA2SMEN_POS) -#define STM32_RCC_AHB1SMENR_DMA2SMEN STM32_RCC_AHB1SMENR_DMA2SMEN_MSK -#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS 2U -#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_DMAMUX1SMEN_POS) -#define STM32_RCC_AHB1SMENR_DMAMUX1SMEN STM32_RCC_AHB1SMENR_DMAMUX1SMEN_MSK -#define STM32_RCC_AHB1SMENR_FLASHSMEN_POS 8U -#define STM32_RCC_AHB1SMENR_FLASHSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_FLASHSMEN_POS) -#define STM32_RCC_AHB1SMENR_FLASHSMEN STM32_RCC_AHB1SMENR_FLASHSMEN_MSK -#define STM32_RCC_AHB1SMENR_SRAM1SMEN_POS 9U -#define STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_SRAM1SMEN_POS) -#define STM32_RCC_AHB1SMENR_SRAM1SMEN STM32_RCC_AHB1SMENR_SRAM1SMEN_MSK -#define STM32_RCC_AHB1SMENR_CRCSMEN_POS 12U -#define STM32_RCC_AHB1SMENR_CRCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_CRCSMEN_POS) -#define STM32_RCC_AHB1SMENR_CRCSMEN STM32_RCC_AHB1SMENR_CRCSMEN_MSK -#define STM32_RCC_AHB1SMENR_TSCSMEN_POS 16U -#define STM32_RCC_AHB1SMENR_TSCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_TSCSMEN_POS) -#define STM32_RCC_AHB1SMENR_TSCSMEN STM32_RCC_AHB1SMENR_TSCSMEN_MSK -#define STM32_RCC_AHB1SMENR_GTZCSMEN_POS 22U -#define STM32_RCC_AHB1SMENR_GTZCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_GTZCSMEN_POS) -#define STM32_RCC_AHB1SMENR_GTZCSMEN STM32_RCC_AHB1SMENR_GTZCSMEN_MSK -#define STM32_RCC_AHB1SMENR_ICACHESMEN_POS 23U -#define STM32_RCC_AHB1SMENR_ICACHESMEN_MSK \ - (0x1UL << STM32_RCC_AHB1SMENR_ICACHESMEN_POS) -#define STM32_RCC_AHB1SMENR_ICACHESMEN STM32_RCC_AHB1SMENR_ICACHESMEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB2SMENR REGISTER *************/ -#define STM32_RCC_AHB2SMENR_GPIOASMEN_POS 0U -#define STM32_RCC_AHB2SMENR_GPIOASMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOASMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOASMEN STM32_RCC_AHB2SMENR_GPIOASMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOBSMEN_POS 1U -#define STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOBSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOBSMEN STM32_RCC_AHB2SMENR_GPIOBSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOCSMEN_POS 2U -#define STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOCSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOCSMEN STM32_RCC_AHB2SMENR_GPIOCSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIODSMEN_POS 3U -#define STM32_RCC_AHB2SMENR_GPIODSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIODSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIODSMEN STM32_RCC_AHB2SMENR_GPIODSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOESMEN_POS 4U -#define STM32_RCC_AHB2SMENR_GPIOESMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOESMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOESMEN STM32_RCC_AHB2SMENR_GPIOESMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOFSMEN_POS 5U -#define STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOFSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOFSMEN STM32_RCC_AHB2SMENR_GPIOFSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOGSMEN_POS 6U -#define STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOGSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOGSMEN STM32_RCC_AHB2SMENR_GPIOGSMEN_MSK -#define STM32_RCC_AHB2SMENR_GPIOHSMEN_POS 7U -#define STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_GPIOHSMEN_POS) -#define STM32_RCC_AHB2SMENR_GPIOHSMEN STM32_RCC_AHB2SMENR_GPIOHSMEN_MSK -#define STM32_RCC_AHB2SMENR_SRAM2SMEN_POS 9U -#define STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_SRAM2SMEN_POS) -#define STM32_RCC_AHB2SMENR_SRAM2SMEN STM32_RCC_AHB2SMENR_SRAM2SMEN_MSK -#define STM32_RCC_AHB2SMENR_ADCSMEN_POS 13U -#define STM32_RCC_AHB2SMENR_ADCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_ADCSMEN_POS) -#define STM32_RCC_AHB2SMENR_ADCSMEN STM32_RCC_AHB2SMENR_ADCSMEN_MSK -#define STM32_RCC_AHB2SMENR_AESSMEN_POS 16U -#define STM32_RCC_AHB2SMENR_AESSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_AESSMEN_POS) -#define STM32_RCC_AHB2SMENR_AESSMEN STM32_RCC_AHB2SMENR_AESSMEN_MSK -#define STM32_RCC_AHB2SMENR_HASHSMEN_POS 17U -#define STM32_RCC_AHB2SMENR_HASHSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_HASHSMEN_POS) -#define STM32_RCC_AHB2SMENR_HASHSMEN STM32_RCC_AHB2SMENR_HASHSMEN_MSK -#define STM32_RCC_AHB2SMENR_RNGSMEN_POS 18U -#define STM32_RCC_AHB2SMENR_RNGSMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_RNGSMEN_POS) -#define STM32_RCC_AHB2SMENR_RNGSMEN STM32_RCC_AHB2SMENR_RNGSMEN_MSK -#define STM32_RCC_AHB2SMENR_PKASMEN_POS 19U -#define STM32_RCC_AHB2SMENR_PKASMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_PKASMEN_POS) -#define STM32_RCC_AHB2SMENR_PKASMEN STM32_RCC_AHB2SMENR_PKASMEN_MSK -#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS 21U -#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_OTFDEC1SMEN_POS) -#define STM32_RCC_AHB2SMENR_OTFDEC1SMEN STM32_RCC_AHB2SMENR_OTFDEC1SMEN_MSK -#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS 22U -#define STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK \ - (0x1UL << STM32_RCC_AHB2SMENR_SDMMC1SMEN_POS) -#define STM32_RCC_AHB2SMENR_SDMMC1SMEN STM32_RCC_AHB2SMENR_SDMMC1SMEN_MSK - -/************** BIT DEFINITION FOR STM32_RCC_AHB3SMENR REGISTER *************/ -#define STM32_RCC_AHB3SMENR_FMCSMEN_POS 0U -#define STM32_RCC_AHB3SMENR_FMCSMEN_MSK \ - (0x1UL << STM32_RCC_AHB3SMENR_FMCSMEN_POS) -#define STM32_RCC_AHB3SMENR_FMCSMEN STM32_RCC_AHB3SMENR_FMCSMEN_MSK -#define STM32_RCC_AHB3SMENR_QSPISMEN_POS 8U -#define STM32_RCC_AHB3SMENR_QSPISMEN_MSK \ - (0x1UL << STM32_RCC_AHB3SMENR_QSPISMEN_POS) -#define STM32_RCC_AHB3SMENR_QSPISMEN STM32_RCC_AHB3SMENR_QSPISMEN_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1SMENR1 REGISTER *************/ -#define STM32_RCC_APB1SMENR1_TIM2SMEN_POS 0U -#define STM32_RCC_APB1SMENR1_TIM2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM2SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM2SMEN STM32_RCC_APB1SMENR1_TIM2SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM3SMEN_POS 1U -#define STM32_RCC_APB1SMENR1_TIM3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM3SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM3SMEN STM32_RCC_APB1SMENR1_TIM3SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM4SMEN_POS 2U -#define STM32_RCC_APB1SMENR1_TIM4SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM4SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM4SMEN STM32_RCC_APB1SMENR1_TIM4SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM5SMEN_POS 3U -#define STM32_RCC_APB1SMENR1_TIM5SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM5SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM5SMEN STM32_RCC_APB1SMENR1_TIM5SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM6SMEN_POS 4U -#define STM32_RCC_APB1SMENR1_TIM6SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM6SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM6SMEN STM32_RCC_APB1SMENR1_TIM6SMEN_MSK -#define STM32_RCC_APB1SMENR1_TIM7SMEN_POS 5U -#define STM32_RCC_APB1SMENR1_TIM7SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_TIM7SMEN_POS) -#define STM32_RCC_APB1SMENR1_TIM7SMEN STM32_RCC_APB1SMENR1_TIM7SMEN_MSK -#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS 10U -#define STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_RTCAPBSMEN_POS) -#define STM32_RCC_APB1SMENR1_RTCAPBSMEN STM32_RCC_APB1SMENR1_RTCAPBSMEN_MSK -#define STM32_RCC_APB1SMENR1_WWDGSMEN_POS 11U -#define STM32_RCC_APB1SMENR1_WWDGSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_WWDGSMEN_POS) -#define STM32_RCC_APB1SMENR1_WWDGSMEN STM32_RCC_APB1SMENR1_WWDGSMEN_MSK -#define STM32_RCC_APB1SMENR1_SPI2SMEN_POS 14U -#define STM32_RCC_APB1SMENR1_SPI2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_SPI2SMEN_POS) -#define STM32_RCC_APB1SMENR1_SPI2SMEN STM32_RCC_APB1SMENR1_SPI2SMEN_MSK -#define STM32_RCC_APB1SMENR1_SPI3SMEN_POS 15U -#define STM32_RCC_APB1SMENR1_SPI3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_SPI3SMEN_POS) -#define STM32_RCC_APB1SMENR1_SPI3SMEN STM32_RCC_APB1SMENR1_SPI3SMEN_MSK -#define STM32_RCC_APB1SMENR1_USART2SMEN_POS 17U -#define STM32_RCC_APB1SMENR1_USART2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USART2SMEN_POS) -#define STM32_RCC_APB1SMENR1_USART2SMEN STM32_RCC_APB1SMENR1_USART2SMEN_MSK -#define STM32_RCC_APB1SMENR1_USART3SMEN_POS 18U -#define STM32_RCC_APB1SMENR1_USART3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USART3SMEN_POS) -#define STM32_RCC_APB1SMENR1_USART3SMEN STM32_RCC_APB1SMENR1_USART3SMEN_MSK -#define STM32_RCC_APB1SMENR1_USART4SMEN_POS 19U -#define STM32_RCC_APB1SMENR1_USART4SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USART4SMEN_POS) -#define STM32_RCC_APB1SMENR1_USART4SMEN STM32_RCC_APB1SMENR1_USART4SMEN_MSK -#define STM32_RCC_APB1SMENR1_USART5SMEN_POS 20U -#define STM32_RCC_APB1SMENR1_USART5SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_USART5SMEN_POS) -#define STM32_RCC_APB1SMENR1_USART5SMEN STM32_RCC_APB1SMENR1_USART5SMEN_MSK -#define STM32_RCC_APB1SMENR1_I2C1SMEN_POS 21U -#define STM32_RCC_APB1SMENR1_I2C1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_I2C1SMEN_POS) -#define STM32_RCC_APB1SMENR1_I2C1SMEN STM32_RCC_APB1SMENR1_I2C1SMEN_MSK -#define STM32_RCC_APB1SMENR1_I2C2SMEN_POS 22U -#define STM32_RCC_APB1SMENR1_I2C2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_I2C2SMEN_POS) -#define STM32_RCC_APB1SMENR1_I2C2SMEN STM32_RCC_APB1SMENR1_I2C2SMEN_MSK -#define STM32_RCC_APB1SMENR1_I2C3SMEN_POS 23U -#define STM32_RCC_APB1SMENR1_I2C3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_I2C3SMEN_POS) -#define STM32_RCC_APB1SMENR1_I2C3SMEN STM32_RCC_APB1SMENR1_I2C3SMEN_MSK -#define STM32_RCC_APB1SMENR1_CRSSMEN_POS 24U -#define STM32_RCC_APB1SMENR1_CRSSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_CRSSMEN_POS) -#define STM32_RCC_APB1SMENR1_CRSSMEN STM32_RCC_APB1SMENR1_CRSSMEN_MSK -#define STM32_RCC_APB1SMENR1_PWRSMEN_POS 28U -#define STM32_RCC_APB1SMENR1_PWRSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_PWRSMEN_POS) -#define STM32_RCC_APB1SMENR1_PWRSMEN STM32_RCC_APB1SMENR1_PWRSMEN_MSK -#define STM32_RCC_APB1SMENR1_DAC1SMEN_POS 29U -#define STM32_RCC_APB1SMENR1_DAC1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_DAC1SMEN_POS) -#define STM32_RCC_APB1SMENR1_DAC1SMEN STM32_RCC_APB1SMENR1_DAC1SMEN_MSK -#define STM32_RCC_APB1SMENR1_OPAMPSMEN_POS 30U -#define STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_OPAMPSMEN_POS) -#define STM32_RCC_APB1SMENR1_OPAMPSMEN STM32_RCC_APB1SMENR1_OPAMPSMEN_MSK -#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS 31U -#define STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR1_LPTIM1SMEN_POS) -#define STM32_RCC_APB1SMENR1_LPTIM1SMEN STM32_RCC_APB1SMENR1_LPTIM1SMEN_MSK - -/************* BIT DEFINITION FOR STM32_RCC_APB1SMENR2 REGISTER *************/ -#define STM32_RCC_APB1SMENR2_LPUART1SMEN_POS 0U -#define STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_LPUART1SMEN_POS) -#define STM32_RCC_APB1SMENR2_LPUART1SMEN STM32_RCC_APB1SMENR2_LPUART1SMEN_MSK -#define STM32_RCC_APB1SMENR2_I2C4SMEN_POS 1U -#define STM32_RCC_APB1SMENR2_I2C4SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_I2C4SMEN_POS) -#define STM32_RCC_APB1SMENR2_I2C4SMEN STM32_RCC_APB1SMENR2_I2C4SMEN_MSK -#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS 5U -#define STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_LPTIM2SMEN_POS) -#define STM32_RCC_APB1SMENR2_LPTIM2SMEN STM32_RCC_APB1SMENR2_LPTIM2SMEN_MSK -#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS 6U -#define STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_LPTIM3SMEN_POS) -#define STM32_RCC_APB1SMENR2_LPTIM3SMEN STM32_RCC_APB1SMENR2_LPTIM3SMEN_MSK -#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS 9U -#define STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_FDCAN1SMEN_POS) -#define STM32_RCC_APB1SMENR2_FDCAN1SMEN STM32_RCC_APB1SMENR2_FDCAN1SMEN_MSK -#define STM32_RCC_APB1SMENR2_USBFSSMEN_POS 21U -#define STM32_RCC_APB1SMENR2_USBFSSMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_USBFSSMEN_POS) -#define STM32_RCC_APB1SMENR2_USBFSSMEN STM32_RCC_APB1SMENR2_USBFSSMEN_MSK -#define STM32_RCC_APB1SMENR2_UCPD1SMEN_POS 23U -#define STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK \ - (0x1UL << STM32_RCC_APB1SMENR2_UCPD1SMEN_POS) -#define STM32_RCC_APB1SMENR2_UCPD1SMEN STM32_RCC_APB1SMENR2_UCPD1SMEN_MSK - -/************ BIT DEFINITION FOR STM32_RCC_APB2SMENR REGISTER *************/ -#define STM32_RCC_APB2SMENR_SYSCFGSMEN_POS 0U -#define STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SYSCFGSMEN_POS) -#define STM32_RCC_APB2SMENR_SYSCFGSMEN STM32_RCC_APB2SMENR_SYSCFGSMEN_MSK -#define STM32_RCC_APB2SMENR_TIM1SMEN_POS 11U -#define STM32_RCC_APB2SMENR_TIM1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM1SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM1SMEN STM32_RCC_APB2SMENR_TIM1SMEN_MSK -#define STM32_RCC_APB2SMENR_SPI1SMEN_POS 12U -#define STM32_RCC_APB2SMENR_SPI1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SPI1SMEN_POS) -#define STM32_RCC_APB2SMENR_SPI1SMEN STM32_RCC_APB2SMENR_SPI1SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM8SMEN_POS 13U -#define STM32_RCC_APB2SMENR_TIM8SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM8SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM8SMEN STM32_RCC_APB2SMENR_TIM8SMEN_MSK -#define STM32_RCC_APB2SMENR_USART1SMEN_POS 14U -#define STM32_RCC_APB2SMENR_USART1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_USART1SMEN_POS) -#define STM32_RCC_APB2SMENR_USART1SMEN STM32_RCC_APB2SMENR_USART1SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM15SMEN_POS 16U -#define STM32_RCC_APB2SMENR_TIM15SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM15SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM15SMEN STM32_RCC_APB2SMENR_TIM15SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM16SMEN_POS 17U -#define STM32_RCC_APB2SMENR_TIM16SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM16SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM16SMEN STM32_RCC_APB2SMENR_TIM16SMEN_MSK -#define STM32_RCC_APB2SMENR_TIM17SMEN_POS 18U -#define STM32_RCC_APB2SMENR_TIM17SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_TIM17SMEN_POS) -#define STM32_RCC_APB2SMENR_TIM17SMEN STM32_RCC_APB2SMENR_TIM17SMEN_MSK -#define STM32_RCC_APB2SMENR_SAI1SMEN_POS 21U -#define STM32_RCC_APB2SMENR_SAI1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SAI1SMEN_POS) -#define STM32_RCC_APB2SMENR_SAI1SMEN STM32_RCC_APB2SMENR_SAI1SMEN_MSK -#define STM32_RCC_APB2SMENR_SAI2SMEN_POS 22U -#define STM32_RCC_APB2SMENR_SAI2SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_SAI2SMEN_POS) -#define STM32_RCC_APB2SMENR_SAI2SMEN STM32_RCC_APB2SMENR_SAI2SMEN_MSK -#define STM32_RCC_APB2SMENR_DFSDM1SMEN_POS 24U -#define STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK \ - (0x1UL << STM32_RCC_APB2SMENR_DFSDM1SMEN_POS) -#define STM32_RCC_APB2SMENR_DFSDM1SMEN STM32_RCC_APB2SMENR_DFSDM1SMEN_MSK - -/************* BIT DEFINITION FOR STM32_RCC_CCIPR REGISTER ******************/ -#define STM32_RCC_CCIPR_USART1SEL_POS 0U -#define STM32_RCC_CCIPR_USART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART1SEL_POS) -#define STM32_RCC_CCIPR_USART1SEL STM32_RCC_CCIPR_USART1SEL_MSK -#define STM32_RCC_CCIPR_USART1SEL_0 (0x1UL << STM32_RCC_CCIPR_USART1SEL_POS) -#define STM32_RCC_CCIPR_USART1SEL_1 (0x2UL << STM32_RCC_CCIPR_USART1SEL_POS) - -#define STM32_RCC_CCIPR_USART2SEL_POS 2U -#define STM32_RCC_CCIPR_USART2SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART2SEL_POS) -#define STM32_RCC_CCIPR_USART2SEL STM32_RCC_CCIPR_USART2SEL_MSK -#define STM32_RCC_CCIPR_USART2SEL_0 (0x1UL << STM32_RCC_CCIPR_USART2SEL_POS) -#define STM32_RCC_CCIPR_USART2SEL_1 (0x2UL << STM32_RCC_CCIPR_USART2SEL_POS) - -#define STM32_RCC_CCIPR_USART3SEL_POS 4U -#define STM32_RCC_CCIPR_USART3SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART3SEL_POS) -#define STM32_RCC_CCIPR_USART3SEL STM32_RCC_CCIPR_USART3SEL_MSK -#define STM32_RCC_CCIPR_USART3SEL_0 (0x1UL << STM32_RCC_CCIPR_USART3SEL_POS) -#define STM32_RCC_CCIPR_USART3SEL_1 (0x2UL << STM32_RCC_CCIPR_USART3SEL_POS) - -#define STM32_RCC_CCIPR_USART4SEL_POS 6U -#define STM32_RCC_CCIPR_USART4SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART4SEL_POS) -#define STM32_RCC_CCIPR_USART4SEL STM32_RCC_CCIPR_USART4SEL_MSK -#define STM32_RCC_CCIPR_USART4SEL_0 (0x1UL << STM32_RCC_CCIPR_USART4SEL_POS) -#define STM32_RCC_CCIPR_USART4SEL_1 (0x2UL << STM32_RCC_CCIPR_USART4SEL_POS) - -#define STM32_RCC_CCIPR_USART5SEL_POS 8U -#define STM32_RCC_CCIPR_USART5SEL_MSK (0x3UL << STM32_RCC_CCIPR_USART5SEL_POS) -#define STM32_RCC_CCIPR_USART5SEL STM32_RCC_CCIPR_USART5SEL_MSK -#define STM32_RCC_CCIPR_USART5SEL_0 (0x1UL << STM32_RCC_CCIPR_USART5SEL_POS) -#define STM32_RCC_CCIPR_USART5SEL_1 (0x2UL << STM32_RCC_CCIPR_USART5SEL_POS) - -#define STM32_RCC_CCIPR_LPUART1SEL_POS 10U -#define STM32_RCC_CCIPR_LPUART1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPUART1SEL_POS) -#define STM32_RCC_CCIPR_LPUART1SEL STM32_RCC_CCIPR_LPUART1SEL_MSK -#define STM32_RCC_CCIPR_LPUART1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPUART1SEL_POS) -#define STM32_RCC_CCIPR_LPUART1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPUART1SEL_POS) - -#define STM32_RCC_CCIPR_I2C1SEL_POS 12U -#define STM32_RCC_CCIPR_I2C1SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C1SEL_POS) -#define STM32_RCC_CCIPR_I2C1SEL STM32_RCC_CCIPR_I2C1SEL_MSK -#define STM32_RCC_CCIPR_I2C1SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C1SEL_POS) -#define STM32_RCC_CCIPR_I2C1SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C1SEL_POS) - -#define STM32_RCC_CCIPR_I2C2SEL_POS 14U -#define STM32_RCC_CCIPR_I2C2SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C2SEL_POS) -#define STM32_RCC_CCIPR_I2C2SEL STM32_RCC_CCIPR_I2C2SEL_MSK -#define STM32_RCC_CCIPR_I2C2SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C2SEL_POS) -#define STM32_RCC_CCIPR_I2C2SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C2SEL_POS) - -#define STM32_RCC_CCIPR_I2C3SEL_POS 16U -#define STM32_RCC_CCIPR_I2C3SEL_MSK (0x3UL << STM32_RCC_CCIPR_I2C3SEL_POS) -#define STM32_RCC_CCIPR_I2C3SEL STM32_RCC_CCIPR_I2C3SEL_MSK -#define STM32_RCC_CCIPR_I2C3SEL_0 (0x1UL << STM32_RCC_CCIPR_I2C3SEL_POS) -#define STM32_RCC_CCIPR_I2C3SEL_1 (0x2UL << STM32_RCC_CCIPR_I2C3SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM1SEL_POS 18U -#define STM32_RCC_CCIPR_LPTIM1SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) -#define STM32_RCC_CCIPR_LPTIM1SEL STM32_RCC_CCIPR_LPTIM1SEL_MSK -#define STM32_RCC_CCIPR_LPTIM1SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) -#define STM32_RCC_CCIPR_LPTIM1SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM1SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM2SEL_POS 20U -#define STM32_RCC_CCIPR_LPTIM2SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) -#define STM32_RCC_CCIPR_LPTIM2SEL STM32_RCC_CCIPR_LPTIM2SEL_MSK -#define STM32_RCC_CCIPR_LPTIM2SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) -#define STM32_RCC_CCIPR_LPTIM2SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM2SEL_POS) - -#define STM32_RCC_CCIPR_LPTIM3SEL_POS 22U -#define STM32_RCC_CCIPR_LPTIM3SEL_MSK (0x3UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) -#define STM32_RCC_CCIPR_LPTIM3SEL STM32_RCC_CCIPR_LPTIM3SEL_MSK -#define STM32_RCC_CCIPR_LPTIM3SEL_0 (0x1UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) -#define STM32_RCC_CCIPR_LPTIM3SEL_1 (0x2UL << STM32_RCC_CCIPR_LPTIM3SEL_POS) - -#define STM32_RCC_CCIPR_FDCANSEL_POS 24U -#define STM32_RCC_CCIPR_FDCANSEL_MSK (0x3UL << STM32_RCC_CCIPR_FDCANSEL_POS) -#define STM32_RCC_CCIPR_FDCANSEL STM32_RCC_CCIPR_FDCANSEL_MSK -#define STM32_RCC_CCIPR_FDCANSEL_0 (0x1UL << STM32_RCC_CCIPR_FDCANSEL_POS) -#define STM32_RCC_CCIPR_FDCANSEL_1 (0x2UL << STM32_RCC_CCIPR_FDCANSEL_POS) - -#define STM32_RCC_CCIPR_CLK48SEL_POS 26U -#define STM32_RCC_CCIPR_CLK48SEL_MSK (0x3UL << STM32_RCC_CCIPR_CLK48SEL_POS) -#define STM32_RCC_CCIPR_CLK48SEL STM32_RCC_CCIPR_CLK48SEL_MSK -#define STM32_RCC_CCIPR_CLK48SEL_0 (0x1UL << STM32_RCC_CCIPR_CLK48SEL_POS) -#define STM32_RCC_CCIPR_CLK48SEL_1 (0x2UL << STM32_RCC_CCIPR_CLK48SEL_POS) - -#define STM32_RCC_CCIPR_ADCSEL_POS 28U -#define STM32_RCC_CCIPR_ADCSEL_MSK (0x3UL << STM32_RCC_CCIPR_ADCSEL_POS) -#define STM32_RCC_CCIPR_ADCSEL STM32_RCC_CCIPR_ADCSEL_MSK -#define STM32_RCC_CCIPR_ADCSEL_0 (0x1UL << STM32_RCC_CCIPR_ADCSEL_POS) -#define STM32_RCC_CCIPR_ADCSEL_1 (0x2UL << STM32_RCC_CCIPR_ADCSEL_POS) - -/************** BIT DEFINITION FOR STM32_RCC_BDCR REGISTER ******************/ -#define STM32_RCC_BDCR_LSEBYP_POS 2U -#define STM32_RCC_BDCR_LSEBYP_MSK (0x1UL << STM32_RCC_BDCR_LSEBYP_POS) -#define STM32_RCC_BDCR_LSEBYP STM32_RCC_BDCR_LSEBYP_MSK - -#define STM32_RCC_BDCR_LSEDRV_POS 3U -#define STM32_RCC_BDCR_LSEDRV_MSK (0x3UL << STM32_RCC_BDCR_LSEDRV_POS) -#define STM32_RCC_BDCR_LSEDRV STM32_RCC_BDCR_LSEDRV_MSK -#define STM32_RCC_BDCR_LSEDRV_0 (0x1UL << STM32_RCC_BDCR_LSEDRV_POS) -#define STM32_RCC_BDCR_LSEDRV_1 (0x2UL << STM32_RCC_BDCR_LSEDRV_POS) - -#define STM32_RCC_BDCR_LSECSSON_POS 5U -#define STM32_RCC_BDCR_LSECSSON_MSK (0x1UL << STM32_RCC_BDCR_LSECSSON_POS) -#define STM32_RCC_BDCR_LSECSSON STM32_RCC_BDCR_LSECSSON_MSK -#define STM32_RCC_BDCR_LSECSSD_POS 6U -#define STM32_RCC_BDCR_LSECSSD_MSK (0x1UL << STM32_RCC_BDCR_LSECSSD_POS) -#define STM32_RCC_BDCR_LSECSSD STM32_RCC_BDCR_LSECSSD_MSK -#define STM32_RCC_BDCR_LSESYSEN_POS 7U -#define STM32_RCC_BDCR_LSESYSEN_MSK (0x1UL << STM32_RCC_BDCR_LSESYSEN_POS) -#define STM32_RCC_BDCR_LSESYSEN STM32_RCC_BDCR_LSESYSEN_MSK - -#define STM32_RCC_BDCR_RTCSEL_POS 8U -#define STM32_RCC_BDCR_RTCSEL_MSK (0x3UL << STM32_RCC_BDCR_RTCSEL_POS) -#define STM32_RCC_BDCR_RTCSEL STM32_RCC_BDCR_RTCSEL_MSK -#define STM32_RCC_BDCR_RTCSEL_0 (0x1UL << STM32_RCC_BDCR_RTCSEL_POS) -#define STM32_RCC_BDCR_RTCSEL_1 (0x2UL << STM32_RCC_BDCR_RTCSEL_POS) - -#define STM32_RCC_BDCR_LSESYSRDY_POS 11U -#define STM32_RCC_BDCR_LSESYSRDY_MSK (0x1UL << STM32_RCC_BDCR_LSESYSRDY_POS) -#define STM32_RCC_BDCR_LSESYSRDY STM32_RCC_BDCR_LSESYSRDY_MSK -#define STM32_RCC_BDCR_LSCOEN_POS 24U -#define STM32_RCC_BDCR_LSCOEN_MSK (0x1UL << STM32_RCC_BDCR_LSCOEN_POS) -#define STM32_RCC_BDCR_LSCOEN STM32_RCC_BDCR_LSCOEN_MSK -#define STM32_RCC_BDCR_LSCOSEL_POS 25U -#define STM32_RCC_BDCR_LSCOSEL_MSK (0x1UL << STM32_RCC_BDCR_LSCOSEL_POS) -#define STM32_RCC_BDCR_LSCOSEL STM32_RCC_BDCR_LSCOSEL_MSK - -/************** BIT DEFINITION FOR STM32_RCC_CSR REGISTER *******************/ -#define STM32_RCC_CSR_LSION_POS 0U -#define STM32_RCC_CSR_LSION_MSK (0x1UL << STM32_RCC_CSR_LSION_POS) -#define STM32_RCC_CSR_LSION STM32_RCC_CSR_LSION_MSK -#define STM32_RCC_CSR_LSIRDY_POS 1U -#define STM32_RCC_CSR_LSIRDY_MSK (0x1UL << STM32_RCC_CSR_LSIRDY_POS) -#define STM32_RCC_CSR_LSIRDY STM32_RCC_CSR_LSIRDY_MSK -#define STM32_RCC_CSR_LSIPRE_POS 4U -#define STM32_RCC_CSR_LSIPRE_MSK (0x1UL << STM32_RCC_CSR_LSIPRE_POS) -#define STM32_RCC_CSR_LSIPRE STM32_RCC_CSR_LSIPRE_MSK - -#define STM32_RCC_CSR_MSISRANGE_POS 8U -#define STM32_RCC_CSR_MSISRANGE_MSK (0xFUL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE STM32_RCC_CSR_MSISRANGE_MSK -#define STM32_RCC_CSR_MSISRANGE_1 (0x4UL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE_2 (0x5UL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE_4 (0x6UL << STM32_RCC_CSR_MSISRANGE_POS) -#define STM32_RCC_CSR_MSISRANGE_8 (0x7UL << STM32_RCC_CSR_MSISRANGE_POS) - -#define STM32_RCC_CSR_RMVF_POS 23U -#define STM32_RCC_CSR_RMVF_MSK (0x1UL << STM32_RCC_CSR_RMVF_POS) -#define STM32_RCC_CSR_RMVF STM32_RCC_CSR_RMVF_MSK -#define STM32_RCC_CSR_OBLRSTF_POS 25U -#define STM32_RCC_CSR_OBLRSTF_MSK (0x1UL << STM32_RCC_CSR_OBLRSTF_POS) -#define STM32_RCC_CSR_OBLRSTF STM32_RCC_CSR_OBLRSTF_MSK -#define STM32_RCC_CSR_PINRSTF_POS 26U -#define STM32_RCC_CSR_PINRSTF_MSK (0x1UL << STM32_RCC_CSR_PINRSTF_POS) -#define STM32_RCC_CSR_PINRSTF STM32_RCC_CSR_PINRSTF_MSK -#define STM32_RCC_CSR_BORRSTF_POS 27U -#define STM32_RCC_CSR_BORRSTF_MSK (0x1UL << STM32_RCC_CSR_BORRSTF_POS) -#define STM32_RCC_CSR_BORRSTF STM32_RCC_CSR_BORRSTF_MSK -#define STM32_RCC_CSR_SFTRSTF_POS 28U -#define STM32_RCC_CSR_SFTRSTF_MSK (0x1UL << STM32_RCC_CSR_SFTRSTF_POS) -#define STM32_RCC_CSR_SFTRSTF STM32_RCC_CSR_SFTRSTF_MSK -#define STM32_RCC_CSR_IWDGRSTF_POS 29U -#define STM32_RCC_CSR_IWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_IWDGRSTF_POS) -#define STM32_RCC_CSR_IWDGRSTF STM32_RCC_CSR_IWDGRSTF_MSK -#define STM32_RCC_CSR_WWDGRSTF_POS 30U -#define STM32_RCC_CSR_WWDGRSTF_MSK (0x1UL << STM32_RCC_CSR_WWDGRSTF_POS) -#define STM32_RCC_CSR_WWDGRSTF STM32_RCC_CSR_WWDGRSTF_MSK -#define STM32_RCC_CSR_LPWRRSTF_POS 31U -#define STM32_RCC_CSR_LPWRRSTF_MSK (0x1UL << STM32_RCC_CSR_LPWRRSTF_POS) -#define STM32_RCC_CSR_LPWRRSTF STM32_RCC_CSR_LPWRRSTF_MSK - -/************** Bit definition for STM32_RCC_CRRCR register *****************/ -#define STM32_RCC_CRRCR_HSI48ON_POS 0U -#define STM32_RCC_CRRCR_HSI48ON_MSK (0x1UL << STM32_RCC_CRRCR_HSI48ON_POS) -#define STM32_RCC_CRRCR_HSI48ON STM32_RCC_CRRCR_HSI48ON_MSK -#define STM32_RCC_CRRCR_HSI48RDY_POS 1U -#define STM32_RCC_CRRCR_HSI48RDY_MSK (0x1UL << STM32_RCC_CRRCR_HSI48RDY_POS) -#define STM32_RCC_CRRCR_HSI48RDY STM32_RCC_CRRCR_HSI48RDY_MSK - -/************** Bit definition for STM32_RCC_CRRCR2 register ****************/ -/* TODO */ - -/************** Bit definition for STM32_RCC_DLYCFGR register ***************/ -/* TODO */ - -/************** Bit definition for STM32_RCC_CCIPR2 register ****************/ -/* TODO */ - - -/*!< HSI48CAL configuration */ -#define STM32_RCC_CRRCR_HSI48CAL_POS 7U -#define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL STM32_RCC_CRRCR_HSI48CAL_MSK -#define STM32_RCC_CRRCR_HSI48CAL_0 (0x001UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_1 (0x002UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_2 (0x004UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_3 (0x008UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_4 (0x010UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_5 (0x020UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_6 (0x040UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_7 (0x080UL << STM32_RCC_CRRCR_HSI48CAL_POS) -#define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) - -/* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_PWREN BIT(28) - -#define STM32_RCC_PB2_SYSCFGEN BIT(0) -#define STM32_RCC_PB2_USART1 BIT(14) - -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) - -#define STM32_RCC_HB2_GPIOA BIT(0) -#define STM32_RCC_HB2_GPIOB BIT(1) -#define STM32_RCC_HB2_GPIOC BIT(2) -#define STM32_RCC_HB2_GPIOD BIT(3) -#define STM32_RCC_HB2_GPIOE BIT(4) -#define STM32_RCC_HB2_GPIOH BIT(7) -#define STM32_RCC_HB2_ADC1 BIT(13) - -/* Reset causes definitions */ -/* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xff000000 -#define RESET_CAUSE_RMVF BIT(23) -/* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF BIT(8) -#define RESET_CAUSE_SBF_CLR BIT(8) - -/* --- Watchdogs --- */ - -/* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_WUTE BIT(10) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_CR_WUTIE BIT(14) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_WUTWF BIT(2) -#define STM32_RTC_ISR_INITS BIT(4) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_ISR_WUTF BIT(9) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_RTC_CLEAR_FLAG(x) \ - (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ - (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -#define RTC_TR_PM_POS 22U -#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) -#define RTC_TR_PM RTC_TR_PM_MSK -#define RTC_TR_HT_POS 20U -#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) -#define RTC_TR_HT RTC_TR_HT_MSK -#define RTC_TR_HU_POS 16U -#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) -#define RTC_TR_HU RTC_TR_HU_MSK -#define RTC_TR_MNT_POS 12U -#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) -#define RTC_TR_MNT RTC_TR_MNT_MSK -#define RTC_TR_MNU_POS 8U -#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) -#define RTC_TR_MNU RTC_TR_MNU_MSK -#define RTC_TR_ST_POS 4U -#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) -#define RTC_TR_ST RTC_TR_ST_MSK -#define RTC_TR_SU_POS 0U -#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) -#define RTC_TR_SU RTC_TR_SU_MSK - - - -/* --- SPI --- */ - -/* The SPI controller registers */ -struct stm32_spi_regs { - uint16_t cr1; - uint16_t _pad0; - uint16_t cr2; - uint16_t _pad1; - unsigned int sr; - uint8_t dr; - uint8_t _pad2; - uint16_t _pad3; - unsigned int crcpr; - unsigned int rxcrcr; - unsigned int txcrcr; - unsigned int i2scfgr; /* STM32L only */ - unsigned int i2spr; /* STM32L only */ -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct stm32_spi_regs stm32_spi_regs_t; - -#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE) -#define STM32_SPI2_REGS ((stm32_spi_regs_t *)STM32_SPI2_BASE) -#define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) -#define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) - -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) -/* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) - -/* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C) -/* Minimum number of bytes that can be written to flash */ -#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE - -#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR -#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR - -/* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - -#define EXTI_RTC_ALR_EVENT BIT(18) - -/* --- ADC --- */ -#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC1_ISR_ADRDY BIT(0) -#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC1_IER_AWDIE BIT(7) -#define STM32_ADC1_IER_OVRIE BIT(4) -#define STM32_ADC1_IER_EOSEQIE BIT(3) -#define STM32_ADC1_IER_EOCIE BIT(2) -#define STM32_ADC1_IER_EOSMPIE BIT(1) -#define STM32_ADC1_IER_ADRDYIE BIT(0) - -#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC1_CR_ADEN BIT(0) -#define STM32_ADC1_CR_ADDIS BIT(1) -#define STM32_ADC1_CR_ADSTP BIT(4) -#define STM32_ADC1_CR_ADVREGEN BIT(28) -#define STM32_ADC1_CR_DEEPPWD BIT(29) -#define STM32_ADC1_CR_ADCAL BIT(31) -#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) -/* Analog watchdog channel selection */ -#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) -#define STM32_ADC1_CFGR_AWDEN BIT(23) -#define STM32_ADC1_CFGR_AWDSGL BIT(22) -#define STM32_ADC1_CFGR_AUTDLY BIT(14) -/* Selects single vs continuous */ -#define STM32_ADC1_CFGR_CONT BIT(13) -/* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC1_CFGR_OVRMOD BIT(12) -/* External trigger polarity selection */ -#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) -#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) -#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) -#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) -#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) -#define STM32_ADC1_CFGR_ALIGN BIT(5) -/* External trigger selection */ -#define STM32_ADC1_CFGR_TRG0 (0 << 6) -#define STM32_ADC1_CFGR_TRG1 (1 << 6) -#define STM32_ADC1_CFGR_TRG2 (2 << 6) -#define STM32_ADC1_CFGR_TRG3 (3 << 6) -#define STM32_ADC1_CFGR_TRG4 (4 << 6) -#define STM32_ADC1_CFGR_TRG5 (5 << 6) -#define STM32_ADC1_CFGR_TRG6 (6 << 6) -#define STM32_ADC1_CFGR_TRG7 (7 << 6) -#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) -/* Selects circular vs one-shot */ -#define STM32_ADC1_CFGR_DMACFG BIT(1) -#define STM32_ADC1_CFGR_DMAEN BIT(0) -#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -/* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) -/* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) -#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) -#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) -#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) -#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) -#define STM32_USB_BCDR_DPPU BIT(15) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- DMA --- */ - -/* - * Available DMA channels, numbered from 0. - * - * Note: The STM datasheet tends to number things from 1. We should ask - * the European elevator engineers to talk to MCU engineer counterparts - * about this. This means that if the datasheet refers to channel n, - * you need to use STM32_DMAC_CHn (=n-1) in the code. - * - * Also note that channels are overloaded; obviously you can only use one - * function on each channel at a time. - */ -enum dma_channel { - /* Channel numbers */ - STM32_DMAC_CH1 = 0, - STM32_DMAC_CH2 = 1, - STM32_DMAC_CH3 = 2, - STM32_DMAC_CH4 = 3, - STM32_DMAC_CH5 = 4, - STM32_DMAC_CH6 = 5, - STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ - STM32_DMAC_CH9 = 8, - STM32_DMAC_CH10 = 9, - STM32_DMAC_CH11 = 10, - STM32_DMAC_CH12 = 11, - STM32_DMAC_CH13 = 12, - STM32_DMAC_CH14 = 13, - STM32_DMAC_CH15 = 14, - - /* Channel functions */ - STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, - STM32_DMAC_SPI1_TX = STM32_DMAC_CH3, - STM32_DMAC_USART1_TX = STM32_DMAC_CH14, - STM32_DMAC_USART1_RX = STM32_DMAC_CH15, - STM32_DMAC_SPI2_RX = STM32_DMAC_CH4, - STM32_DMAC_SPI2_TX = STM32_DMAC_CH5, - STM32_DMAC_SPI3_RX = STM32_DMAC_CH9, - STM32_DMAC_SPI3_TX = STM32_DMAC_CH10, - STM32_DMAC_COUNT = 15, -}; - -#define STM32_DMAC_PER_CTLR 8 - -/* Registers for a single channel of the DMA controller */ -struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; -}; - -/* Always use stm32_dma_chan_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_chan stm32_dma_chan_t; - -/* Common code and header file must use this */ -typedef stm32_dma_chan_t dma_chan_t; - -/* Registers for the DMA controller */ -struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; - stm32_dma_chan_t chan[STM32_DMAC_COUNT]; -}; - -/* Always use stm32_dma_regs_t so volatile keyword is included! */ -typedef volatile struct stm32_dma_regs stm32_dma_regs_t; - -#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - - -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) -#define STM32_DMA_REGS(channel) \ - ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) - -/* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) -#define STM32_DMA_ISR_MASK(channel, mask) \ - ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - - -/* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - -#endif /* !__ASSEMBLER__ */ - diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h deleted file mode 100644 index 74a195a54e..0000000000 --- a/chip/stm32/registers.h +++ /dev/null @@ -1,492 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * @file - * @brief Register map for the STM32 family of chips - * - * This header file should only contain register definitions and - * functionality that are common to all STM32 chips. - * Any chip/family specific macros must be placed in their family - * specific registers file, which is conditionally included at the - * end of this file. - * Include this file directly for all STM32 register definitions. - * - * ### History and Reasoning ### - * In a time before chip family register file separation, - * long long ago, there lived a single file called `registers.h`, - * which housed register definitions for all STM32 chip family and variants. - * This poor file was 3000 lines of register macros and C definitions, - * swiss-cheesed by nested preprocessor conditional logic. - * Adding a single new chip variant required splitting multiple, - * already nested, conditional sections throughout the file. - * Readability was on the difficult side and refactoring was dangerous. - * - * The number of STM32 variants had outgrown the single registers file model. - * The minor gains of sharing a set of registers between a subset of chip - * variants no longer outweighed the complexity of the following operations: - * - Adding a new chip variant or variant feature - * - Determining if a register was properly setup for a variant or if it - * was simply not unset - * - * To strike a balance between shared registers and chip specific registers, - * the registers.h file remains a place for common definitions, but family - * specific definitions were moved to their own files. - * These family specific files contain a much reduced level of preprocessor - * logic for variant specific registers. - * - * See https://crrev.com/c/1674679 to witness the separation steps. - */ - -#ifndef __CROS_EC_REGISTERS_H -#define __CROS_EC_REGISTERS_H - -#include "common.h" -#include "compile_time_macros.h" - - -#ifndef __ASSEMBLER__ - -/* Register definitions */ - -/* --- USART --- */ -#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) -#define STM32_USART_REG(base, offset) REG32((base) + (offset)) - -#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) - -/* --- TIMERS --- */ -#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) - -#define STM32_TIM_REG(n, offset) \ - REG16(STM32_TIM_BASE(n) + (offset)) -#define STM32_TIM_REG32(n, offset) \ - REG32(STM32_TIM_BASE(n) + (offset)) - -#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) -#define STM32_TIM_CR1_CEN BIT(0) -#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) -#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) -#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) -#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) -#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) -#define STM32_TIM_EGR_UG BIT(0) -#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) -#define STM32_TIM_CCMR1_OC1PE BIT(2) -/* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ -#define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) -#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) -#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) -#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) -#define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2) -#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) -#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) -#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) -#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) -#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) -#define STM32_TIM_CCER_CC1E BIT(0) -#define STM32_TIM_CCER_CC1P BIT(1) -#define STM32_TIM_CCER_CC1NE BIT(2) -#define STM32_TIM_CCER_CC1NP BIT(3) -#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) -#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) -#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) -#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30) -#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34) -#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38) -#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) -#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) -#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) -#define STM32_TIM_BDTR_MOE BIT(15) -#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) -#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) -#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) - -#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4) - -#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24) -#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C) -#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34) -#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38) -#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C) -#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40) -/* Timer registers as struct */ -struct timer_ctlr { - unsigned cr1; - unsigned cr2; - unsigned smcr; - unsigned dier; - - unsigned sr; - unsigned egr; - unsigned ccmr1; - unsigned ccmr2; - - unsigned ccer; - unsigned cnt; - unsigned psc; - unsigned arr; - - unsigned ccr[5]; /* ccr[0] = reserved30 */ - - unsigned bdtr; - unsigned dcr; - unsigned dmar; - - unsigned option_register; -}; -/* Must be volatile, or compiler optimizes out repeated accesses */ -typedef volatile struct timer_ctlr timer_ctlr_t; - -/* --- Low power timers --- */ -#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE) - -#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset)) - -#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) -#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) -#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) -#define STM32_LPTIM_INT_DOWN BIT(6) -#define STM32_LPTIM_INT_UP BIT(5) -#define STM32_LPTIM_INT_ARROK BIT(4) -#define STM32_LPTIM_INT_CMPOK BIT(3) -#define STM32_LPTIM_INT_EXTTRIG BIT(2) -#define STM32_LPTIM_INT_ARRM BIT(1) -#define STM32_LPTIM_INT_CMPM BIT(0) -#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) -#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) -#define STM32_LPTIM_CR_RSTARE BIT(4) -#define STM32_LPTIM_CR_COUNTRST BIT(3) -#define STM32_LPTIM_CR_CNTSTRT BIT(2) -#define STM32_LPTIM_CR_SNGSTRT BIT(1) -#define STM32_LPTIM_CR_ENABLE BIT(0) -#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) -#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) -#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) -#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24) - -/* --- GPIO --- */ - -#define GPIO_A STM32_GPIOA_BASE -#define GPIO_B STM32_GPIOB_BASE -#define GPIO_C STM32_GPIOC_BASE -#define GPIO_D STM32_GPIOD_BASE -#define GPIO_E STM32_GPIOE_BASE -#define GPIO_F STM32_GPIOF_BASE -#define GPIO_G STM32_GPIOG_BASE -#define GPIO_H STM32_GPIOH_BASE -#define GPIO_I STM32_GPIOI_BASE -#define GPIO_J STM32_GPIOJ_BASE -#define GPIO_K STM32_GPIOK_BASE - -#define UNIMPLEMENTED_GPIO_BANK GPIO_A - - -/* --- I2C --- */ -#define STM32_I2C1_PORT 0 -#define STM32_I2C2_PORT 1 -#define STM32_I2C3_PORT 2 -#define STM32_FMPI2C4_PORT 3 - -#define stm32_i2c_reg(port, offset) \ - ((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset))) -/* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR_LPSDSR (1 << 0) -#define STM32_PWR_CR_FLPS (1 << 9) -#define STM32_PWR_CR_SVOS5 (1 << 14) -#define STM32_PWR_CR_SVOS4 (2 << 14) -#define STM32_PWR_CR_SVOS3 (3 << 14) -#define STM32_PWR_CR_SVOS_MASK (3 << 14) - -/* RTC domain control register */ -#define STM32_RCC_BDCR_BDRST BIT(16) -#define STM32_RCC_BDCR_RTCEN BIT(15) -#define STM32_RCC_BDCR_LSERDY BIT(1) -#define STM32_RCC_BDCR_LSEON BIT(0) -#define BDCR_RTCSEL_MASK ((0x3) << 8) -#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) -#define BDCR_SRC_LSE 0x1 -#define BDCR_SRC_LSI 0x2 -#define BDCR_SRC_HSE 0x3 -/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_TIM2 BIT(0) -#define STM32_RCC_PB1_TIM3 BIT(1) -#define STM32_RCC_PB1_TIM4 BIT(2) -#define STM32_RCC_PB1_TIM5 BIT(3) -#define STM32_RCC_PB1_TIM6 BIT(4) -#define STM32_RCC_PB1_TIM7 BIT(5) -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ -#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ -#define STM32_RCC_PB1_WWDG BIT(11) -#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ -#define STM32_RCC_PB1_SPI2 BIT(14) -#define STM32_RCC_PB1_SPI3 BIT(15) -#define STM32_RCC_PB1_USART2 BIT(17) -#define STM32_RCC_PB1_USART3 BIT(18) -#define STM32_RCC_PB1_USART4 BIT(19) -#define STM32_RCC_PB1_USART5 BIT(20) -#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SPI1 BIT(12) -/* Reset causes definitions */ - -/* --- Watchdogs --- */ - -#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00) -#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04) -#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) - -#define STM32_WWDG_TB_8 (3 << 7) -#define STM32_WWDG_EWI BIT(9) - -#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) -#define STM32_IWDG_KR_UNLOCK 0x5555 -#define STM32_IWDG_KR_RELOAD 0xaaaa -#define STM32_IWDG_KR_START 0xcccc -#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04) -#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) -#define STM32_IWDG_RLR_MAX 0x0fff -#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) -#define STM32_IWDG_SR_WVU BIT(2) -#define STM32_IWDG_SR_RVU BIT(1) -#define STM32_IWDG_SR_PVU BIT(0) -#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) - -/* --- Real-Time Clock --- */ -/* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) -/* --- Routing interface --- */ -/* STM32L1xx only */ -#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04) -#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08) -#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C) -#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10) -#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14) -#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18) -#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C) -#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20) -#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24) -#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28) -#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30) -#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34) -#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38) -#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C) -#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40) -#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44) -#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48) -#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C) -#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50) -#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54) -#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58) - -/* --- DAC --- */ -#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00) -#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04) -#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08) -#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C) -#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10) -#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14) -#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18) -#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C) -#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20) -#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24) -#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28) -#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C) -#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) -#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) - -#define STM32_DAC_CR_DMAEN2 BIT(28) -#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) -#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) -#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) -#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19) -#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) -#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) -#define STM32_DAC_CR_TSEL2_MASK (7 << 19) -#define STM32_DAC_CR_TEN2 BIT(18) -#define STM32_DAC_CR_BOFF2 BIT(17) -#define STM32_DAC_CR_EN2 BIT(16) -#define STM32_DAC_CR_DMAEN1 BIT(12) -#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) -#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) -#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) -#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3) -#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) -#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) -#define STM32_DAC_CR_TSEL1_MASK (7 << 3) -#define STM32_DAC_CR_TEN1 BIT(2) -#define STM32_DAC_CR_BOFF1 BIT(1) -#define STM32_DAC_CR_EN1 BIT(0) -/* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -/* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) - -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) -#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - -/* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) - -/* --- AXI interconnect --- */ - -/* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) - -/* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) - -#endif /* !__ASSEMBLER__ */ - -#if defined(CHIP_FAMILY_STM32F0) -#include "registers-stm32f0.h" -#elif defined(CHIP_FAMILY_STM32F3) -#include "registers-stm32f3.h" -#elif defined(CHIP_FAMILY_STM32F4) -#include "registers-stm32f4.h" -#elif defined(CHIP_FAMILY_STM32F7) -#include "registers-stm32f7.h" -#elif defined(CHIP_FAMILY_STM32G4) -#include "registers-stm32g4.h" -#elif defined(CHIP_FAMILY_STM32H7) -#include "registers-stm32h7.h" -#elif defined(CHIP_FAMILY_STM32L) -#include "registers-stm32l.h" -#elif defined(CHIP_FAMILY_STM32L4) -#include "registers-stm32l4.h" -#elif defined(CHIP_FAMILY_STM32L5) -#include "registers-stm32l5.h" -#else -#error "Unsupported chip family" -#endif - -#endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c deleted file mode 100644 index 3dbbbc4fa9..0000000000 --- a/chip/stm32/spi.c +++ /dev/null @@ -1,747 +0,0 @@ -/* - * Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI driver for Chrome EC. - * - * This uses DMA to handle transmission and reception. - */ - -#include "chipset.h" -#include "clock.h" -#include "console.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "spi.h" -#include "stm32-dma.h" -#include "system.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) - -/* SPI FIFO registers */ -#ifdef CHIP_FAMILY_STM32H7 -#define SPI_TXDR REG8(&STM32_SPI1_REGS->txdr) -#define SPI_RXDR REG8(&STM32_SPI1_REGS->rxdr) -#else -#define SPI_TXDR STM32_SPI1_REGS->dr -#define SPI_RXDR STM32_SPI1_REGS->dr -#endif - -/* DMA channel option */ -static const struct dma_option dma_tx_option = { - STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -#ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH) -#endif -}; - -static const struct dma_option dma_rx_option = { - STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -#ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH) -#endif -}; - -/* - * Timeout to wait for SPI request packet - * - * This affects the slowest SPI clock we can support. A delay of 8192 us - * permits a 512-byte request at 500 KHz, assuming the master starts sending - * bytes as soon as it asserts chip select. That's as slow as we would - * practically want to run the SPI interface, since running it slower - * significantly impacts firmware update times. - */ -#define SPI_CMD_RX_TIMEOUT_US 8192 - -#ifdef CONFIG_SPI_PROTOCOL_V2 -/* - * Offset of output parameters needs to account for pad and framing bytes and - * one last past-end byte at the end so any additional bytes clocked out by - * the AP will have a known and identifiable value. - */ -#define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2) -#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES + 1) -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ -/* - * Max data size for a version 3 request/response packet. This is big enough - * to handle a request/response header, flash write offset/size, and 512 bytes - * of flash data. - */ -#define SPI_MAX_REQUEST_SIZE 0x220 -#define SPI_MAX_RESPONSE_SIZE 0x220 - -/* - * The AP blindly clocks back bytes over the SPI interface looking for a - * framing byte. So this preamble must always precede the actual response - * packet. Search for "spi-frame-header" in U-boot to see how that's - * implemented. - * - * The preamble must be 32-bit aligned so that the response buffer is also - * 32-bit aligned. - */ -static const uint8_t out_preamble[4] = { - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_FRAME_START, /* This is the byte which matters */ -}; - -/* - * Space allocation of the past-end status byte (EC_SPI_PAST_END) in the out_msg - * buffer. This seems to be dynamic because the F0 family needs to send it 4 - * times in order to make sure it actually stays at the repeating byte after DMA - * ends. - * - * See crosbug.com/p/31390 - */ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) -#define EC_SPI_PAST_END_LENGTH 4 -#else -#define EC_SPI_PAST_END_LENGTH 1 -#endif - -/* - * Our input and output buffers. These must be large enough for our largest - * message, including protocol overhead, and must be 32-bit aligned. - */ -static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) + - EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached; -static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached; -static uint8_t enabled; -#ifdef CONFIG_SPI_PROTOCOL_V2 -static struct host_cmd_handler_args args; -#endif -static struct host_packet spi_packet; - -/* - * This is set if SPI NSS raises to high while EC is still processing a - * command. - */ -static int setup_transaction_later; - -enum spi_state { - /* SPI not enabled (initial state, and when chipset is off) */ - SPI_STATE_DISABLED = 0, - - /* Setting up receive DMA */ - SPI_STATE_PREPARE_RX, - - /* Ready to receive next request */ - SPI_STATE_READY_TO_RX, - - /* Receiving request */ - SPI_STATE_RECEIVING, - - /* Processing request */ - SPI_STATE_PROCESSING, - - /* Sending response */ - SPI_STATE_SENDING, - - /* - * Received bad data - transaction started before we were ready, or - * packet header from host didn't parse properly. Ignoring received - * data. - */ - SPI_STATE_RX_BAD, -} state; - -/** - * Wait until we have received a certain number of bytes - * - * Watch the DMA receive channel until it has the required number of bytes, - * or a timeout occurs - * - * We keep an eye on the NSS line - if this goes high then the transaction is - * over so there is no point in trying to receive the bytes. - * - * @param rxdma RX DMA channel to watch - * @param needed Number of bytes that are needed - * @param nss GPIO signal for NSS control line - * @return 0 if bytes received, -1 if we hit a timeout or NSS went high - */ -static int wait_for_bytes(dma_chan_t *rxdma, int needed, - enum gpio_signal nss) -{ - timestamp_t deadline; - - ASSERT(needed <= sizeof(in_msg)); - deadline.val = 0; - while (1) { - if (dma_bytes_done(rxdma, sizeof(in_msg)) >= needed) - return 0; - if (gpio_get_level(nss)) - return -1; - if (!deadline.val) { - deadline = get_time(); - deadline.val += SPI_CMD_RX_TIMEOUT_US; - } - if (timestamp_expired(deadline, NULL)) - return -1; - } -} - -#ifdef CONFIG_SPI_PROTOCOL_V2 -/** - * Send a reply on a given port. - * - * The format of a reply is as per the command interface, with a number of - * preamble bytes before it. - * - * The format of a reply is a sequence of bytes: - * - * <hdr> <status> <len> <msg bytes> <sum> [<preamble byte>...] - * - * The hdr byte is just a tag to indicate that the real message follows. It - * signals the end of any preamble required by the interface. - * - * The length is the entire packet size, including the header, length bytes, - * message payload, checksum, and postamble byte. - * - * The preamble is at least 2 bytes, but can be longer if the STM takes ages - * to react to the incoming message. Since we send our first byte as the AP - * sends us the command, we clearly can't send anything sensible for that - * byte. The second byte must be written to the output register just when the - * command byte is ready (I think), so we can't do anything there either. - * Any processing we do may increase this delay. That's the reason for the - * preamble. - * - * It is interesting to note that it seems to be possible to run the SPI - * interface faster than the CPU clock with this approach. - * - * We keep an eye on the NSS line - if this goes high then the transaction is - * over so there is no point in trying to send the reply. - * - * @param txdma TX DMA channel to send on - * @param status Status result to send - * @param msg_ptr Message payload to send, which normally starts - * SPI_PROTO2_OFFSET bytes into out_msg - * @param msg_len Number of message bytes to send - */ -static void reply(dma_chan_t *txdma, - enum ec_status status, char *msg_ptr, int msg_len) -{ - char *msg = out_msg; - int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET; - int sum, i; - - ASSERT(msg_len + SPI_PROTO2_OVERHEAD <= sizeof(out_msg)); - - /* Add our header bytes - the first one might not actually be sent */ - msg[0] = EC_SPI_PROCESSING; - msg[1] = EC_SPI_FRAME_START; - msg[2] = status; - msg[3] = msg_len & 0xff; - - /* - * Calculate the checksum; includes the status and message length bytes - * but not the pad and framing bytes since those are stripped by the AP - * driver. - */ - sum = status + msg_len; - for (i = 0; i < msg_len; i++) { - int ch = msg_ptr[i]; - sum += ch; - if (need_copy) - msg[i + SPI_PROTO2_OFFSET] = ch; - } - - /* Add the checksum and get ready to send */ - msg[SPI_PROTO2_OFFSET + msg_len] = sum & 0xff; - msg[SPI_PROTO2_OFFSET + msg_len + 1] = EC_SPI_PAST_END; - dma_prepare_tx(&dma_tx_option, msg_len + SPI_PROTO2_OVERHEAD, msg); - - /* Kick off the DMA to send the data */ - dma_go(txdma); -} -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ - -/** - * Sends a byte over SPI without DMA - * - * This is mostly used when we want to relay status bytes to the AP while we're - * receiving the message and we're thinking about it. - * - * @note It may be sent 0, 1, or >1 times, depending on whether the host clocks - * the bus or not. Basically, the EC is saying "if you ask me what my status is, - * you'll get this value. But you're not required to ask, or you can ask - * multiple times." - * - * @param byte status byte to send, one of the EC_SPI_* #defines from - * ec_commands.h - */ -static void tx_status(uint8_t byte) -{ - stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS; - - SPI_TXDR = byte; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - /* It sends the byte 4 times in order to be sure it bypassed the FIFO - * from the STM32F0 line. - */ - spi->dr = byte; - spi->dr = byte; - spi->dr = byte; -#elif defined(CHIP_FAMILY_STM32H7) - spi->udrdr = byte; -#endif -} - -/** - * Get ready to receive a message from the master. - * - * Set up our RX DMA and disable our TX DMA. Set up the data output so that - * we will send preamble bytes. - */ -static void setup_for_transaction(void) -{ - stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS; - volatile uint8_t unused __attribute__((unused)); - - /* clear this as soon as possible */ - setup_transaction_later = 0; - -#ifndef CHIP_FAMILY_STM32H7 /* H7 is not ready to set status here */ - /* Not ready to receive yet */ - tx_status(EC_SPI_NOT_READY); -#endif - - /* We are no longer actively processing a transaction */ - state = SPI_STATE_PREPARE_RX; - - /* Stop sending response, if any */ - dma_disable(STM32_DMAC_SPI1_TX); - - /* - * Read unused bytes in case there are some pending; this prevents the - * receive DMA from getting that byte right when we start it. - */ - unused = SPI_RXDR; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - /* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */ - unused = spi->dr; - unused = spi->dr; - unused = spi->dr; -#endif - - /* Start DMA */ - dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg); - - /* Ready to receive */ - state = SPI_STATE_READY_TO_RX; - tx_status(EC_SPI_OLD_READY); - -#ifdef CHIP_FAMILY_STM32H7 - spi->cr1 |= STM32_SPI_CR1_SPE; -#endif -} - -/* Forward declaration */ -static void spi_init(void); - -/* - * If a setup_for_transaction() was postponed, call it now. - * Note that setup_for_transaction() cancels Tx DMA. - */ -static void check_setup_transaction_later(void) -{ - if (setup_transaction_later) { - spi_init(); /* Fix for bug chrome-os-partner:31390 */ - /* - * 'state' is set to SPI_STATE_READY_TO_RX. Somehow AP - * de-asserted the SPI NSS during the handler was running. - * Thus, the pending result will be dropped anyway. - */ - } -} - -#ifdef CONFIG_SPI_PROTOCOL_V2 -/** - * Called for V2 protocol to indicate that a command has completed - * - * Some commands can continue for a while. This function is called by - * host_command when it completes. - * - */ -static void spi_send_response(struct host_cmd_handler_args *args) -{ - enum ec_status result = args->result; - dma_chan_t *txdma; - - /* - * If we're not processing, then the AP has already terminated the - * transaction, and won't be listening for a response. - */ - if (state != SPI_STATE_PROCESSING) - return; - - /* state == SPI_STATE_PROCESSING */ - - if (args->response_size > args->response_max) - result = EC_RES_INVALID_RESPONSE; - - /* Transmit the reply */ - txdma = dma_get_channel(STM32_DMAC_SPI1_TX); - reply(txdma, result, args->response, args->response_size); - - /* - * Before the state is set to SENDING, any CS de-assertion would - * set setup_transaction_later to 1. - */ - state = SPI_STATE_SENDING; - check_setup_transaction_later(); -} -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ - -/** - * Called to send a response back to the host. - * - * Some commands can continue for a while. This function is called by - * host_command when it completes. - * - */ -static void spi_send_response_packet(struct host_packet *pkt) -{ - dma_chan_t *txdma; - - /* - * If we're not processing, then the AP has already terminated the - * transaction, and won't be listening for a response. - */ - if (state != SPI_STATE_PROCESSING) - return; - - /* state == SPI_STATE_PROCESSING */ - - /* Append our past-end byte, which we reserved space for. */ - ((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - /* Make sure we are going to be outputting it properly when the DMA - * ends due to the TX FIFO bug on the F0. See crosbug.com/p/31390 - */ - ((uint8_t *)pkt->response)[pkt->response_size + 1] = EC_SPI_PAST_END; - ((uint8_t *)pkt->response)[pkt->response_size + 2] = EC_SPI_PAST_END; - ((uint8_t *)pkt->response)[pkt->response_size + 3] = EC_SPI_PAST_END; -#endif - - /* Transmit the reply */ - txdma = dma_get_channel(STM32_DMAC_SPI1_TX); - dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size - + EC_SPI_PAST_END_LENGTH, out_msg); - dma_go(txdma); -#ifdef CHIP_FAMILY_STM32H7 - /* clear any previous underrun */ - STM32_SPI1_REGS->ifcr = STM32_SPI_SR_UDR; -#endif /* CHIP_FAMILY_STM32H7 */ - - /* - * Before the state is set to SENDING, any CS de-assertion would - * set setup_transaction_later to 1. - */ - state = SPI_STATE_SENDING; - check_setup_transaction_later(); -} - -/** - * Handle an event on the NSS pin - * - * A falling edge of NSS indicates that the master is starting a new - * transaction. A rising edge indicates that we have finished. - * - * @param signal GPIO signal for the NSS pin - */ -void spi_event(enum gpio_signal signal) -{ - dma_chan_t *rxdma; - uint16_t i; - - /* If not enabled, ignore glitches on NSS */ - if (!enabled) - return; - - /* Check chip select. If it's high, the AP ended a transaction. */ - if (gpio_get_level(GPIO_SPI1_NSS)) { - enable_sleep(SLEEP_MASK_SPI); - - /* - * If the buffer is still used by the host command, postpone - * the DMA rx setup. - */ - if (state == SPI_STATE_PROCESSING) { - setup_transaction_later = 1; - return; - } - - /* Set up for the next transaction */ - spi_init(); /* Fix for bug chrome-os-partner:31390 */ - return; - } - disable_sleep(SLEEP_MASK_SPI); - - /* Chip select is low = asserted */ - if (state != SPI_STATE_READY_TO_RX) { - /* - * AP started a transaction but we weren't ready for it. - * Tell AP we weren't ready, and ignore the received data. - */ - CPRINTS("SPI not ready"); - tx_status(EC_SPI_NOT_READY); - state = SPI_STATE_RX_BAD; - return; - } - - /* We're now inside a transaction */ - state = SPI_STATE_RECEIVING; - tx_status(EC_SPI_RECEIVING); - rxdma = dma_get_channel(STM32_DMAC_SPI1_RX); - - /* Wait for version, command, length bytes */ - if (wait_for_bytes(rxdma, 3, GPIO_SPI1_NSS)) - goto spi_event_error; - - if (in_msg[0] == EC_HOST_REQUEST_VERSION) { - /* Protocol version 3 */ - struct ec_host_request *r = (struct ec_host_request *)in_msg; - int pkt_size; - - /* Wait for the rest of the command header */ - if (wait_for_bytes(rxdma, sizeof(*r), GPIO_SPI1_NSS)) - goto spi_event_error; - - /* - * Check how big the packet should be. We can't just wait to - * see how much data the host sends, because it will keep - * sending extra data until we respond. - */ - pkt_size = host_request_expected_size(r); - if (pkt_size == 0 || pkt_size > sizeof(in_msg)) - goto spi_event_error; - - /* Wait for the packet data */ - if (wait_for_bytes(rxdma, pkt_size, GPIO_SPI1_NSS)) - goto spi_event_error; - - spi_packet.send_response = spi_send_response_packet; - - spi_packet.request = in_msg; - spi_packet.request_temp = NULL; - spi_packet.request_max = sizeof(in_msg); - spi_packet.request_size = pkt_size; - - /* Response must start with the preamble */ - memcpy(out_msg, out_preamble, sizeof(out_preamble)); - spi_packet.response = out_msg + sizeof(out_preamble); - /* Reserve space for the preamble and trailing past-end byte */ - spi_packet.response_max = sizeof(out_msg) - - sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH; - spi_packet.response_size = 0; - - spi_packet.driver_result = EC_RES_SUCCESS; - - /* Move to processing state */ - state = SPI_STATE_PROCESSING; - tx_status(EC_SPI_PROCESSING); - - host_packet_receive(&spi_packet); - return; - - } else if (in_msg[0] >= EC_CMD_VERSION0) { -#ifdef CONFIG_SPI_PROTOCOL_V2 - /* - * Protocol version 2 - * - * TODO(crosbug.com/p/20257): Remove once kernel supports - * version 3. - */ - -#ifdef CHIP_FAMILY_STM32F0 - CPRINTS("WARNING: Protocol version 2 is not supported on the F0" - " line due to crosbug.com/p/31390"); -#endif - - args.version = in_msg[0] - EC_CMD_VERSION0; - args.command = in_msg[1]; - args.params_size = in_msg[2]; - - /* Wait for parameters */ - if (wait_for_bytes(rxdma, 3 + args.params_size, GPIO_SPI1_NSS)) - goto spi_event_error; - - /* - * Params are not 32-bit aligned in protocol version 2. As a - * workaround, move them to the beginning of the input buffer - * so they are aligned. - */ - if (args.params_size) - memmove(in_msg, in_msg + 3, args.params_size); - - args.params = in_msg; - args.send_response = spi_send_response; - - /* Allow room for the header bytes */ - args.response = out_msg + SPI_PROTO2_OFFSET; - args.response_max = sizeof(out_msg) - SPI_PROTO2_OVERHEAD; - args.response_size = 0; - args.result = EC_RES_SUCCESS; - - /* Move to processing state */ - state = SPI_STATE_PROCESSING; - tx_status(EC_SPI_PROCESSING); - - host_command_received(&args); - return; -#else /* !defined(CONFIG_SPI_PROTOCOL_V2) */ - /* Protocol version 2 is deprecated. */ - CPRINTS("ERROR: Protocol V2 is not supported!"); -#endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ - } - - spi_event_error: - /* Error, timeout, or protocol we can't handle. Ignore data. */ - tx_status(EC_SPI_RX_BAD_DATA); - state = SPI_STATE_RX_BAD; - CPRINTS("SPI rx bad data"); - - CPRINTF("in_msg=["); - for (i = 0; i < dma_bytes_done(rxdma, sizeof(in_msg)); i++) - CPRINTF("%02x ", in_msg[i]); - CPRINTF("]\n"); -} - -static void spi_chipset_startup(void) -{ - /* Enable pullup and interrupts on NSS */ - gpio_set_flags(GPIO_SPI1_NSS, GPIO_INT_BOTH | GPIO_PULL_UP); - - /* Set SPI pins to alternate function */ - gpio_config_module(MODULE_SPI, 1); - - /* Set up for next transaction */ - setup_for_transaction(); - - enabled = 1; -} -#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK -DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, spi_chipset_startup, HOOK_PRIO_DEFAULT); -#else -DECLARE_HOOK(HOOK_CHIPSET_RESUME, spi_chipset_startup, HOOK_PRIO_DEFAULT); -#endif - -static void spi_chipset_shutdown(void) -{ - enabled = 0; - state = SPI_STATE_DISABLED; - - /* Disable pullup and interrupts on NSS */ - gpio_set_flags(GPIO_SPI1_NSS, GPIO_INPUT); - - /* Set SPI pins to inputs so we don't leak power when AP is off */ - gpio_config_module(MODULE_SPI, 0); - - /* Allow deep sleep when AP off */ - enable_sleep(SLEEP_MASK_SPI); -} -#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND_COMPLETE, spi_chipset_shutdown, - HOOK_PRIO_DEFAULT); -#else -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, spi_chipset_shutdown, HOOK_PRIO_DEFAULT); -#endif - -static void spi_init(void) -{ - stm32_spi_regs_t *spi = STM32_SPI1_REGS; - uint8_t was_enabled = enabled; - - /* Reset the SPI Peripheral to clear any existing weird states. */ - /* Fix for bug chrome-os-partner:31390 */ - enabled = 0; - state = SPI_STATE_DISABLED; - STM32_RCC_APB2RSTR |= STM32_RCC_PB2_SPI1; - STM32_RCC_APB2RSTR &= ~STM32_RCC_PB2_SPI1; - - /* 40 MHz pin speed */ - STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00; - - /* Enable clocks to SPI1 module */ - STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; - - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - - /* - * Select the right DMA request for the variants using it. - * This is not required for STM32F4 since the channel (aka request) is - * set directly in the respective dma_option. In fact, it would be - * overridden in dma-stm32f4::prepare_stream(). - */ -#ifdef CHIP_FAMILY_STM32L4 - dma_select_channel(STM32_DMAC_SPI1_TX, 1); - dma_select_channel(STM32_DMAC_SPI1_RX, 1); -#elif defined(CHIP_FAMILY_STM32H7) - dma_select_channel(STM32_DMAC_SPI1_TX, DMAMUX1_REQ_SPI1_TX); - dma_select_channel(STM32_DMAC_SPI1_RX, DMAMUX1_REQ_SPI1_RX); -#endif - /* - * Enable rx/tx DMA and get ready to receive our first transaction and - * "disable" FIFO by setting event to happen after only 1 byte - */ -#ifdef CHIP_FAMILY_STM32H7 - spi->cfg2 = 0; - spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) | - STM32_SPI_CFG1_CRCSIZE(8) | - STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN | - STM32_SPI_CFG1_UDRCFG_CONST | - STM32_SPI_CFG1_UDRDET_BEGIN_FRM; - spi->cr1 = 0; -#else /* !CHIP_FAMILY_STM32H7 */ - spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); - - /* Enable the SPI peripheral */ - spi->cr1 |= STM32_SPI_CR1_SPE; -#endif /* !CHIP_FAMILY_STM32H7 */ - - gpio_enable_interrupt(GPIO_SPI1_NSS); - - /* - * If we were already enabled or chipset is already on, - * prepare for transaction - */ - if (was_enabled || chipset_in_state(CHIPSET_STATE_ON)) - spi_chipset_startup(); -} -DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI); - -/** - * Get protocol information - */ -enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); -#ifdef CONFIG_SPI_PROTOCOL_V2 - r->protocol_versions |= BIT(2); -#endif - r->protocol_versions |= BIT(3); - r->max_request_packet_size = SPI_MAX_REQUEST_SIZE; - r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE; - r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; - - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} diff --git a/chip/stm32/spi_master-stm32h7.c b/chip/stm32/spi_master-stm32h7.c deleted file mode 100644 index 4195dc595a..0000000000 --- a/chip/stm32/spi_master-stm32h7.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI master driver. - */ - -#include "common.h" -#include "dma.h" -#include "gpio.h" -#include "shared_mem.h" -#include "spi.h" -#include "stm32-dma.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* SPI ports are used as master */ -static stm32_spi_regs_t *SPI_REGS[] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - STM32_SPI1_REGS, -#endif - STM32_SPI2_REGS, - STM32_SPI3_REGS, - STM32_SPI4_REGS, -}; - -/* DMA request mapping on channels */ -static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - DMAMUX1_REQ_SPI1_TX, -#endif - DMAMUX1_REQ_SPI2_TX, - DMAMUX1_REQ_SPI3_TX, - DMAMUX1_REQ_SPI4_TX, -}; -static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - DMAMUX1_REQ_SPI1_RX, -#endif - DMAMUX1_REQ_SPI2_RX, - DMAMUX1_REQ_SPI3_RX, - DMAMUX1_REQ_SPI4_RX, -}; - -static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; - -#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC) - -static const struct dma_option dma_tx_option[] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -#endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -}; - -static const struct dma_option dma_rx_option[] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -#endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, -}; - -static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; - -/** - * Initialize SPI module, registers, and clocks - * @param spi_device device to initialize. - */ -static void spi_master_config(const struct spi_device_t *spi_device) -{ - int port = spi_device->port; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* - * Set SPI master, baud rate, and software slave control. - */ - spi->cr1 = STM32_SPI_CR1_SSI; - spi->cfg2 = STM32_SPI_CFG2_MSTR | STM32_SPI_CFG2_SSM | - STM32_SPI_CFG2_AFCNTR; - spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) | - STM32_SPI_CFG1_CRCSIZE(8) | - STM32_SPI_CR1_DIV(spi_device->div); - - dma_select_channel(dma_tx_option[port].channel, dma_req_tx[port]); - dma_select_channel(dma_rx_option[port].channel, dma_req_rx[port]); -} - -static int spi_master_initialize(const struct spi_device_t *spi_device) -{ - spi_master_config(spi_device); - - gpio_set_level(spi_device->gpio_cs, 1); - - /* Set flag */ - spi_enabled[spi_device->port] = 1; - - return EC_SUCCESS; -} - -/** - * Shutdown SPI module - */ -static int spi_master_shutdown(const struct spi_device_t *spi_device) -{ - int rv = EC_SUCCESS; - int port = spi_device->port; - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* Set flag */ - spi_enabled[port] = 0; - - /* Disable DMA streams */ - dma_disable(dma_tx_option[port].channel); - dma_disable(dma_rx_option[port].channel); - - /* Disable SPI */ - spi->cr1 &= ~STM32_SPI_CR1_SPE; - - /* Disable DMA buffers */ - spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN); - - return rv; -} - -int spi_enable(const struct spi_device_t *spi_device, int enable) -{ - int port = spi_device->port; - if (enable == spi_enabled[port]) - return EC_SUCCESS; - if (enable) - return spi_master_initialize(spi_device); - else - return spi_master_shutdown(spi_device); -} - -static int spi_dma_start(const struct spi_device_t *spi_device, - const uint8_t *txdata, uint8_t *rxdata, int len) -{ - dma_chan_t *txdma; - int port = spi_device->port; - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* - * Workaround for STM32H7 errata: without resetting the SPI controller, - * the RX DMA requests will happen too early on the 2nd transfer. - */ - STM32_RCC_APB2RSTR = STM32_RCC_PB2_SPI4; - STM32_RCC_APB2RSTR = 0; - dma_clear_isr(dma_tx_option[port].channel); - dma_clear_isr(dma_rx_option[port].channel); - /* restore proper SPI configuration registers. */ - spi_master_config(spi_device); - - spi->cr2 = len; - spi->cfg1 |= STM32_SPI_CFG1_RXDMAEN; - /* Set up RX DMA */ - if (rxdata) - dma_start_rx(&dma_rx_option[port], len, rxdata); - - /* Set up TX DMA */ - if (txdata) { - txdma = dma_get_channel(dma_tx_option[port].channel); - dma_prepare_tx(&dma_tx_option[port], len, txdata); - dma_go(txdma); - } - - spi->cfg1 |= STM32_SPI_CFG1_TXDMAEN; - spi->cr1 |= STM32_SPI_CR1_SPE; - spi->cr1 |= STM32_SPI_CR1_CSTART; - - return EC_SUCCESS; -} - -static inline bool dma_is_enabled_(const struct dma_option *option) -{ - return dma_is_enabled(dma_get_channel(option->channel)); -} - -static int spi_dma_wait(int port) -{ - timestamp_t timeout; - stm32_spi_regs_t *spi = SPI_REGS[port]; - int rv = EC_SUCCESS; - - /* Wait for DMA transmission to complete */ - if (dma_is_enabled_(&dma_tx_option[port])) { - rv = dma_wait(dma_tx_option[port].channel); - if (rv) - return rv; - - timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC; - /* Wait for FIFO empty and BSY bit clear */ - while (!(spi->sr & (STM32_SPI_SR_TXC))) - if (get_time().val > timeout.val) - return EC_ERROR_TIMEOUT; - - /* Disable TX DMA */ - dma_disable(dma_tx_option[port].channel); - } - - /* Wait for DMA reception to complete */ - if (dma_is_enabled_(&dma_rx_option[port])) { - rv = dma_wait(dma_rx_option[port].channel); - if (rv) - return rv; - - timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC; - /* Wait for FRLVL[1:0] to indicate FIFO empty */ - while (spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE)) - if (get_time().val > timeout.val) - return EC_ERROR_TIMEOUT; - - /* Disable RX DMA */ - dma_disable(dma_rx_option[port].channel); - } - - spi->cr1 &= ~STM32_SPI_CR1_SPE; - spi->cfg1 &= ~(STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN); - - return rv; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv = EC_SUCCESS; - int port = spi_device->port; - int full_readback = 0; - - char *buf = NULL; - -#ifndef CONFIG_SPI_HALFDUPLEX - if (rxlen == SPI_READBACK_ALL) { - buf = rxdata; - full_readback = 1; - } else { - rv = shared_mem_acquire(MAX(txlen, rxlen), &buf); - if (rv != EC_SUCCESS) - return rv; - } -#endif - - /* Drive SS low */ - gpio_set_level(spi_device->gpio_cs, 0); - - rv = spi_dma_start(spi_device, txdata, buf, txlen); - if (rv != EC_SUCCESS) - goto err_free; - - if (full_readback) - return EC_SUCCESS; - - if (rxlen) { - rv = spi_dma_wait(port); - if (rv != EC_SUCCESS) - goto err_free; - - rv = spi_dma_start(spi_device, buf, rxdata, rxlen); - if (rv != EC_SUCCESS) - goto err_free; - } - -err_free: - if (!full_readback) - shared_mem_release(buf); - return rv; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int rv = spi_dma_wait(spi_device->port); - - /* Drive SS high */ - gpio_set_level(spi_device->gpio_cs, 1); - - return rv; -} - -int spi_transaction_wait(const struct spi_device_t *spi_device) -{ - return spi_dma_wait(spi_device->port); -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv; - int port = spi_device->port; - - mutex_lock(spi_mutex + port); - rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - rv |= spi_transaction_flush(spi_device); - mutex_unlock(spi_mutex + port); - - return rv; -} diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c deleted file mode 100644 index 8943c0c682..0000000000 --- a/chip/stm32/spi_master.c +++ /dev/null @@ -1,429 +0,0 @@ -/* - * Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * SPI master driver. - */ - -#include "common.h" -#include "dma.h" -#include "gpio.h" -#include "hwtimer.h" -#include "shared_mem.h" -#include "spi.h" -#include "stm32-dma.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -#if defined(CHIP_VARIANT_STM32F373) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_VARIANT_STM32F76X) -#define HAS_SPI3 -#else -#undef HAS_SPI3 -#endif - -/* The second (and third if available) SPI port are used as master */ -static stm32_spi_regs_t *SPI_REGS[] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - STM32_SPI1_REGS, -#endif - STM32_SPI2_REGS, -#ifdef HAS_SPI3 - STM32_SPI3_REGS, -#endif -}; - -#ifdef CHIP_FAMILY_STM32L4 -/* DMA request mapping on channels */ -static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - /* SPI1 */ 1, -#endif - /* SPI2 */ 1, - /* SPI3 */ 3, -}; -#endif - -static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; - -#define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC) - -/* Default DMA channel options */ -#ifdef CHIP_FAMILY_STM32F4 -#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch) -#else -#define F4_CHANNEL(ch) 0 -#endif - -static const struct dma_option dma_tx_option[] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_TX_REQ_CH) - }, -#endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_TX_REQ_CH) - }, -#ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_TX_REQ_CH) - }, -#endif -}; - -static const struct dma_option dma_rx_option[] = { -#ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_RX_REQ_CH) - }, -#endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_RX_REQ_CH) - }, -#ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_RX_REQ_CH) - }, -#endif -}; - -static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; - -static int spi_tx_done(stm32_spi_regs_t *spi) -{ - return !(spi->sr & (STM32_SPI_SR_FTLVL | STM32_SPI_SR_BSY)); -} - -static int spi_rx_done(stm32_spi_regs_t *spi) -{ - return !(spi->sr & (STM32_SPI_SR_FRLVL | STM32_SPI_SR_RXNE)); -} - -/* Read until RX FIFO is empty (i.e. RX done) */ -static int spi_clear_rx_fifo(stm32_spi_regs_t *spi) -{ - uint8_t unused __attribute__((unused)); - uint32_t start = __hw_clock_source_read(), delta; - - while (!spi_rx_done(spi)) { - unused = spi->dr; /* Read one byte from FIFO */ - delta = __hw_clock_source_read() - start; - if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) - return EC_ERROR_TIMEOUT; - } - return EC_SUCCESS; -} - -/* Wait until TX FIFO is empty (i.e. TX done) */ -static int spi_clear_tx_fifo(stm32_spi_regs_t *spi) -{ - uint32_t start = __hw_clock_source_read(), delta; - - while (!spi_tx_done(spi)) { - /* wait for TX complete */ - delta = __hw_clock_source_read() - start; - if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) - return EC_ERROR_TIMEOUT; - } - return EC_SUCCESS; -} - -/** - * Initialize SPI module, registers, and clocks - * - * - port: which port to initialize. - */ -static int spi_master_initialize(const struct spi_device_t *spi_device) -{ - int port = spi_device->port; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* - * Set SPI master, baud rate, and software slave control. - * */ - - /* - * STM32F412 - * Section 26.3.5 Slave select (NSS) pin management and Figure 276 - * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=817 - * - * The documentation in this section is a bit confusing, so here's a - * summary based on discussion with ST: - * - * Software NSS management (SSM = 1): - * - In master mode, the NSS output is deactivated. You need to use a - * GPIO in output mode for slave select. This is generally used for - * multi-slave operation, but you can also use it for single slave - * operation. In this case, you should make sure to configure a GPIO - * for NSS, but *not* activate the SPI alternate function on that - * same pin since that will enable hardware NSS management (see - * below). - * - In slave mode, the NSS input level is equal to the SSI bit value. - * - * Hardware NSS management (SSM = 0): - * - In slave mode, when NSS pin is detected low the slave (MCU) is - * selected. - * - In master mode, there are two configurations, depending on the - * SSOE bit in register SPIx_CR1. - * - NSS output enable (SSM=0, SSOE=1): - * The MCU (master) drives NSS low as soon as SPI is enabled - * (SPE=1) and releases it when SPI is disabled (SPE=0). - * - * - NSS output disable (SSM=0, SSOE=0): - * Allows multimaster capability. The MCU (master) drives NSS - * low. If another master tries to takes control of the bus and - * NSS is pulled low, a mode fault is generated and the MCU - * changes to slave mode. - * - * - NSS output disable (SSM=0, SSOE=0): if the MCU is acting as - * master on the bus, this config allows multimaster capability. If - * the NSS pin is pulled low in this mode, the SPI enters master - * mode fault state and the device is automatically reconfigured in - * slave mode. In slave mode, the NSS pin works as a standard "chip - * select" input and the slave is selected while NSS lin is at low - * level. - */ - spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI | - (spi_device->div << 3); - -#ifdef CHIP_FAMILY_STM32L4 - dma_select_channel(dma_tx_option[port].channel, dma_req[port]); - dma_select_channel(dma_rx_option[port].channel, dma_req[port]); -#endif - /* - * Configure 8-bit datasize, set FRXTH, enable DMA, - * and set data size (applies to STM32F0 only). - * - * STM32F412: - * https://www.st.com/resource/en/reference_manual/dm00180369.pdf#page=852 - * - * - * STM32F0: - * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803 - */ - spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); - -#ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE; -#endif - - /* Drive Chip Select high before turning on SPI module */ - gpio_set_level(spi_device->gpio_cs, 1); - - /* Enable SPI hardware module. This will actively drive the CLK pin */ - spi->cr1 |= STM32_SPI_CR1_SPE; - - /* Set flag */ - spi_enabled[port] = 1; - - return EC_SUCCESS; -} - -/** - * Shutdown SPI module - */ -static int spi_master_shutdown(const struct spi_device_t *spi_device) -{ - int rv = EC_SUCCESS; - int port = spi_device->port; - stm32_spi_regs_t *spi = SPI_REGS[port]; - - /* Set flag */ - spi_enabled[port] = 0; - - /* Disable DMA streams */ - dma_disable(dma_tx_option[port].channel); - dma_disable(dma_rx_option[port].channel); - - /* Disable SPI. Let the CLK pin float. */ - spi->cr1 &= ~STM32_SPI_CR1_SPE; - - spi_clear_rx_fifo(spi); - - /* Disable DMA buffers */ - spi->cr2 &= ~(STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN); - - return rv; -} - -int spi_enable(const struct spi_device_t *spi_device, int enable) -{ - if (enable == spi_enabled[spi_device->port]) - return EC_SUCCESS; - if (enable) - return spi_master_initialize(spi_device); - else - return spi_master_shutdown(spi_device); -} - -static int spi_dma_start(int port, const uint8_t *txdata, - uint8_t *rxdata, int len) -{ - dma_chan_t *txdma; - - /* Set up RX DMA */ - if (rxdata) - dma_start_rx(&dma_rx_option[port], len, rxdata); - - /* Set up TX DMA */ - if (txdata) { - txdma = dma_get_channel(dma_tx_option[port].channel); - dma_prepare_tx(&dma_tx_option[port], len, txdata); - dma_go(txdma); - } - - return EC_SUCCESS; -} - -static bool dma_is_enabled_(const struct dma_option *option) -{ - return dma_is_enabled(dma_get_channel(option->channel)); -} - -static int spi_dma_wait(int port) -{ - int rv = EC_SUCCESS; - - /* Wait for DMA transmission to complete */ - if (dma_is_enabled_(&dma_tx_option[port])) { - /* - * In TX mode, SPI only generates clock when we write to FIFO. - * Therefore, even though `dma_wait` polls with interval 0.1ms, - * we won't send extra bytes. - */ - rv = dma_wait(dma_tx_option[port].channel); - if (rv) - return rv; - /* Disable TX DMA */ - dma_disable(dma_tx_option[port].channel); - } - - /* Wait for DMA reception to complete */ - if (dma_is_enabled_(&dma_rx_option[port])) { - /* - * Because `dma_wait` polls with interval 0.1ms, we will read at - * least ~100 bytes (with 8MHz clock). If you don't want this - * overhead, you can use interrupt handler - * (`dma_enable_tc_interrupt_callback`) and disable SPI - * interface in callback function. - */ - rv = dma_wait(dma_rx_option[port].channel); - if (rv) - return rv; - /* Disable RX DMA */ - dma_disable(dma_rx_option[port].channel); - } - return rv; -} - -int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv = EC_SUCCESS; - int port = spi_device->port; - int full_readback = 0; - - stm32_spi_regs_t *spi = SPI_REGS[port]; - char *buf = NULL; - - /* We should not ever be called when disabled, but fail early if so. */ - if (!spi_enabled[port]) - return EC_ERROR_BUSY; - -#ifndef CONFIG_SPI_HALFDUPLEX - if (rxlen == SPI_READBACK_ALL) { - buf = rxdata; - full_readback = 1; - } else { - rv = shared_mem_acquire(MAX(txlen, rxlen), &buf); - if (rv != EC_SUCCESS) - return rv; - } -#endif - - /* Drive SS low */ - gpio_set_level(spi_device->gpio_cs, 0); - - spi_clear_rx_fifo(spi); - - rv = spi_dma_start(port, txdata, buf, txlen); - if (rv != EC_SUCCESS) - goto err_free; - -#ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 |= STM32_SPI_CR1_BIDIOE; -#endif - - if (full_readback) - return EC_SUCCESS; - - rv = spi_dma_wait(port); - if (rv != EC_SUCCESS) - goto err_free; - - spi_clear_tx_fifo(spi); - - if (rxlen) { - rv = spi_dma_start(port, buf, rxdata, rxlen); - if (rv != EC_SUCCESS) - goto err_free; -#ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 &= ~STM32_SPI_CR1_BIDIOE; -#endif - } - -err_free: -#ifndef CONFIG_SPI_HALFDUPLEX - if (!full_readback) - shared_mem_release(buf); -#endif - return rv; -} - -int spi_transaction_flush(const struct spi_device_t *spi_device) -{ - int rv = spi_dma_wait(spi_device->port); - - /* Drive SS high */ - gpio_set_level(spi_device->gpio_cs, 1); - - return rv; -} - -int spi_transaction_wait(const struct spi_device_t *spi_device) -{ - return spi_dma_wait(spi_device->port); -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int rv; - int port = spi_device->port; - - mutex_lock(spi_mutex + port); - rv = spi_transaction_async(spi_device, txdata, txlen, rxdata, rxlen); - rv |= spi_transaction_flush(spi_device); - mutex_unlock(spi_mutex + port); - - return rv; -} diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h deleted file mode 100644 index 06233b9c93..0000000000 --- a/chip/stm32/stm32-dma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * Select DMA stream-channel mapping - * - * This selects which stream (peripheral) to be used on a specific channel. - * Some STM32 chips simply logically OR requests, thus do not require this - * selection. - * - * @param channel: (Global) channel # base 0 (Note some STM32s use base 1) - * @param peripheral: Refer to the TRM for 'peripheral request signals' - */ -void dma_select_channel(enum dma_channel channel, unsigned char stream); diff --git a/chip/stm32/system.c b/chip/stm32/system.c deleted file mode 100644 index 03e9a74ac4..0000000000 --- a/chip/stm32/system.c +++ /dev/null @@ -1,631 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* System module for Chrome EC : hardware specific implementation */ - -#include "bkpdata.h" -#include "clock.h" -#include "console.h" -#include "cpu.h" -#include "cros_version.h" -#include "flash.h" -#include "gpio_chip.h" -#include "hooks.h" -#include "host_command.h" -#include "panic.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" -#include "watchdog.h" - -#ifdef CONFIG_STM32_CLOCK_LSE -#define BDCR_SRC BDCR_SRC_LSE -#define BDCR_RDY STM32_RCC_BDCR_LSERDY -#else -#define BDCR_SRC BDCR_SRC_LSI -#define BDCR_RDY 0 -#endif -#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \ - BDCR_RDY) -#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \ - STM32_RCC_BDCR_BDRST) - -#ifdef CONFIG_USB_PD_DUAL_ROLE -BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3); -#endif - -void __no_hibernate(uint32_t seconds, uint32_t microseconds) -{ -#ifdef CONFIG_COMMON_RUNTIME - /* - * Hibernate not implemented on this platform. - * - * Until then, treat this as a request to hard-reboot. - */ - cprints(CC_SYSTEM, "hibernate not supported, so rebooting"); - cflush(); - system_reset(SYSTEM_RESET_HARD); -#endif -} - -void __enter_hibernate(uint32_t seconds, uint32_t microseconds) - __attribute__((weak, alias("__no_hibernate"))); - -void system_hibernate(uint32_t seconds, uint32_t microseconds) -{ -#ifdef CONFIG_HOSTCMD_PD - /* Inform the PD MCU that we are going to hibernate. */ - host_command_pd_request_hibernate(); - /* Wait to ensure exchange with PD before hibernating. */ - msleep(100); -#endif - - /* Flush console before hibernating */ - cflush(); - - if (board_hibernate) - board_hibernate(); - - /* chip specific standby mode */ - __enter_hibernate(seconds, microseconds); -} - -uint32_t chip_read_reset_flags(void) -{ - return bkpdata_read_reset_flags(); -} - -void chip_save_reset_flags(uint32_t flags) -{ - bkpdata_write_reset_flags(flags); -} - -static void check_reset_cause(void) -{ - uint32_t flags = chip_read_reset_flags(); - uint32_t raw_cause = STM32_RCC_RESET_CAUSE; -#ifdef STM32_PWR_RESET_CAUSE - uint32_t pwr_status = STM32_PWR_RESET_CAUSE; -#endif - - /* Clear the hardware reset cause by setting the RMVF bit */ - STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF; -#ifdef STM32_PWR_RESET_CAUSE - /* Clear SBF in PWR_CSR */ - STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR; -#endif - /* Clear saved reset flags */ - chip_save_reset_flags(0); - - if (raw_cause & RESET_CAUSE_WDG) { - /* - * IWDG or WWDG, if the watchdog was not used as an hard reset - * mechanism - */ - if (!(flags & EC_RESET_FLAG_HARD)) - flags |= EC_RESET_FLAG_WATCHDOG; - } - - if (raw_cause & RESET_CAUSE_SFT) - flags |= EC_RESET_FLAG_SOFT; - - if (raw_cause & RESET_CAUSE_POR) - flags |= EC_RESET_FLAG_POWER_ON; - - if (raw_cause & RESET_CAUSE_PIN) - flags |= EC_RESET_FLAG_RESET_PIN; - -#ifdef STM32_PWR_RESET_CAUSE - if (pwr_status & RESET_CAUSE_SBF) - /* Hibernated and subsequently awakened */ - flags |= EC_RESET_FLAG_HIBERNATE; -#endif - - if (!flags && (raw_cause & RESET_CAUSE_OTHER)) - flags |= EC_RESET_FLAG_OTHER; - - /* - * WORKAROUND: as we cannot de-activate the watchdog during - * long hibernation, we are woken-up once by the watchdog and - * go back to hibernate if we detect that condition, without - * watchdog initialized this time. - * The RTC deadline (if any) is already set. - */ - if ((flags & EC_RESET_FLAG_HIBERNATE) && - (flags & EC_RESET_FLAG_WATCHDOG)) { - __enter_hibernate(0, 0); - } - - system_set_reset_flags(flags); -} - -/* Stop all timers and WDGs we might use when JTAG stops the CPU. */ -void chip_pre_init(void) -{ - uint32_t apb1fz_reg = 0; - uint32_t apb2fz_reg = 0; - -#if defined(CHIP_FAMILY_STM32F0) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | - STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; - - /* enable clock to debug module before writing */ - STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN; -#elif defined(CHIP_FAMILY_STM32F3) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; -#elif defined(CHIP_FAMILY_STM32F4) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14| - STM32_RCC_PB1_RTC | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | STM32_RCC_PB2_TIM9 | - STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; -#elif defined(CHIP_FAMILY_STM32L4) - -#ifdef CHIP_VARIANT_STM32L431X - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16; -#else - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; -#endif -#elif defined(CHIP_FAMILY_STM32L) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | - STM32_RCC_PB2_TIM11; -#elif defined(CHIP_FAMILY_STM32G4) - apb1fz_reg = - STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 | - STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 | - STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 | - STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG | - STM32_DBGMCU_APB1FZ_IWDG; - apb2fz_reg = - STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 | - STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 | - STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20; -#elif defined(CHIP_FAMILY_STM32H7) - /* TODO(b/67081508) */ -#endif -#if defined(CHIP_FAMILY_STM32L5) - (void)apb1fz_reg; - (void)apb2fz_reg; -#else - if (apb1fz_reg) - STM32_DBGMCU_APB1FZ |= apb1fz_reg; - if (apb2fz_reg) - STM32_DBGMCU_APB2FZ |= apb2fz_reg; -#endif -} - -#ifdef CONFIG_PVD -/****************************************************************************** - * Detects sagging Vdd voltage and resets the system via the programmable - * voltage detector interrupt. - */ -static void configure_pvd(void) -{ - /* Clear Interrupt Enable Mask Register. */ - STM32_EXTI_IMR &= ~EXTI_PVD_EVENT; - - /* Clear Rising and Falling Trigger Selection Registers. */ - STM32_EXTI_RTSR &= ~EXTI_PVD_EVENT; - STM32_EXTI_FTSR &= ~EXTI_PVD_EVENT; - - /* Clear the value of the PVD Level Selection. */ - STM32_PWR_CR &= ~STM32_PWD_PVD_LS_MASK; - - /* Set the new value of the PVD Level Selection. */ - STM32_PWR_CR |= STM32_PWD_PVD_LS(PVD_THRESHOLD); - - /* Enable Power Clock. */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_PWREN; - - /* Configure the NVIC for PVD. */ - task_enable_irq(STM32_IRQ_PVD); - - /* Configure interrupt mode. */ - STM32_EXTI_IMR |= EXTI_PVD_EVENT; - STM32_EXTI_RTSR |= EXTI_PVD_EVENT; - - /* Enable the PVD Output. */ - STM32_PWR_CR |= STM32_PWR_PVDE; -} - -void pvd_interrupt(void) -{ - /* Clear Pending Register */ - STM32_EXTI_PR = EXTI_PVD_EVENT; - /* Handle recovery by rebooting the system */ - system_reset(0); -} -DECLARE_IRQ(STM32_IRQ_PVD, pvd_interrupt, HOOK_PRIO_FIRST); - -#endif /* CONFIG_PVD */ - -void system_pre_init(void) -{ -#ifdef CONFIG_SOFTWARE_PANIC - uint16_t reason, info; - uint8_t exception, panic_flags; -#endif - - /* enable clock on Power module */ -#ifndef CHIP_FAMILY_STM32H7 -#ifdef CHIP_FAMILY_STM32L4 - STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; -#else - STM32_RCC_APB1ENR |= STM32_RCC_PWREN; -#endif -#endif -#if defined(CHIP_FAMILY_STM32F4) - /* enable backup registers */ - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN; -#elif defined(CHIP_FAMILY_STM32H7) - /* enable backup registers */ - STM32_RCC_AHB4ENR |= BIT(28); -#elif defined(CHIP_FAMILY_STM32L4) - /* enable RTC APB clock */ - STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_RTCAPBEN; -#else - /* enable backup registers */ - STM32_RCC_APB1ENR |= BIT(27); -#endif - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - /* Enable access to RCC CSR register and RTC backup registers */ - STM32_PWR_CR |= BIT(8); -#ifdef CHIP_VARIANT_STM32L476 - /* Enable Vddio2 */ - STM32_PWR_CR2 |= BIT(9); -#endif - - /* switch on LSI */ - STM32_RCC_CSR |= BIT(0); - /* Wait for LSI to be ready */ - while (!(STM32_RCC_CSR & BIT(1))) - ; - -#if defined(CHIP_FAMILY_STM32G4) - /* Make sure PWR clock is enabled */ - STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN; - /* Enable access to backup domain registers */ - STM32_PWR_CR1 |= STM32_PWR_CR1_DBP; -#endif - /* re-configure RTC if needed */ -#ifdef CHIP_FAMILY_STM32L - if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) { - /* The RTC settings are bad, we need to reset it */ - STM32_RCC_CSR |= 0x00800000; - /* Enable RTC and use LSI as clock source */ - STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000; - } -#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) || \ - defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4) - if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) { - /* The RTC settings are bad, we need to reset it */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; - STM32_RCC_BDCR = STM32_RCC_BDCR & ~BDCR_ENABLE_MASK; -#ifdef CONFIG_STM32_CLOCK_LSE - /* Turn on LSE */ - STM32_RCC_BDCR |= STM32_RCC_BDCR_LSEON; - /* Wait for LSE to be ready */ - while (!(STM32_RCC_BDCR & STM32_RCC_BDCR_LSERDY)) - ; -#endif - /* Select clock source and enable RTC */ - STM32_RCC_BDCR |= BDCR_RTCSEL(BDCR_SRC) | STM32_RCC_BDCR_RTCEN; - } -#else -#error "Unsupported chip family" -#endif - - check_reset_cause(); - -#ifdef CONFIG_SOFTWARE_PANIC - /* Restore then clear saved panic reason */ - reason = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_REASON); - info = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_INFO); - exception = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION); - panic_flags = bkpdata_read(BKPDATA_INDEX_SAVED_PANIC_FLAGS); - if (reason || info || exception || panic_flags) { - panic_set_reason(reason, info, exception); - panic_get_data()->flags = panic_flags; - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, 0); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, 0); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, 0); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, 0); - } -#endif - -#ifdef CONFIG_PVD - configure_pvd(); -#endif -} - -void system_reset(int flags) -{ - uint32_t save_flags = 0; - - /* Disable interrupts to avoid task swaps during reboot */ - interrupt_disable(); - - /* - * TODO(crbug.com/1045283): Change this part of code to use - * system_encode_save_flags, like all other system_reset functions. - * - * system_encode_save_flags(flags, &save_flags); - */ - - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | EC_RESET_FLAG_PRESERVED; - - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= EC_RESET_FLAG_AP_OFF; - - /* Remember that the software asked us to hard reboot */ - if (flags & SYSTEM_RESET_HARD) - save_flags |= EC_RESET_FLAG_HARD; - - /* Add in stay in RO flag into saved flags. */ - if (flags & SYSTEM_RESET_STAY_IN_RO) - save_flags |= EC_RESET_FLAG_STAY_IN_RO; - - if (flags & SYSTEM_RESET_AP_WATCHDOG) - save_flags |= EC_RESET_FLAG_AP_WATCHDOG; - - chip_save_reset_flags(save_flags); - -#ifdef CONFIG_ARMV7M_CACHE - /* - * Disable caches (D-cache is also flushed and invalidated) - * so changes that lives in cache are saved in memory now. - * Any subsequent writes will be done immediately. - */ - cpu_disable_caches(); -#endif - - if (flags & SYSTEM_RESET_HARD) { -#ifdef CONFIG_SOFTWARE_PANIC - uint32_t reason, info; - uint8_t exception; - uint8_t panic_flags = panic_get_data()->flags; - - /* Panic data will be wiped by hard reset, so save it */ - panic_get_reason(&reason, &info, &exception); - /* 16 bits stored - upper 16 bits of reason / info are lost */ - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, exception); - bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, panic_flags); -#endif - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32L4) - /* - * Ask the flash module to reboot, so that we reload the - * option bytes. - */ - crec_flash_physical_force_reload(); - - /* Fall through to watchdog if that fails */ -#endif - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - /* - * On some chips, a reboot doesn't always reload the option - * bytes, and we need to explicitly request for a reload. - * The reload request triggers a chip reset, so let's just - * use this for hard reset. - */ - STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH; -#elif defined(CHIP_FAMILY_STM32G4) - STM32_FLASH_KEYR = FLASH_KEYR_KEY1; - STM32_FLASH_KEYR = FLASH_KEYR_KEY2; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; - STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; - STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH; -#else - /* - * RM0433 Rev 6 - * Section 44.3.3 - * https://www.st.com/resource/en/reference_manual/dm00314099.pdf#page=1898 - * - * When the window option is not used, the IWDG can be - * configured as follows: - * - * 1. Enable the IWDG by writing 0x0000 CCCC in the Key - * register (IWDG_KR). - * 2. Enable register access by writing 0x0000 5555 in the Key - * register (IWDG_KR). - * 3. Write the prescaler by programming the Prescaler register - * (IWDG_PR) from 0 to 7. - * 4. Write the Reload register (IWDG_RLR). - * 5. Wait for the registers to be updated - * (IWDG_SR = 0x0000 0000). - * 6. Refresh the counter value with IWDG_RLR - * (IWDG_KR = 0x0000 AAAA) - */ - - /* - * RM0433 Rev 7 - * Section 45.4.4 Page 1920 - * https://www.st.com/resource/en/reference_manual/dm00314099.pdf - * If several reload, prescaler, or window values are used by - * the application, it is mandatory to wait until RVU bit is - * reset before changing the reload value, to wait until PVU bit - * is reset before changing the prescaler value, and to wait - * until WVU bit is reset before changing the window value. - * - * Here we should wait to finish previous IWDG_RLR register - * update (see watchdog_init()) before starting next update, - * otherwise new IWDG_RLR value will be lost. - */ - while (STM32_IWDG_SR & STM32_IWDG_SR_RVU) - ; - - /* - * Enable IWDG, which shouldn't be necessary since the IWDG - * only needs to be started once, but STM32F412 hangs unless - * this is added. - * - * See http://b/137045370. - */ - STM32_IWDG_KR = STM32_IWDG_KR_START; - - /* Ask the watchdog to trigger a hard reboot */ - STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; - STM32_IWDG_RLR = 0x1; - /* Wait for value to be updated. */ - while (STM32_IWDG_SR & STM32_IWDG_SR_RVU) - ; - - /* Reload IWDG counter, it also locks registers */ - STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; -#endif - /* wait for the chip to reboot */ - while (1) - ; - } else { - if (flags & SYSTEM_RESET_WAIT_EXT) { - int i; - - /* Wait 10 seconds for external reset */ - for (i = 0; i < 1000; i++) { - watchdog_reload(); - udelay(10000); - } - } - - /* Request a soft system reset from the core. */ - CPU_NVIC_APINT = CPU_NVIC_APINT_KEY_WR | CPU_NVIC_APINT_SYSRST; - } - - /* Spin and wait for reboot; should never return */ - while (1) - ; -} - -int system_set_scratchpad(uint32_t value) -{ - /* Check if value fits in 16 bits */ - if (value & 0xffff0000) - return EC_ERROR_INVAL; - return bkpdata_write(BKPDATA_INDEX_SCRATCHPAD, (uint16_t)value); -} - -int system_get_scratchpad(uint32_t *value) -{ - *value = (uint32_t)bkpdata_read(BKPDATA_INDEX_SCRATCHPAD); - return EC_SUCCESS; -} - -const char *system_get_chip_vendor(void) -{ - return "stm"; -} - -const char *system_get_chip_name(void) -{ - return STRINGIFY(CHIP_VARIANT); -} - -const char *system_get_chip_revision(void) -{ - return ""; -} - -int system_get_chip_unique_id(uint8_t **id) -{ - *id = (uint8_t *)STM32_UNIQUE_ID_ADDRESS; - return STM32_UNIQUE_ID_LENGTH; -} - -int system_get_bbram(enum system_bbram_idx idx, uint8_t *value) -{ - int msb = 0; - int bkpdata_index = bkpdata_index_lookup(idx, &msb); - - if (bkpdata_index < 0) - return EC_ERROR_INVAL; - - *value = (bkpdata_read(bkpdata_index) >> (8 * msb)) & 0xff; - return EC_SUCCESS; -} - -int system_set_bbram(enum system_bbram_idx idx, uint8_t value) -{ - uint16_t read; - int msb = 0; - int bkpdata_index = bkpdata_index_lookup(idx, &msb); - - if (bkpdata_index < 0) - return EC_ERROR_INVAL; - - read = bkpdata_read(bkpdata_index); - if (msb) - read = (read & 0xff) | (value << 8); - else - read = (read & 0xff00) | value; - - bkpdata_write(bkpdata_index, read); - return EC_SUCCESS; -} - -int system_is_reboot_warm(void) -{ - /* - * Detecting if the system is warm is relevant for a - * few reasons. - * One such reason is that some firmwares transition from - * RO to RW images. When this happens, we may not need to - * restart certain clocks. On the flip side, we may need - * to restart the clocks if the RW requires a different - * set of clocks. Thus, the clock configurations need to - * be checked for a perfect match. - */ - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - return ((STM32_RCC_AHBENR & 0x7e0000) == 0x7e0000); -#elif defined(CHIP_FAMILY_STM32L) - return ((STM32_RCC_AHBENR & 0x3f) == 0x3f); -#elif defined(CHIP_FAMILY_STM32L4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); -#elif defined(CHIP_FAMILY_STM32L5) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); -#elif defined(CHIP_FAMILY_STM32F4) - return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) - == gpio_required_clocks()); -#elif defined(CHIP_FAMILY_STM32G4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == gpio_required_clocks()); -#elif defined(CHIP_FAMILY_STM32H7) - return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) - == STM32_RCC_AHB4ENR_GPIOMASK); -#endif -} diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c deleted file mode 100644 index 48d5335c53..0000000000 --- a/chip/stm32/trng.c +++ /dev/null @@ -1,145 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Hardware Random Number Generator */ - -#include "common.h" -#include "console.h" -#include "host_command.h" -#include "panic.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "trng.h" -#include "util.h" - -uint32_t rand(void) -{ - int tries = 300; - /* Wait for a valid random number */ - while (!(STM32_RNG_SR & STM32_RNG_SR_DRDY) && --tries) - ; - /* we cannot afford to feed the caller with an arbitrary number */ - if (!tries) - software_panic(PANIC_SW_BAD_RNG, task_get_current()); - /* Finally the 32-bit of entropy */ - return STM32_RNG_DR; -} - -test_mockable void rand_bytes(void *buffer, size_t len) -{ - while (len) { - uint32_t number = rand(); - size_t cnt = 4; - /* deal with the lack of alignment guarantee in the API */ - uintptr_t align = (uintptr_t)buffer & 3; - - if (len < 4 || align) { - cnt = MIN(4 - align, len); - memcpy(buffer, &number, cnt); - } else { - *(uint32_t *)buffer = number; - } - len -= cnt; - buffer += cnt; - } -} - -test_mockable void init_trng(void) -{ -#ifdef CHIP_FAMILY_STM32L4 - /* Enable the 48Mhz internal RC oscillator */ - STM32_RCC_CRRCR |= STM32_RCC_CRRCR_HSI48ON; - /* no timeout: we watchdog if the oscillator doesn't start */ - while (!(STM32_RCC_CRRCR & STM32_RCC_CRRCR_HSI48RDY)) - ; - - /* Clock the TRNG using the HSI48 */ - STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) - | (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT); -#elif defined(CHIP_FAMILY_STM32H7) - /* Enable the 48Mhz internal RC oscillator */ - STM32_RCC_CR |= STM32_RCC_CR_HSI48ON; - /* no timeout: we watchdog if the oscillator doesn't start */ - while (!(STM32_RCC_CR & STM32_RCC_CR_HSI48RDY)) - ; - - /* Clock the TRNG using the HSI48 */ - STM32_RCC_D2CCIP2R = - (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) - | STM32_RCC_D2CCIP2_RNGSEL_HSI48; -#elif defined(CHIP_FAMILY_STM32F4) - /* - * The RNG clock is the same as the SDIO/USB OTG clock, already set at - * 48 MHz during clock initialisation. Nothing to do. - */ -#else -#error "Please add support for CONFIG_RNG on this chip family." -#endif - /* Enable the RNG logic */ - STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_RNGEN; - /* Start the random number generation */ - STM32_RNG_CR |= STM32_RNG_CR_RNGEN; -} - -test_mockable void exit_trng(void) -{ - STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN; - STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN; -#ifdef CHIP_FAMILY_STM32L4 - STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON; -#elif defined(CHIP_FAMILY_STM32H7) - STM32_RCC_CR &= ~STM32_RCC_CR_HSI48ON; -#elif defined(CHIP_FAMILY_STM32F4) - /* Nothing to do */ -#endif -} - -#if defined(CONFIG_CMD_RAND) -/* - * We want to avoid accidentally exposing debug commands in RO since we can't - * update RO once in production. - */ -#if defined(SECTION_IS_RW) -static int command_rand(int argc, char **argv) -{ - uint8_t data[32]; - - init_trng(); - rand_bytes(data, sizeof(data)); - exit_trng(); - - ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); - - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(rand, command_rand, - NULL, "Output random bytes to console."); - -static enum ec_status host_command_rand(struct host_cmd_handler_args *args) -{ - const struct ec_params_rand_num *p = args->params; - struct ec_response_rand_num *r = args->response; - uint16_t num_rand_bytes = p->num_rand_bytes; - - if (system_is_locked()) - return EC_RES_ACCESS_DENIED; - - if (num_rand_bytes > args->response_max) - return EC_RES_OVERFLOW; - - init_trng(); - rand_bytes(r->rand, num_rand_bytes); - exit_trng(); - - args->response_size = num_rand_bytes; - - return EC_SUCCESS; -} - -DECLARE_HOST_COMMAND(EC_CMD_RAND_NUM, host_command_rand, - EC_VER_MASK(EC_VER_RAND_NUM)); -#endif /* SECTION_IS_RW */ -#endif /* CONFIG_CMD_RAND */ diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c deleted file mode 100644 index 0632fc6687..0000000000 --- a/chip/stm32/uart.c +++ /dev/null @@ -1,420 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* USART driver for Chrome EC */ - -#include "common.h" -#include "clock.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "uart.h" -#include "util.h" -#include "stm32-dma.h" - -/* Console USART index */ -#define UARTN CONFIG_UART_CONSOLE -#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) - -#ifdef CONFIG_UART_TX_DMA -#define UART_TX_INT_ENABLE STM32_USART_CR1_TCIE - -#ifndef CONFIG_UART_TX_DMA_CH -#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX -#endif - -/* DMA channel options; assumes UART1 */ -static const struct dma_option dma_tx_option = { - CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT -#ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH) -#endif -}; - -#else -#define UART_TX_INT_ENABLE STM32_USART_CR1_TXEIE -#endif - -#ifdef CONFIG_UART_RX_DMA - -#ifndef CONFIG_UART_RX_DMA_CH -#define CONFIG_UART_RX_DMA_CH STM32_DMAC_USART1_RX -#endif -/* DMA channel options; assumes UART1 */ -static const struct dma_option dma_rx_option = { - CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | -#ifdef CHIP_FAMILY_STM32F4 - STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) | -#endif - STM32_DMA_CCR_CIRC -}; - -static int dma_rx_len; /* Size of receive DMA circular buffer */ -#endif - -static int init_done; /* Initialization done? */ -static int should_stop; /* Last TX control action */ - -int uart_init_done(void) -{ - return init_done; -} - -void uart_tx_start(void) -{ - /* If interrupt is already enabled, nothing to do */ - if (STM32_USART_CR1(UARTN_BASE) & UART_TX_INT_ENABLE) - return; - - disable_sleep(SLEEP_MASK_UART); - should_stop = 0; - STM32_USART_CR1(UARTN_BASE) |= UART_TX_INT_ENABLE | - STM32_USART_CR1_TCIE; - task_trigger_irq(STM32_IRQ_USART(UARTN)); -} - -void uart_tx_stop(void) -{ - STM32_USART_CR1(UARTN_BASE) &= ~UART_TX_INT_ENABLE; - should_stop = 1; -#ifdef CONFIG_UART_TX_DMA - enable_sleep(SLEEP_MASK_UART); -#endif -} - -void uart_tx_flush(void) -{ - while (!(STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE)) - ; -} - -int uart_tx_ready(void) -{ - return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TXE; -} - -#ifdef CONFIG_UART_TX_DMA - -int uart_tx_dma_ready(void) -{ - return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC; -} - -void uart_tx_dma_start(const char *src, int len) -{ - /* Prepare DMA */ - dma_prepare_tx(&dma_tx_option, len, src); - - /* Force clear TC so we don't re-interrupt */ - STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC; - - /* Enable TCIE (chrome-os-partner:28837) */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TCIE; - - /* Start DMA */ - dma_go(dma_get_channel(dma_tx_option.channel)); -} - -#endif /* CONFIG_UART_TX_DMA */ - -int uart_rx_available(void) -{ - return STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_RXNE; -} - -#ifdef CONFIG_UART_RX_DMA - -void uart_rx_dma_start(char *dest, int len) -{ - /* Start receiving */ - dma_rx_len = len; - dma_start_rx(&dma_rx_option, len, dest); -} - -int uart_rx_dma_head(void) -{ - return dma_bytes_done(dma_get_channel(CONFIG_UART_RX_DMA_CH), - dma_rx_len); -} - -#endif - -void uart_write_char(char c) -{ - /* Wait for space */ - while (!uart_tx_ready()) - ; - - STM32_USART_TDR(UARTN_BASE) = c; -} - -int uart_read_char(void) -{ - return STM32_USART_RDR(UARTN_BASE); -} - -/* Interrupt handler for console USART */ -void uart_interrupt(void) -{ -#ifndef CONFIG_UART_TX_DMA - /* - * When transmission completes, enable sleep if we are done with Tx. - * After that, proceed if there is other interrupt to handle. - */ - if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) { - if (should_stop) { - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE; - enable_sleep(SLEEP_MASK_UART); - } -#if defined(CHIP_FAMILY_STM32F4) - STM32_USART_SR(UARTN_BASE) &= ~STM32_USART_SR_TC; -#else - STM32_USART_ICR(UARTN_BASE) |= STM32_USART_SR_TC; -#endif - if (!(STM32_USART_SR(UARTN_BASE) & ~STM32_USART_SR_TC)) - return; - } -#endif - -#ifdef CONFIG_UART_TX_DMA - /* Disable transmission complete interrupt if DMA done */ - if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TCIE; -#else - /* - * Disable the TX empty interrupt before filling the TX buffer since it - * needs an actual write to DR to be cleared. - */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_TXEIE; -#endif - -#ifndef CONFIG_UART_RX_DMA - /* - * Read input FIFO until empty. DMA-based receive does this from a - * hook in the UART buffering module. - */ - uart_process_input(); -#endif - - /* Fill output FIFO */ - uart_process_output(); - -#ifndef CONFIG_UART_TX_DMA - /* - * Re-enable TX empty interrupt only if it was not disabled by - * uart_process_output(). - */ - if (!should_stop) - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_TXEIE; -#endif -} -DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 2); - -/** - * Handle clock frequency changes - */ -static void uart_freq_change(void) -{ - int freq; - int div; - -#if (defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)) && \ - (UARTN <= 2) - /* - * UART is clocked from HSI (8MHz) to allow it to work when waking - * up from sleep - */ - freq = 8000000; -#elif defined(CHIP_FAMILY_STM32H7) - freq = 64000000; /* from 64 Mhz HSI */ -#elif defined(CHIP_FAMILY_STM32L4) - /* UART clocked from HSI 16 */ - freq = 16000000; -#else - /* UART clocked from the main clock */ - freq = clock_get_freq(); -#endif - -#if (UARTN == 9) /* LPUART */ - div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256; -#else - div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE); -#endif - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ - defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4) - if (div / 16 > 0) { - /* - * CPU clock is high enough to support x16 oversampling. - * BRR = (div mantissa)<<4 | (4-bit div fraction) - */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_OVER8; - STM32_USART_BRR(UARTN_BASE) = div; - } else { - /* - * CPU clock is low; use x8 oversampling. - * BRR = (div mantissa)<<4 | (3-bit div fraction) - */ - STM32_USART_BRR(UARTN_BASE) = ((div / 8) << 4) | (div & 7); - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_OVER8; - } -#else - /* STM32F only supports x16 oversampling */ - STM32_USART_BRR(UARTN_BASE) = div; -#endif - -} -DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT); - -void uart_init(void) -{ - /* Select clock source */ -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) -#if (UARTN == 1) - STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ -#elif (UARTN == 2) - STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */ -#endif /* UARTN */ -#elif defined(CHIP_FAMILY_STM32H7) /* Clocked from 64 Mhz HSI */ -#if ((UARTN == 1) || (UARTN == 6)) - STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART16SEL_HSI; -#else - STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART234578SEL_HSI; -#endif /* UARTN */ -#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4) - /* USART1 clock source from SYSCLK */ - STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK; -#ifdef CHIP_FAMILY_STM32L4 - /* For STM32L4, use HSI for UART, to wake up from low power mode */ - STM32_RCC_CCIPR |= - (STM32_RCC_CCIPR_UART_HSI16 << STM32_RCC_CCIPR_USART1SEL_SHIFT); -#else - STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK - << STM32_RCC_CCIPR_USART1SEL_SHIFT); -#endif - /* LPUART1 clock source from SYSCLK */ - STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK; - STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK - << STM32_RCC_CCIPR_LPUART1SEL_SHIFT); -#endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */ - - /* Enable USART clock */ -#if (UARTN == 1) - STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1; -#ifdef CHIP_FAMILY_STM32L4 -#if defined(CONFIG_UART_RX_DMA) || defined(CONFIG_UART_TX_DMA) - STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA1; - STM32_RCC_AHB1ENR |= STM32_RCC_HB1_DMA2; -#endif -#endif -#elif (UARTN == 6) - STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART6; -#elif (UARTN == 9) - STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_LPUART1EN; -#else - STM32_RCC_APB1ENR |= CONCAT2(STM32_RCC_PB1_USART, UARTN); -#endif - - /* - * For STM32F3, A delay of 1 APB clock cycles is needed before we - * can access any USART register. Fortunately, we have - * gpio_config_module() below and thus don't need to add the delay. - */ - - /* Configure GPIOs */ - gpio_config_module(MODULE_UART, 1); - -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \ -|| defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4) - /* - * Wake up on start bit detection. WUS can only be written when UE=0, - * so clear UE first. - */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UE; - - /* - * Also disable the RX overrun interrupt, since we don't care about it - * and we don't want to clear an extra flag in the interrupt - */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT | - STM32_USART_CR3_OVRDIS; -#endif - - /* - * UART enabled, 8 Data bits, oversampling x16, no parity, - * TX and RX enabled. - */ -#ifdef CHIP_FAMILY_STM32L4 - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_TE | STM32_USART_CR1_RE; -#else - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; -#endif - - /* 1 stop bit, no fancy stuff */ - STM32_USART_CR2(UARTN_BASE) = 0x0000; - -#ifdef CONFIG_UART_TX_DMA - /* Enable DMA transmitter */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT; -#ifdef CONFIG_UART_TX_DMA_PH - dma_select_channel(CONFIG_UART_TX_DMA_CH, CONFIG_UART_TX_DMA_PH); -#endif -#else - /* DMA disabled, special modes disabled, error interrupt disabled */ - STM32_USART_CR3(UARTN_BASE) &= ~STM32_USART_CR3_DMAR & - ~STM32_USART_CR3_DMAT & - ~STM32_USART_CR3_EIE; -#endif - -#ifdef CONFIG_UART_RX_DMA - /* Enable DMA receiver */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAR; -#else - /* Enable receive-not-empty interrupt */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_RXNEIE; -#endif - -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F4) - /* Use single-bit sampling */ - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_ONEBIT; -#endif - - /* Set initial baud rate */ - uart_freq_change(); - - /* Enable interrupts */ - task_enable_irq(STM32_IRQ_USART(UARTN)); - -#ifdef CHIP_FAMILY_STM32L4 - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UE; -#endif - - init_done = 1; -} - -#ifdef CONFIG_FORCE_CONSOLE_RESUME -void uart_enable_wakeup(int enable) -{ - if (enable) { - /* - * Allow UART wake up from STOP mode. Note, UART clock must - * be HSI(8MHz) for wakeup to work. - */ - STM32_USART_CR1(UARTN_BASE) |= STM32_USART_CR1_UESM; - STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUFIE; - } else { - /* Disable wake up from STOP mode. */ - STM32_USART_CR1(UARTN_BASE) &= ~STM32_USART_CR1_UESM; - } -} -#endif diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c deleted file mode 100644 index ef6ec92a89..0000000000 --- a/chip/stm32/ucpd-stm32gx.c +++ /dev/null @@ -1,1615 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* STM32GX UCPD module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "common.h" -#include "driver/tcpm/tcpm.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "ucpd-stm32gx.h" -#include "usb_pd.h" -#include "usb_pd_tcpm.h" -#include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - -#define USB_VID_STM32 0x0483 - -/* - * USB PD message buffer length. Absent extended messages, the longest PD - * message will be 7 objects (4 bytes each) plus a 2 byte header. TCPMv2 - * suports extended messages via chunking so the data buffer length is - * set assumign that extended messages are chunked. - */ -#define UCPD_BUF_LEN 30 - -#define UCPD_IMR_RX_INT_MASK (STM32_UCPD_IMR_RXNEIE| \ - STM32_UCPD_IMR_RXORDDETIE | \ - STM32_UCPD_IMR_RXHRSTDETIE | \ - STM32_UCPD_IMR_RXOVRIE | \ - STM32_UCPD_IMR_RXMSGENDIE) - -#define UCPD_IMR_TX_INT_MASK (STM32_UCPD_IMR_TXISIE | \ - STM32_UCPD_IMR_TXMSGDISCIE | \ - STM32_UCPD_IMR_TXMSGSENTIE | \ - STM32_UCPD_IMR_TXMSGABTIE | \ - STM32_UCPD_IMR_TXUNDIE) - -#define UCPD_ICR_TX_INT_MASK (STM32_UCPD_ICR_TXMSGDISCCF | \ - STM32_UCPD_ICR_TXMSGSENTCF | \ - STM32_UCPD_ICR_TXMSGABTCF | \ - STM32_UCPD_ICR_TXUNDCF) - -#define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3) -#define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3) - -struct msg_header_info { - enum pd_power_role pr; - enum pd_data_role dr; -}; -static struct msg_header_info msg_header; - -/* States for managing tx messages in ucpd task */ -enum ucpd_state { - STATE_IDLE, - STATE_ACTIVE_TCPM, - STATE_ACTIVE_CRC, - STATE_HARD_RESET, - STATE_WAIT_CRC_ACK, -}; - -/* Events for pd_interrupt_handler_task */ -#define UCPD_EVT_GOOD_CRC_REQ BIT(0) -#define UCPD_EVT_TCPM_MSG_REQ BIT(1) -#define UCPD_EVT_HR_REQ BIT(2) -#define UCPD_EVT_TX_MSG_FAIL BIT(3) -#define UCPD_EVT_TX_MSG_DISC BIT(4) -#define UCPD_EVT_TX_MSG_SUCCESS BIT(5) -#define UCPD_EVT_HR_DONE BIT(6) -#define UCPD_EVT_HR_FAIL BIT(7) -#define UCPD_EVT_RX_GOOD_CRC BIT(8) -#define UCPD_EVT_RX_MSG BIT(9) - -#define UCPD_T_RECEIVE_US (1 * MSEC) - -#define UCPD_N_RETRY_COUNT_REV20 3 -#define UCPD_N_RETRY_COUNT_REV30 2 - -/* - * Tx messages are iniated either by TCPM/PRL layer or from ucpd when a GoodCRC - * ack message needs to be sent. - */ -enum ucpd_tx_msg { - TX_MSG_NONE = -1, - TX_MSG_TCPM = 0, - TX_MSG_GOOD_CRC = 1, - TX_MSG_TOTAL = 2, -}; - -#define MSG_TCPM_MASK BIT(TX_MSG_TCPM) -#define MSG_GOOD_CRC_MASK BIT(TX_MSG_GOOD_CRC) - -union buffer { - uint16_t header; - uint8_t msg[UCPD_BUF_LEN]; -}; - -struct ucpd_tx_desc { - enum tcpci_msg_type type; - int msg_len; - int msg_index; - union buffer data; -}; - -/* Track VCONN on/off state */ -static int ucpd_vconn_enable; - -/* Tx message variables */ -struct ucpd_tx_desc ucpd_tx_buffers[TX_MSG_TOTAL]; -struct ucpd_tx_desc *ucpd_tx_active_buffer; -static int ucpd_tx_request; -static int ucpd_timeout_us; -static enum ucpd_state ucpd_tx_state; -static int msg_id_match; -static int tx_retry_count; -static int tx_retry_max; - -static int ucpd_txorderset[] = { - TX_ORDERSET_SOP, - TX_ORDERSET_SOP_PRIME, - TX_ORDERSET_SOP_PRIME_PRIME, - TX_ORDERSET_SOP_PRIME_DEBUG, - TX_ORDERSET_SOP_PRIME_PRIME_DEBUG, - TX_ORDERSET_HARD_RESET, - TX_ORDERSET_CABLE_RESET, -}; - -/* PD Rx variables */ -static int ucpd_rx_byte_count; -static uint8_t ucpd_rx_buffer[UCPD_BUF_LEN]; -static int ucpd_crc_id; -static bool ucpd_rx_sop_prime_enabled; -static int ucpd_rx_msg_active; -static bool ucpd_rx_bist_mode; - -#ifdef CONFIG_STM32G4_UCPD_DEBUG -/* Defines and macros for ucpd state logging */ -#define TX_STATE_LOG_LEN BIT(5) -#define TX_STATE_LOG_MASK (TX_STATE_LOG_LEN - 1) - -struct ucpd_tx_state { - uint32_t ts; - int tx_request; - int timeout_us; - enum ucpd_state enter_state; - enum ucpd_state exit_state; - uint32_t evt; -}; - -struct ucpd_tx_state ucpd_tx_statelog[TX_STATE_LOG_LEN]; -int ucpd_tx_state_log_idx; -int ucpd_tx_state_log_freeze; - -static char ucpd_names[][12] = { - "TX_IDLE", - "ACT_TCPM", - "ACT_CRC", - "HARD_RST", - "WAIT_CRC", -}; -/* Defines and macros used for ucpd pd message logging */ -#define MSG_LOG_LEN 64 -#define MSG_BUF_LEN 10 - -struct msg_info { - uint8_t dir; - uint8_t comp; - uint8_t crc; - uint16_t header; - uint32_t ts; - uint8_t buf[MSG_BUF_LEN]; -}; -static int msg_log_cnt; -static int msg_log_idx; -static struct msg_info msg_log[MSG_LOG_LEN]; - -#define UCPD_CC_STRING_LEN 5 - -static char ccx[4][UCPD_CC_STRING_LEN] = { - "Ra", - "Rp", - "Rd", - "Open", -}; -static char rp_string[][8] = { - "Rp_usb", - "Rp_1.5", - "Rp_3.0", - "Open", -}; -static int ucpd_sr_cc_event; -static int ucpd_cc_set_save; -static int ucpd_cc_change_log; - -static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line); - -static void ucpd_log_add_msg(uint16_t header, int dir) -{ - uint32_t ts = __hw_clock_source_read(); - int idx = msg_log_idx; - uint8_t *buf = dir ? ucpd_rx_buffer : ucpd_tx_active_buffer->data.msg; - - /* - * Add a msg entry in the history log. The log is currently designed to - * be from reset until MSG_LOG_LEN messages have been added. - * ts -> lower 32 bits of 1 uSec running clock - * dir -> 0 = tx message, 1 = rx message - * comp -> ucpd transmit success - * crc -> GoodCrc received following tx message - */ - if (msg_log_cnt++ < MSG_LOG_LEN) { - int msg_bytes = MIN((PD_HEADER_CNT(header) << 2) + 2, - MSG_BUF_LEN); - - msg_log[idx].header = header; - msg_log[idx].ts = ts; - msg_log[idx].dir = dir; - msg_log[idx].comp = 0; - msg_log[idx].crc = 0; - msg_log_idx++; - memcpy(msg_log[idx].buf, buf, msg_bytes); - } -} - -static void ucpd_log_mark_tx_comp(void) -{ - /* - * This msg logging utility function is used to mark when a message was - * successfully transmitted when transmit interrupt occurs and the tx - * message sent status was set. Because the transmit message is added - * before it's sent by ucpd, the index has to back up one to mark the - * correct log entry. - */ - if (msg_log_cnt < MSG_LOG_LEN) { - if (msg_log_idx > 0) - msg_log[msg_log_idx - 1].comp = 1; - } -} - -static void ucpd_log_mark_crc(void) -{ - /* - * This msg logging utility function is used to mark when a GoodCRC - * message is received following a tx message. This status is displayed - * in column s2. Because this indication follows both transmit message - * and GoodCRC rx, the index must be back up 2 rows to mark the correct - * tx message entry. - */ - if (msg_log_cnt < MSG_LOG_LEN) { - if (msg_log_idx >= 2) - msg_log[msg_log_idx - 2].crc = 1; - } -} - -static void ucpd_cc_status(int port) -{ - int rc = stm32gx_ucpd_get_role_control(port); - int cc1_pull, cc2_pull; - enum tcpc_cc_voltage_status v_cc1, v_cc2; - int rv; - char *rp_name; - - cc1_pull = rc & 0x3; - cc2_pull = (rc >> 2) & 0x3; - - /* - * This function is used to display CC settings, including pull type, - * and if Rp, what the Rp value is set to. In addition, the current - * values of CC voltage detector, polarity, and PD enable status are - * displayed. - */ - rv = stm32gx_ucpd_get_cc(port,&v_cc1, &v_cc2); - rp_name = rp_string[(rc >> 4) % 0x3]; - ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", - ccx[cc1_pull], ccx[cc2_pull], rp_name); - if (!rv) - ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2); -} - -void ucpd_cc_detect_notify_enable(int enable) -{ - /* - * This variable is used to control when a CC detach detector is - * active. - */ - ucpd_cc_change_log = enable; -} - -static void ucpd_log_invalidate_entry(void) -{ - /* - * This is a msg log utility function which is triggered when an - * unexpected detach event is detected. - */ - if (msg_log_idx < (MSG_LOG_LEN - 1)) { - int idx = msg_log_idx; - - msg_log[idx].header = 0xabcd; - msg_log[idx].ts = __hw_clock_source_read(); - msg_log[idx].dir = 0; - msg_log[idx].comp = 0; - msg_log[idx].crc = 0; - msg_log_cnt++; - msg_log_idx++; - } -} - -/* - * This function will mark in the msg log when a detach event occurs. It will - * only be active if ucpd_cc_change_log is set which can be controlled via the - * ucpd console command. - */ -static void ucpd_cc_change_notify(void) -{ - if (ucpd_cc_change_log) { - uint32_t sr = ucpd_sr_cc_event; - - ucpd_log_invalidate_entry(); - - ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n", - (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3, - (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3, - (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) - & 0x3); - /* Display CC status on EC console */ - ucpd_cc_status(0); - } -} -DECLARE_DEFERRED(ucpd_cc_change_notify); -#endif /* CONFIG_STM32G4_UCPD_DEBUG */ - -static int ucpd_msg_is_good_crc(uint16_t header) -{ - /* - * Good CRC is a control message (no data objects) with GOOD_CRC message - * type in the header. - */ - return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) && - (PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? 1 : 0; -} - -static void ucpd_hard_reset_rx_log(void) -{ - CPRINTS("ucpd: hard reset recieved"); -} -DECLARE_DEFERRED(ucpd_hard_reset_rx_log); - -static void ucpd_port_enable(int port, int enable) -{ - if (enable) - STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN; - else - STM32_UCPD_CFGR1(port) &= ~STM32_UCPD_CFGR1_UCPDEN; -} - -static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line) -{ - int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >> - STM32_UCPD_CR_CCENABLE_SHIFT; - - return ((cc_enable >> cc_line) & 0x1); -} - -static void ucpd_tx_data_byte(int port) -{ - int index = ucpd_tx_active_buffer->msg_index++; - - STM32_UCPD_TXDR(port) = ucpd_tx_active_buffer->data.msg[index]; -} - -static void ucpd_rx_data_byte(int port) -{ - if (ucpd_rx_byte_count < UCPD_BUF_LEN) - ucpd_rx_buffer[ucpd_rx_byte_count++] = STM32_UCPD_RXDR(port); -} - -static void ucpd_tx_interrupts_enable(int port, int enable) -{ - if (enable) { - STM32_UCPD_ICR(port) = UCPD_ICR_TX_INT_MASK; - STM32_UCPD_IMR(port) |= UCPD_IMR_TX_INT_MASK; - } else { - STM32_UCPD_IMR(port) &= ~UCPD_IMR_TX_INT_MASK; - } -} - -static void ucpd_rx_enque_error(void) -{ - CPRINTS("ucpd: TCPM Enque Error!!"); -} -DECLARE_DEFERRED(ucpd_rx_enque_error); - -static void stm32gx_ucpd_state_init(int port) -{ - /* Init variables used to manage tx process */ - ucpd_tx_request = 0; - tx_retry_count = 0; - ucpd_tx_state = STATE_IDLE; - ucpd_timeout_us = -1; - - /* Init variables used to manage rx */ - ucpd_rx_sop_prime_enabled = 0; - ucpd_rx_msg_active = 0; - ucpd_rx_bist_mode = 0; - - /* Vconn tracking variable */ - ucpd_vconn_enable = 0; -} - -int stm32gx_ucpd_init(int port) -{ - uint32_t cfgr1_reg; - uint32_t moder_reg; - - /* Disable UCPD interrupts */ - task_disable_irq(STM32_IRQ_UCPD1); - - /* - * After exiting reset, stm32gx will have dead battery mode enabled by - * default which connects Rd to CC1/CC2. This should be disabled when EC - * is powered up. - */ - STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS; - - /* Ensure that clock to UCPD is enabled */ - STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN; - - /* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */ - moder_reg = STM32_GPIO_MODER(GPIO_B); - moder_reg |= 0x3300; - STM32_GPIO_MODER(GPIO_B) = moder_reg; - /* - * CFGR1 must be written when UCPD peripheral is disabled. Note that - * disabling ucpd causes the peripheral to quit any ongoing activity and - * sets all ucpd registers back their default values. - */ - ucpd_port_enable(port, 0); - - cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) | - STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | - STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | - STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); - STM32_UCPD_CFGR1(port) = cfgr1_reg; - - /* - * Set RXORDSETEN field to control which types of ordered sets the PD - * receiver must receive. - * SOP, SOP', Hard Reset Det, Cable Reset Det enabled - */ - STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_RXORDSETEN_VAL(0x1B); - - /* Enable ucpd */ - ucpd_port_enable(port, 1); - - /* Configure CC change interrupts */ - STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE | - STM32_UCPD_IMR_TYPECEVT2IE; - STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF | - STM32_UCPD_ICR_TYPECEVT2CF; - - /* SOP'/SOP'' must be enabled via TCPCI call */ - ucpd_rx_sop_prime_enabled = false; - - stm32gx_ucpd_state_init(port); - - /* Enable UCPD interrupts */ - task_enable_irq(STM32_IRQ_UCPD1); - - return EC_SUCCESS; -} - -int stm32gx_ucpd_release(int port) -{ - ucpd_port_enable(port, 0); - - return EC_SUCCESS; -} - -int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) -{ - int vstate_cc1; - int vstate_cc2; - int anamode; - uint32_t sr; - - /* - * cc_voltage_status is determined from vstate_cc bit field in the - * status register. The meaning of the value vstate_cc depends on - * current value of ANAMODE (src/snk). - * - * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1, - * but needs to be modified slightly for case ANAMODE = 0. - * - * If presenting Rp (source), then need to to a circular shift of - * vstate_ccx value: - * vstate_cc | cc_state - * ------------------ - * 0 -> 1 - * 1 -> 2 - * 2 -> 0 - */ - - /* Get vstate_ccx values and power role */ - sr = STM32_UCPD_SR(port); - /* Get Rp or Rd active */ - anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); - vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >> - STM32_UCPD_SR_VSTATE_CC1_SHIFT; - vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >> - STM32_UCPD_SR_VSTATE_CC2_SHIFT; - - /* Do circular shift if port == source */ - if (anamode) { - if (vstate_cc1 != STM32_UCPD_SR_VSTATE_RA) - vstate_cc1 += 4; - if (vstate_cc2 != STM32_UCPD_SR_VSTATE_RA) - vstate_cc2 += 4; - } else { - if (vstate_cc1 != STM32_UCPD_SR_VSTATE_OPEN) - vstate_cc1 = (vstate_cc1 + 1) % 3; - if (vstate_cc2 != STM32_UCPD_SR_VSTATE_OPEN) - vstate_cc2 = (vstate_cc2 + 1) % 3; - } - - *cc1 = vstate_cc1; - *cc2 = vstate_cc2; - - return EC_SUCCESS; -} - -int stm32gx_ucpd_get_role_control(int port) -{ - int role_control; - int cc1; - int cc2; - int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); - int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) - >> STM32_UCPD_CR_ANASUBMODE_SHIFT; - - /* - * Role control register is defined as: - * R_cc1 -> b 1:0 - * R_cc2 -> b 3:2 - * Rp -> b 5:4 - * - * In TCPCI, CCx is defined as: - * 00b -> Ra - * 01b -> Rp - * 10b -> Rd - * 11b -> Open (don't care) - * - * For ucpd, this information is encoded in ANAMODE and ANASUBMODE - * fields as follows: - * ANAMODE CCx - * 0 -> Rp -> 1 - * 1 -> Rd -> 2 - * - * ANASUBMODE: - * 00b -> TYPEC_RP_RESERVED (open) - * 01b -> TYPEC_RP_USB - * 10b -> TYPEC_RP_1A5 - * 11b -> TYPEC_RP_3A0 - * - * CCx = ANAMODE + 1, if CCx is enabled - * Rp = (ANASUBMODE - 1) & 0x3 - */ - cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 : - TYPEC_CC_OPEN; - cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 : - TYPEC_CC_OPEN; - role_control = cc1 | (cc2 << 2); - /* Circular shift anasubmode to convert to Rp range */ - role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4); - - return role_control; -} - -static uint32_t ucpd_get_cc_enable_mask(int port) -{ - uint32_t mask = STM32_UCPD_CR_CCENABLE_MASK; - - if (ucpd_vconn_enable) { - uint32_t cr = STM32_UCPD_CR(port); - int pol = !!(cr & STM32_UCPD_CR_PHYCCSEL); - - mask &= ~(1 << (STM32_UCPD_CR_CCENABLE_SHIFT + !pol)); - } - - return mask; -} - -int stm32gx_ucpd_vconn_disc_rp(int port, int enable) -{ - int cr; - - /* Update VCONN on/off status. Do this before getting cc enable mask */ - ucpd_vconn_enable = enable; - - cr = STM32_UCPD_CR(port); - cr &= ~STM32_UCPD_CR_CCENABLE_MASK; - cr |= ucpd_get_cc_enable_mask(port); - - /* Apply cc pull resistor change */ - STM32_UCPD_CR(port) = cr; - - return EC_SUCCESS; -} - -int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp) -{ - uint32_t cr = STM32_UCPD_CR(port); - - /* - * Always set ANASUBMODE to match desired Rp. TCPM layer has a valid - * range of 0, 1, or 2. This range maps to 1, 2, or 3 in ucpd for - * ANASUBMODE. - */ - cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK; - cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp)); - - /* Disconnect both pull from both CC lines for R_open case */ - cr &= ~STM32_UCPD_CR_CCENABLE_MASK; - /* Set ANAMODE if cc_pull is Rd */ - if (cc_pull == TYPEC_CC_RD) { - cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK; - /* Clear ANAMODE if cc_pull is Rp */ - } else if (cc_pull == TYPEC_CC_RP) { - cr &= ~(STM32_UCPD_CR_ANAMODE); - cr |= ucpd_get_cc_enable_mask(port); - } - -#ifdef CONFIG_STM32G4_UCPD_DEBUG - if (ucpd_cc_change_log) { - CPRINTS("ucpd: set_cc: pull = %d, rp = %d", cc_pull, rp); - } -#endif - /* Update pull values */ - STM32_UCPD_CR(port) = cr; - - return EC_SUCCESS; -} - -int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) { - /* - * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This - * function is called when polarity is updated at TCPM layer. STM32Gx - * only supports POLARITY_CC1 or POLARITY_CC2 and this is stored in the - * PHYCCSEL bit in the CR register. - */ - if (polarity > POLARITY_CC2) - return EC_ERROR_UNIMPLEMENTED; - - if (polarity == POLARITY_CC1) - STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYCCSEL; - else if (polarity == POLARITY_CC2) - STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYCCSEL; - -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_cc_set_save = STM32_UCPD_CR(port); -#endif - - return EC_SUCCESS; -} - -int stm32gx_ucpd_set_rx_enable(int port, int enable) -{ - /* - * USB PD receiver enable is controlled by the bit PHYRXEN in - * UCPD_CR. Enable Rx interrupts when RX PD decoder is active. - */ - if (enable) { - STM32_UCPD_ICR(port) = UCPD_IMR_RX_INT_MASK; - STM32_UCPD_IMR(port) |= UCPD_IMR_RX_INT_MASK; - STM32_UCPD_CR(port) |= STM32_UCPD_CR_PHYRXEN; - } else { - STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_PHYRXEN; - STM32_UCPD_IMR(port) &= ~UCPD_IMR_RX_INT_MASK; - } - - return EC_SUCCESS; -} - -int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role) -{ - msg_header.pr = power_role; - msg_header.dr = data_role; - - return EC_SUCCESS; -} - -int stm32gx_ucpd_sop_prime_enable(int port, bool enable) -{ - /* Update static varialbe used to filter SOP//SOP'' messages */ - ucpd_rx_sop_prime_enabled = enable; - - return EC_SUCCESS; -} - -int stm32gx_ucpd_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) -{ - chip_info->vendor_id = USB_VID_STM32; - chip_info->product_id = 0; - chip_info->device_id = STM32_DBGMCU_IDCODE & 0xfff; - chip_info->fw_version_number = 0xEC; - - return EC_SUCCESS; -} - -static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) -{ - enum tcpci_msg_type type; - - /* Select the correct tx desciptor */ - ucpd_tx_active_buffer = &ucpd_tx_buffers[msg_type]; - type = ucpd_tx_active_buffer->type; - - if (type == TCPCI_MSG_TX_HARD_RESET) { - /* - * From RM0440 45.4.4: - * In order to facilitate generation of a Hard Reset, a special - * code of TXMODE field is used. No other fields need to be - * written. On writing the correct code, the hardware forces - * Hard Reset Tx under the correct (optimal) timings with - * respect to an on-going Tx message, which (if still in - * progress) is cleanly terminated by truncating the current - * sequence and directly appending an EOP K-code sequence. No - * specific interrupt is generated relating to this truncation - * event. - * - * Because Hard Reset can interrupt ongoing Tx operations, it is - * started differently than all other tx messages. Only need to - * enable hard reset interrupts, and then set a bit in the CR - * register to initiate. - */ - /* Enable interrupt for Hard Reset sent/discarded */ - STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF | - STM32_UCPD_ICR_HRSTSENTCF; - STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE | - STM32_UCPD_IMR_HRSTSENTIE; - /* Initiate Hard Reset */ - STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST; - } else if (type != TCPCI_MSG_INVALID) { - int msg_len = 0; - int mode; - - /* - * These types are normal transmission, TXMODE = 0. To transmit - * regular message, control or data, requires the following: - * 1. Set TXMODE: - * Normal -> 0 - * Cable Reset -> 1 - * Bist -> 2 - * 2. Set TX_ORDSETR based on message type - * 3. Set TX_PAYSZR which must account for 2 bytes of header - * 4. Configure DMA (optional if DMA is desired) - * 5. Enable transmit interrupts - * 6. Start TX by setting TXSEND in CR - * - */ - - /* - * Set tx length parameter (in bytes). Note the count field in - * the header is number of 32 bit objects. Also, the length - * field must account for the 2 header bytes. - */ - if (type == TCPCI_MSG_TX_BIST_MODE_2) { - mode = STM32_UCPD_CR_TXMODE_BIST; - } else if (type == TCPCI_MSG_CABLE_RESET) { - mode = STM32_UCPD_CR_TXMODE_CBL_RST; - } else { - mode = STM32_UCPD_CR_TXMODE_DEF; - msg_len = ucpd_tx_active_buffer->msg_len; - } - - STM32_UCPD_TX_PAYSZR(port) = msg_len; - - /* Set tx mode */ - STM32_UCPD_CR(port) &= ~STM32_UCPD_CR_TXMODE_MASK; - STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXMODE_VAL(mode); - - /* Index into ordset enum for start of packet */ - if (type <= TCPCI_MSG_CABLE_RESET) - STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type]; - else - STM32_UCPD_TX_ORDSETR(port) = - ucpd_txorderset[TX_ORDERSET_SOP]; - - /* Reset msg byte index */ - ucpd_tx_active_buffer-> msg_index = 0; - - /* Enable interrupts */ - ucpd_tx_interrupts_enable(port, 1); - - /* Trigger ucpd peripheral to start pd message transmit */ - STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXSEND; - -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_log_add_msg(ucpd_tx_active_buffer->data.header, 0); -#endif - } - - return EC_SUCCESS; -} - -static void ucpd_set_tx_state(enum ucpd_state state) -{ - ucpd_tx_state = state; -} - -#ifdef CONFIG_STM32G4_UCPD_DEBUG -static void ucpd_task_log(int timeout, enum ucpd_state enter, - enum ucpd_state exit, int req, uint32_t evt) -{ - static int same_count = 0; - int idx = ucpd_tx_state_log_idx; - - if (ucpd_tx_state_log_freeze) - return; - - ucpd_tx_statelog[idx].ts = get_time().le.lo; - ucpd_tx_statelog[idx].tx_request = req; - ucpd_tx_statelog[idx].timeout_us = timeout; - ucpd_tx_statelog[idx].enter_state = enter; - ucpd_tx_statelog[idx].exit_state = exit; - ucpd_tx_statelog[idx].evt = evt; - - ucpd_tx_state_log_idx = (idx + 1) & TX_STATE_LOG_MASK; - - if (enter == exit) { - same_count++; - } else { - same_count = 0; - } - - /* - * Should not have same enter/exit states. If this happens, then freeze - * state log to help in debugging. - */ - if (same_count > 5) - ucpd_tx_state_log_freeze = 1; -} - -static void ucpd_task_log_dump(void) -{ - int n; - int idx; - - ucpd_tx_state_log_freeze = 1; - - /* current index will be oldest entry in the log */ - idx = ucpd_tx_state_log_idx; - - ccprintf("\n\t UCDP Task Log\n"); - for (n = 0; n < TX_STATE_LOG_LEN; n++) { - ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", - n, - ucpd_names[ucpd_tx_statelog[idx].enter_state], - ucpd_names[ucpd_tx_statelog[idx].exit_state], - ucpd_tx_statelog[idx].tx_request, - ucpd_tx_statelog[idx].evt, - ucpd_tx_statelog[idx].ts, - ucpd_tx_statelog[idx].timeout_us); - - idx = (idx + 1) & TX_STATE_LOG_MASK; - msleep(5); - } - - ucpd_tx_state_log_freeze = 0; -} -#endif - -static void ucpd_manage_tx(int port, int evt) -{ - enum ucpd_tx_msg msg_src = TX_MSG_NONE; - uint16_t hdr; -#ifdef CONFIG_STM32G4_UCPD_DEBUG - enum ucpd_state enter = ucpd_tx_state; - int req = ucpd_tx_request; -#endif - - if (evt & UCPD_EVT_HR_REQ) { - /* - * Hard reset control messages are treated as a priority. The - * control message will already be set up as it comes from the - * PRL layer like any other PD ctrl/data message. So just need - * to indicate the correct message source and set the state to - * hard reset here. - */ - ucpd_set_tx_state(STATE_HARD_RESET); - msg_src = TX_MSG_TCPM; - ucpd_tx_request &= ~(1 << msg_src); - } - - switch (ucpd_tx_state) { - case STATE_IDLE: - if (ucpd_tx_request & MSG_GOOD_CRC_MASK) { - ucpd_set_tx_state(STATE_ACTIVE_CRC); - msg_src = TX_MSG_GOOD_CRC; - } else if (ucpd_tx_request & MSG_TCPM_MASK) { - if (evt & UCPD_EVT_RX_MSG) { - /* - * USB-PD Specification rev 3.0, section 6.10 - * On receiving a received message, the protocol - * layer shall discard any pending message. - * - * Since the pending message from the PRL has - * not been sent yet, it needs to be discarded - * based on the received message event. - */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); - ucpd_tx_request &= ~MSG_TCPM_MASK; - } else if (!ucpd_rx_msg_active) { - ucpd_set_tx_state(STATE_ACTIVE_TCPM); - msg_src = TX_MSG_TCPM; - /* Save msgID required for GoodCRC check */ - hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header; - msg_id_match = PD_HEADER_ID(hdr); - tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ? - UCPD_N_RETRY_COUNT_REV30 : - UCPD_N_RETRY_COUNT_REV20; - } - } - - /* If state is not idle, then start tx message */ - if (ucpd_tx_state != STATE_IDLE) { - ucpd_tx_request &= ~(1 << msg_src); - tx_retry_count = 0; - } - break; - - case STATE_ACTIVE_TCPM: - /* - * Check if tx msg has finsihed. For TCPM messages - * transmit is not complete until a GoodCRC message - * matching the msgID just sent is received. But, a tx - * message can fail due to collision or underrun, - * etc. If that failure occurs, dont' wait for GoodCrc - * and just go to failure path. - */ - if (evt & UCPD_EVT_TX_MSG_SUCCESS) { - ucpd_set_tx_state(STATE_WAIT_CRC_ACK); - ucpd_timeout_us = UCPD_T_RECEIVE_US; - } else if (evt & UCPD_EVT_TX_MSG_DISC || - evt & UCPD_EVT_TX_MSG_FAIL) { - if (tx_retry_count < tx_retry_max) { - if (evt & UCPD_EVT_RX_MSG) { - /* - * A message was received so there is no - * need to retry this tx message which - * had failed to send previously. - * Likely, due to the wire - * being active from the message that - * was just received. - */ - ucpd_set_tx_state(STATE_IDLE); - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); - ucpd_set_tx_state(STATE_IDLE); - } else { - /* - * Tx attempt failed. Remain in this - * state, but trigger new tx attempt. - */ - msg_src = TX_MSG_TCPM; - tx_retry_count++; - } - } else { - enum tcpc_transmit_complete status; - - status = (evt & UCPD_EVT_TX_MSG_FAIL) ? - TCPC_TX_COMPLETE_FAILED : - TCPC_TX_COMPLETE_DISCARDED; - ucpd_set_tx_state(STATE_IDLE); - pd_transmit_complete(port, status); - } - } - break; - - case STATE_ACTIVE_CRC: - if (evt & (UCPD_EVT_TX_MSG_SUCCESS | UCPD_EVT_TX_MSG_FAIL | - UCPD_EVT_TX_MSG_DISC)) { - ucpd_set_tx_state(STATE_IDLE); - if (evt & UCPD_EVT_TX_MSG_FAIL) - CPRINTS("ucpd: Failed to send GoodCRC!"); - else if (evt & UCPD_EVT_TX_MSG_DISC) - CPRINTS("ucpd: GoodCRC message discarded!"); - } - break; - - case STATE_WAIT_CRC_ACK: - if (evt & UCPD_EVT_RX_GOOD_CRC && - ucpd_crc_id == msg_id_match) { - /* GoodCRC with matching ID was received */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_SUCCESS); - ucpd_set_tx_state(STATE_IDLE); -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_log_mark_crc(); -#endif - } else if ((evt & UCPD_EVT_RX_GOOD_CRC) || - (evt & TASK_EVENT_TIMER)) { - /* GoodCRC w/out match or timeout waiting */ - if (tx_retry_count < tx_retry_max) { - ucpd_set_tx_state(STATE_ACTIVE_TCPM); - msg_src = TX_MSG_TCPM; - tx_retry_count++; - } else { - ucpd_set_tx_state(STATE_IDLE); - pd_transmit_complete(port, - TCPC_TX_COMPLETE_FAILED); - } - } else if (evt & UCPD_EVT_RX_MSG) { - /* - * In the case of a collsion, it's possible the port - * partner may not send a GoodCRC and instead send the - * message that was colliding. If a message is received - * in this state, then treat it as a discard from an - * incoming message. - */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); - ucpd_set_tx_state(STATE_IDLE); - } - break; - - case STATE_HARD_RESET: - if (evt & UCPD_EVT_HR_DONE) { - /* HR complete, reset tx state values */ - ucpd_set_tx_state(STATE_IDLE); - ucpd_tx_request = 0; - tx_retry_count = 0; - } else if (evt & UCPD_EVT_HR_FAIL) { - ucpd_set_tx_state(STATE_IDLE); - ucpd_tx_request = 0; - tx_retry_count = 0; - } - break; - } - - /* If msg_src is valid, then start transmit */ - if (msg_src > TX_MSG_NONE) { - stm32gx_ucpd_start_transmit(port, msg_src); - } - -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_task_log(ucpd_timeout_us, enter, ucpd_tx_state, req, evt); -#endif -} - -/* - * Main task entry point for UCPD task - * - * @param p The PD port number for which to handle interrupts (pointer is - * reinterpreted as an integer directly). - */ -void ucpd_task(void *p) -{ - const int port = (int) ((intptr_t) p); - - /* Init variables used to manage tx process */ - stm32gx_ucpd_state_init(port); - - while (1) { - /* - * Note that ucpd_timeout_us is file scope and may be modified - * in the tx state machine when entering the STATE_WAIT_CRC_ACK - * state. Otherwise, the expectation is that the task is woken - * only upon non-timer events. - */ - int evt = task_wait_event(ucpd_timeout_us); - - /* - * USB-PD messages are intiated in TCPM stack (PRL - * layer). However, GoodCRC messages are initiated within the - * UCPD driver based on USB-PD rx messages. These 2 types of - * transmit paths are managed via task events. - * - * UCPD generated GoodCRC messages, are the priority path as - * they must be sent immediately following a successful USB-PD - * rx message. As long as a transmit operation is not underway, - * then a transmit message will be started upon request. The ISR - * routine sets the event to indicate that the transmit - * operation is complete. - * - * Hard reset requests are sent as a TCPM message, but in terms - * of the ucpd transmitter, they are treated as a 3rd tx msg - * source since they can interrupt an ongoing tx msg, and there - * is no requirement to wait for a GoodCRC reply message. - */ - - /* Assume there is no timer for next task wake */ - ucpd_timeout_us = -1; - - if (evt & UCPD_EVT_GOOD_CRC_REQ) - ucpd_tx_request |= MSG_GOOD_CRC_MASK; - - if (evt & UCPD_EVT_TCPM_MSG_REQ) - ucpd_tx_request |= MSG_TCPM_MASK; - - /* - * Manage PD tx messages. The state machine may need to be - * called more than once when the task wakes. For instance, if - * the task is woken at the completion of sending a GoodCRC, - * there may be a TCPM message request pending and just changing - * the state back to idle would not trigger start of transmit. - */ - do { - ucpd_manage_tx(port, evt); - /* Look at task events only once. */ - evt = 0; - } while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE - && !ucpd_rx_msg_active); - } -} - -static void ucpd_send_good_crc(int port, uint16_t rx_header) -{ - int msg_id; - int rev_id; - uint16_t tx_header; - enum tcpci_msg_type tx_type; - enum pd_power_role pr = 0; - enum pd_data_role dr = 0; - - /* - * A GoodCRC message shall be sent by receiver to ack that the previous - * message was correctly received. The GoodCRC message shall return the - * rx message's msg_id field. The one exception is for GoodCRC messages, - * which do not generate a GoodCRC response - */ - if (ucpd_msg_is_good_crc(rx_header)) { - return; - } - - /* - * Get the rx ordered set code just detected. SOP -> SOP''_Debug are in - * the same order as enum tcpci_msg_type and so can be used - * directly. - */ - tx_type = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK; - - /* - * PD Header(SOP): - * Extended b15 -> set to 0 for control messages - * Count b14:12 -> number of 32 bit data objects = 0 for ctrl msg - * MsgID b11:9 -> running byte counter (extracted from rx msg) - * Power Role b8 -> stored in static, from set_msg_header() - * Spec Rev b7:b6 -> PD spec revision (extracted from rx msg) - * Data Role b5 -> stored in static, from set_msg_header - * Msg Type b4:b0 -> data or ctrl type = PD_CTRL_GOOD_CRC - */ - /* construct header message */ - msg_id = PD_HEADER_ID(rx_header); - rev_id = PD_HEADER_REV(rx_header); - if (tx_type == TCPCI_MSG_SOP) { - pr = msg_header.pr; - dr = msg_header.dr; - } - tx_header = PD_HEADER(PD_CTRL_GOOD_CRC, pr, dr, msg_id, 0, rev_id, 0); - - /* Good CRC is header with no other objects */ - ucpd_tx_buffers[TX_MSG_GOOD_CRC].msg_len = 2; - ucpd_tx_buffers[TX_MSG_GOOD_CRC].data.header = tx_header; - ucpd_tx_buffers[TX_MSG_GOOD_CRC].type = tx_type; - - /* Notify ucpd task that a GoodCRC message tx request is pending */ - task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ); -} - -int stm32gx_ucpd_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, - const uint32_t *data) -{ - /* Length in bytes = (4 * object len) + 2 header byes */ - int len = (PD_HEADER_CNT(header) << 2) + 2; - - if (len > UCPD_BUF_LEN) - return EC_ERROR_OVERFLOW; - - /* Store tx msg info in TCPM msg descriptor */ - ucpd_tx_buffers[TX_MSG_TCPM].msg_len = len; - ucpd_tx_buffers[TX_MSG_TCPM].type = type; - ucpd_tx_buffers[TX_MSG_TCPM].data.header = header; - /* Copy msg objects to ucpd data buffer, after 2 header bytes */ - memcpy(ucpd_tx_buffers[TX_MSG_TCPM].data.msg + 2, (uint8_t *)data, - len - 2); - - /* - * Check for hard reset message here. A different event is used for hard - * resets as they are able to interrupt ongoing transmit, and should - * have priority over any pending message. - */ - if (type == TCPCI_MSG_TX_HARD_RESET) - task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_REQ); - else - task_set_event(TASK_ID_UCPD, UCPD_EVT_TCPM_MSG_REQ); - - return EC_SUCCESS; -} - -int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head) -{ - uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer; - int rxpaysz; -#ifdef CONFIG_USB_PD_DECODE_SOP - int sop; -#endif - - /* First 2 bytes of data buffer are the header */ - *head = *rx_header; - -#ifdef CONFIG_USB_PD_DECODE_SOP -/* - * The message header is a 16-bit value that's stored in a 32-bit data type. - * SOP* is encoded in bits 31 to 28 of the 32-bit data type. - * NOTE: The 4 byte header is not part of the PD spec. - */ - /* Get SOP value */ - sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK; - /* Put SOP in bits 31:28 of 32 bit header */ - *head |= PD_HEADER_SOP(sop); -#endif - rxpaysz = STM32_UCPD_RX_PAYSZR(port) & STM32_UCPD_RX_PAYSZR_MASK; - /* This size includes 2 bytes for message header */ - rxpaysz -= 2; - /* Copy payload (src/dst are both 32 bit aligned) */ - memcpy(payload, ucpd_rx_buffer + 2, rxpaysz); - - return EC_SUCCESS; -} - -enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port, - const bool enable) -{ - ucpd_rx_bist_mode = enable; - CPRINTS("ucpd: Bist test mode = %d", enable); - - return EC_SUCCESS; -} - -void stm32gx_ucpd1_irq(void) -{ - /* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */ - int port = 0; - uint32_t sr = STM32_UCPD_SR(port); - uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | STM32_UCPD_SR_TXMSGABT - | STM32_UCPD_SR_TXMSGDISC | STM32_UCPD_SR_HRSTSENT | - STM32_UCPD_SR_HRSTDISC; - - /* Check for CC events, set event to wake PD task */ - if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) { - task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_CC); -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_sr_cc_event = sr; - hook_call_deferred(&ucpd_cc_change_notify_data, 0); -#endif - } - - /* - * Check for Tx events. tx_mask includes all status bits related to the - * end of a USB-PD tx message. If any of these bits are set, the - * transmit attempt is completed. Set an event to notify ucpd tx state - * machine that transmit operation is complete. - */ - if (sr & tx_done_mask) { - /* Check for tx message complete */ - if (sr & STM32_UCPD_SR_TXMSGSENT) { - task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_SUCCESS); -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_log_mark_tx_comp(); -#endif - } else if (sr & (STM32_UCPD_SR_TXMSGABT | - STM32_UCPD_SR_TXUND)) { - task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL); - } else if (sr & STM32_UCPD_SR_TXMSGDISC) { - task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC); -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_log_mark_tx_comp(); -#endif - } else if (sr & STM32_UCPD_SR_HRSTSENT) { - task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_DONE); - } else if (sr & STM32_UCPD_SR_HRSTDISC) { - task_set_event(TASK_ID_UCPD, UCPD_EVT_HR_FAIL); - } - /* Disable Tx interrupts */ - ucpd_tx_interrupts_enable(port, 0); - } - - /* Check for data register empty */ - if (sr & STM32_UCPD_SR_TXIS) - ucpd_tx_data_byte(port); - - /* Check for Rx Events */ - /* Check first for start of new message */ - if (sr & STM32_UCPD_SR_RXORDDET) { - ucpd_rx_byte_count = 0; - ucpd_rx_msg_active = 1; - } - /* Check for byte received */ - if (sr & STM32_UCPD_SR_RXNE) - ucpd_rx_data_byte(port); - - /* Check for end of message */ - if (sr & STM32_UCPD_SR_RXMSGEND) { - ucpd_rx_msg_active = 0; - /* Check for errors */ - if (!(sr & STM32_UCPD_SR_RXERR)) { - uint16_t *rx_header = (uint16_t *)ucpd_rx_buffer; - enum tcpci_msg_type type; - int good_crc = 0; - - type = STM32_UCPD_RX_ORDSETR(port) & - STM32_UCPD_RXORDSETR_MASK; - - good_crc = ucpd_msg_is_good_crc(*rx_header); - -#ifdef CONFIG_STM32G4_UCPD_DEBUG - ucpd_log_add_msg(*rx_header, 1); -#endif - /* - * Don't pass GoodCRC control messages to the TCPM - * layer. In addition, need to filter for SOP'/SOP'' - * packets if those are not enabled. SOP'/SOP'' - * reception is controlled by a static variable. The - * hardware orderset detection pattern can't be changed - * without disabling the ucpd peripheral. - */ - if (!good_crc && (ucpd_rx_sop_prime_enabled || - type == TCPCI_MSG_SOP)) { - - /* - * If BIST test mode is active, then still need - * to send GoodCRC reply, but there is no need - * to send the message up to the tcpm layer. - */ - if(!ucpd_rx_bist_mode) { - if (tcpm_enqueue_message(port)) - hook_call_deferred(&ucpd_rx_enque_error_data, - 0); - } - - task_set_event(TASK_ID_UCPD, - UCPD_EVT_RX_MSG); - - /* Send GoodCRC message (if required) */ - ucpd_send_good_crc(port, *rx_header); - } else if (good_crc) { - task_set_event(TASK_ID_UCPD, - UCPD_EVT_RX_GOOD_CRC); - ucpd_crc_id = PD_HEADER_ID(*rx_header); - } - } else { - /* Rx message is complete, but there were bit errors */ - CPRINTS("ucpd: rx message error"); - } - } - /* Check for fault conditions */ - if (sr & STM32_UCPD_SR_RXHRSTDET) { - /* hard reset received */ - pd_execute_hard_reset(port); - task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE); - hook_call_deferred(&ucpd_hard_reset_rx_log_data, 0); - } - - /* Clear interrupts now that PD events have been set */ - STM32_UCPD_ICR(port) = sr; -} -DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1); - -#ifdef CONFIG_STM32G4_UCPD_DEBUG -static char ctrl_names[][12] = { - "rsvd", - "GoodCRC", - "Goto Min", - "Accept", - "Reject", - "Ping", - "PS_Rdy", - "Get_SRC", - "Get_SNK", - "DR_Swap", - "PR_Swap", - "VCONN_Swp", - "Wait", - "Soft_Rst", - "RSVD", - "RSVD", - "Not_Sup", - "Get_SRC_Ext", - "Get_Status", -}; - -static char data_names[][10] = { - "RSVD", - "SRC_CAP", - "REQUEST", - "BIST", - "SINK_CAP", - "BATTERY", - "ALERT", - "GET_INFO", - "ENTER_USB", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "VDM", -}; - -static void ucpd_dump_msg_log(void) -{ - int i; - int type; - int len; - int dir; - uint16_t header; - char *name; - - - ccprintf("ucpd: msg_total = %d\n", msg_log_cnt); - ccprintf("Idx\t Delta(us)\tDir\t Type\t\tLen\t s1 s2 PR\t DR\n"); - ccprintf("-----------------------------------------------------------" - "-----------------\n"); - - for (i = 0; i < msg_log_idx; i++) { - uint32_t delta_ts = 0; - int j; - - header = msg_log[i].header; - - if (header != 0xabcd) { - type = PD_HEADER_TYPE(header); - len = PD_HEADER_CNT(header); - name = len ? data_names[type] : ctrl_names[type]; - dir = msg_log[i].dir; - if (i) { - delta_ts = msg_log[i].ts - msg_log[i-1].ts; - } - - ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d %d\t" - "%s\t %s", - i, - delta_ts, - dir ? "Rx" : "Tx", - name, - len, - msg_log[i].comp, - msg_log[i].crc, - PD_HEADER_PROLE(header) ? "SRC" : "SNK", - PD_HEADER_DROLE(header) ? "DFP" : "UFP"); - len = MIN((len * 4) + 2, MSG_BUF_LEN); - for (j = 0; j < len; j++) - ccprintf(" %02x", msg_log[i].buf[j]); - } else { - if (i) { - delta_ts = msg_log[i].ts - msg_log[i-1].ts; - } - ccprintf("msg[%02d]: %08d\t CC Voltage Change!", - i, delta_ts); - } - ccprintf("\n"); - msleep(5); - } -} - -static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp) -{ - int cc_enable; - uint32_t cr = STM32_UCPD_CR(port); - - /* - * Only update ANASUBMODE if specified pull type is Rp. - */ - if (pull == TYPEC_CC_RP) { - cr &= ~STM32_UCPD_CR_ANASUBMODE_MASK; - cr |= STM32_UCPD_CR_ANASUBMODE_VAL(UCPD_RP_TO_ANASUB(rp)); - } - - /* - * Can't independently set pull value for CC1 from CC2. But, can - * independently connect or disconnect pull for CC1 and CC2. Enable here - * the CC lines specified by cc_mask. If desired pull is TYPEC_CC_OPEN, - * then the CC lines specified in cc_mask will be disabled. - */ - /* Get existing cc enable value */ - cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >> - STM32_UCPD_CR_CCENABLE_SHIFT; - /* Apply cc_mask (enable CC line specified) */ - cc_enable |= cc_mask; - - /* Set ANAMODE if cc_pull is Rd */ - if (pull == TYPEC_CC_RD) - cr |= STM32_UCPD_CR_ANAMODE; - /* Clear ANAMODE if cc_pull is Rp */ - else if (pull == TYPEC_CC_RP) - cr &= ~(STM32_UCPD_CR_ANAMODE); - else if (pull == TYPEC_CC_OPEN) - cc_enable &= ~cc_mask; - - /* The value for this field needs to be OR'd in */ - cr &= ~STM32_UCPD_CR_CCENABLE_MASK; - cr |= STM32_UCPD_CR_CCENABLE_VAL(cc_enable); - /* Update pull values */ - STM32_UCPD_CR(port) = cr; - /* Display updated settings */ - ucpd_cc_status(port); -} - -void ucpd_info(int port) -{ - ucpd_cc_status(port); - ccprintf("\trx_en\t = %d\n\tpol\t = %d\n", - !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYRXEN), - !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_PHYCCSEL)); - - /* Dump ucpd task state info */ - ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n", - ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us); - - ucpd_task_log_dump(); -} - -static int command_ucpd(int argc, char **argv) -{ - uint32_t tx_data = 0; - char *e; - int val; - int port = 0; - - if (argc < 2) - return EC_ERROR_PARAM_COUNT; - - if (!strcasecmp(argv[1], "rst")) { - /* Force reset of ucpd peripheral */ - stm32gx_ucpd_init(port); - pd_execute_hard_reset(port); - task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_WAKE); - } else if (!strcasecmp(argv[1], "info")) { - ucpd_info(port); - } else if (!strcasecmp(argv[1], "bist")) { - /* Need to initiate via DPM to have a timer */ - /* TODO(b/182861002): uncomment when Gingerbread has - * full PD support landed. - * pd_dpm_request(port, DPM_REQUEST_BIST_TX); - */ - } else if (!strcasecmp(argv[1], "hard")) { - stm32gx_ucpd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, - &tx_data); - } else if (!strcasecmp(argv[1], "pol")) { - if (argc < 3) - return EC_ERROR_PARAM_COUNT; - val = strtoi(argv[2], &e, 10); - if (val > 1) - val = 0; - stm32gx_ucpd_set_polarity(port, val); - stm32gx_ucpd_set_rx_enable(port, 1); - ccprintf("ucpd: set pol = %d, PHYRXEN = 1\n", val); - } else if (!strcasecmp(argv[1], "cc")) { - int cc_mask; - int pull; - int rp = 0; /* needs to be initialized */ - - if (argc < 3) { - ucpd_cc_status(port); - return EC_SUCCESS; - } - cc_mask = strtoi(argv[2], &e, 10); - if (cc_mask < 1 || cc_mask > 3) - return EC_ERROR_PARAM2; - /* cc_mask has determines which cc setting to apply */ - if (!strcasecmp(argv[3], "rd")) { - pull = TYPEC_CC_RD; - } else if (!strcasecmp(argv[3], "rp")) { - pull = TYPEC_CC_RP; - rp = strtoi(argv[4], &e, 10); - if (rp < 0 || rp > 2) - return EC_ERROR_PARAM4; - } else if (!strcasecmp(argv[3], "open")) { - pull = TYPEC_CC_OPEN; - } else { - return EC_ERROR_PARAM3; - } - stm32gx_ucpd_set_cc_debug(port, cc_mask, pull, rp); - - } else if (!strcasecmp(argv[1], "log")) { - if (argc < 3) { - ucpd_dump_msg_log(); - } else if (!strcasecmp(argv[2], "clr")) { - msg_log_cnt = 0; - msg_log_idx = 0; - } - } else { - return EC_ERROR_PARAM1; - } - return EC_SUCCESS; -} -DECLARE_CONSOLE_COMMAND(ucpd, command_ucpd, - "[rst|info|bist|hard|pol <0|1>|cc xx <rd|rp|open>|log", - "ucpd peripheral debug and control options"); -#endif diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h deleted file mode 100644 index d3af41e5bc..0000000000 --- a/chip/stm32/ucpd-stm32gx.h +++ /dev/null @@ -1,231 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_UCPD_STM32GX_H -#define __CROS_EC_UCPD_STM32GX_H - -/* STM32 UCPD driver for Chrome EC */ - -#include "usb_pd_tcpm.h" - -/* - * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to - * a prescaler who's output feeds the 'half-bit' divider which is used - * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is - * designed to work in freq ranges of 6 <--> 18 MHz, however recommended - * range is 9 <--> 18 MHz. - * - * ------- @ 16 MHz --------- @ ~600 kHz ------------- - * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt | - * ------- --------- | ------------- - * | ------------- - * |---------->| ifrgap_cnt| - * ------------- - * Requirements: - * 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67 - * 2. tTransitionWindow - 12 to 20 uSec - * 3. tInterframGap - uSec - * - * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period - * tTransitionWindow = 1.687 uS * 8 = 13.5 uS - * tInterFrameGap = 1.687 uS * 17 = 28.68 uS - */ - -#define UCPD_PSC_DIV 1 -#define UCPD_HBIT_DIV 27 -#define UCPD_TRANSWIN_CNT 8 -#define UCPD_IFRGAP_CNT 17 - - -/* - * K-codes and ordered set defines. These codes and sets are used to encode - * which type of USB-PD message is being sent. This information can be found in - * the USB-PD spec section 5.4 - 5.6. This info is also included in the STM32G4 - * TRM (RM0440) 45.4.3 - */ -#define UCPD_SYNC1 0x18u -#define UCPD_SYNC2 0x11u -#define UCPD_SYNC3 0x06u -#define UCPD_RST1 0x07u -#define UCPD_RST2 0x19u -#define UCPD_EOP 0x0Du - -/* This order of this enum matches tcpm_sop_type */ -enum ucpd_tx_ordset { - TX_ORDERSET_SOP = (UCPD_SYNC1 | - (UCPD_SYNC1<<5u) | - (UCPD_SYNC1<<10u) | - (UCPD_SYNC2<<15u)), - - TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | - (UCPD_SYNC1<<5u) | - (UCPD_SYNC3<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_PRIME = (UCPD_SYNC1 | - (UCPD_SYNC3<<5u) | - (UCPD_SYNC1<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_DEBUG = (UCPD_SYNC1 | - (UCPD_RST2<<5u) | - (UCPD_RST2<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_PRIME_DEBUG = (UCPD_SYNC1 | - (UCPD_RST2<<5u) | - (UCPD_SYNC3<<10u) | - (UCPD_SYNC2<<15u)), - - TX_ORDERSET_HARD_RESET = (UCPD_RST1 | - (UCPD_RST1<<5u) | - (UCPD_RST1<<10u) | - (UCPD_RST2<<15u)), - - TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | - (UCPD_SYNC1<<5u) | - (UCPD_RST1<<10u) | - (UCPD_SYNC3<<15u)), -}; - - -/** - * STM32Gx UCPD implementation of tcpci .init method - * - * @param usbc_port -> USB-C Port number - * @return EC_SUCCESS - */ -int stm32gx_ucpd_init(int usbc_port); - -/** - * STM32Gx UCPD implementation of tcpci .release method - * - * @param usbc_port -> USB-C Port number - * @return EC_SUCCESS - */ -int stm32gx_ucpd_release(int usbc_port); - -/** - * STM32Gx UCPD implementation of tcpci .get_cc method - * - * @param usbc_port -> USB-C Port number - * @param *cc1 -> pointer to cc1 result - * @param *cc2 -> pointer to cc2 result - * @return EC_SUCCESS - */ -int stm32gx_ucpd_get_cc(int usbc_port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); - -/** - * STM32Gx equivalent for TCPCI role_control register - * - * @param usbc_port -> USB-C Port number - * @return EC_SUCCESS - */ -int stm32gx_ucpd_get_role_control(int usbc_port); - -/** - * STM32Gx UCPD implementation of tcpci .set_cc method - * - * @param usbc_port -> USB-C Port number - * @param cc_pull -> Rp or Rd selection - * @param rp -> value of Rp (if cc_pull == Rp) - * @return EC_SUCCESS - */ -int stm32gx_ucpd_set_cc(int usbc_port, int cc_pull, int rp); - -/** - * STM32Gx UCPD implementation of tcpci .set_cc method - * - * @param usbc_port -> USB-C Port number - * @param polarity -> CC1 or CC2 selection - * @return EC_SUCCESS - */ -int stm32gx_ucpd_set_polarity(int usbc_port, enum tcpc_cc_polarity polarity); - -/** - * STM32Gx UCPD implementation of tcpci .set_rx_enable method - * - * @param usbc_port -> USB-C Port number - * @param enable -> on/off for USB-PD messages - * @return EC_SUCCESS - */ -int stm32gx_ucpd_set_rx_enable(int port, int enable); - -/** - * STM32Gx UCPD implementation of tcpci .set_msg_header method - * - * @param usbc_port -> USB-C Port number - * @param power_role -> port's current power role - * @param data_role -> port's current data role - * @return EC_SUCCESS - */ -int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role); - -/** - * STM32Gx UCPD implementation of tcpci .transmit method - * - * @param usbc_port -> USB-C Port number - * @param type -> SOP/SOP'/SOP'' etc - * @param header -> usb pd message header - * @param *data -> pointer to message contents - * @return EC_SUCCESS - */ -int stm32gx_ucpd_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, - const uint32_t *data); - -/** - * STM32Gx UCPD implementation of tcpci .get_message_raw method - * - * @param usbc_port -> USB-C Port number - * @param *payload -> pointer to where message should be written - * @param *head -> pointer to message header - * @return EC_SUCCESS - */ -int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head); - -/** - * STM32Gx method to remove Rp when VCONN is being supplied - * - * @param usbc_port -> USB-C Port number - * @param enable -> connect/disc Rp - * @return EC_SUCCESS - */ -int stm32gx_ucpd_vconn_disc_rp(int port, int enable); - -/** - * STM32Gx UCPD implementation of tcpci .sop_prime_enable method - * - * @param usbc_port -> USB-C Port number - * @param enable -> control of SOP'/SOP'' messages - * @return EC_SUCCESS - */ -int stm32gx_ucpd_sop_prime_enable(int port, bool enable); - -int stm32gx_ucpd_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info); - -/** - * This function is used to enable/disable a ucpd debug feature that is used to - * mark the ucpd message log when there is a usbc detach event. - * - * @param enable -> on/off control for debug feature - */ -void ucpd_cc_detect_notify_enable(int enable); - -/** - * This function is used to enable/disable rx bist test mode in the ucpd - * driver. This mode is controlled at the PE layer. When this mode is enabled, - * the ucpd receiver will not pass BIST data messages to the protocol layer and - * only send GoodCRC replies. - * - * @param usbc_port -> USB-C Port number - * @param enable -> on/off control for rx bist mode - */ -enum ec_error_list stm32gx_ucpd_set_bist_test_mode(const int port, - const bool enable); - -#endif /* __CROS_EC_UCPD_STM32GX_H */ diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c deleted file mode 100644 index 908542146f..0000000000 --- a/chip/stm32/usart-stm32f0.c +++ /dev/null @@ -1,166 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32f0.h" - -#include "clock.h" -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 4 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - /* - * Make sure we register this config before enabling the HW. - * If we did it the other way around the FREQ_CHANGE hook could be - * called before we update the configs array and we would miss the - * clock frequency change event, leaving our baud rate divisor wrong. - */ - configs[config->hw->index] = config; - - usart_set_baud(config, config->baud); - - task_enable_irq(config->hw->irq); -} - -void usart_set_baud(struct usart_config const *config, int baud) -{ - usart_set_baud_f0_l(config, baud, clock_get_freq()); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - int index = config->hw->index; - - /* - * Only disable the shared interrupt for USART3/4 if both USARTs are - * now disabled. - */ - if ((index == 0) || - (index == 1) || - (index == 2 && configs[3] == NULL) || - (index == 3 && configs[2] == NULL)) - task_disable_irq(config->hw->irq); - - configs[index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -static void freq_change(void) -{ - size_t i; - - for (i = 0; i < ARRAY_SIZE(configs); ++i) - if (configs[i]) - usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); -} - -DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3_4, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART4) -struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART3_4, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART3) || defined(CONFIG_STREAM_USART4) -void usart3_4_interrupt(void) -{ - /* - * This interrupt handler could be called with one of these configs - * not initialized, so we need to check here and only call the generic - * USART interrupt handler for initialized configs. - */ - if (configs[2]) - usart_interrupt(configs[2]); - - if (configs[3]) - usart_interrupt(configs[3]); -} - -DECLARE_IRQ(STM32_IRQ_USART3_4, usart3_4_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h deleted file mode 100644 index 1b7eee95a7..0000000000 --- a/chip/stm32/usart-stm32f0.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32F0_H -#define __CROS_EC_USART_STM32F0_H - -#include "usart.h" - -/* - * The STM32F0 series can have as many as four UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; -extern struct usart_hw_config const usart4_hw; - -#endif /* __CROS_EC_USART_STM32F0_H */ diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c deleted file mode 100644 index 42a0cf310e..0000000000 --- a/chip/stm32/usart-stm32f3.c +++ /dev/null @@ -1,120 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32f3.h" - -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 3 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - configs[config->hw->index] = config; - - /* - * All three USARTS are clocked from the HSI(8MHz) source. This is - * done because the clock sources elsewhere are setup so that the result - * of clock_get_freq() is not the input clock frequency to the USARTs - * baud rate divisors. - */ - STM32_RCC_CFGR3 |= 0x000f0003; - - usart_set_baud_f0_l(config, config->baud, 8000000); - - task_enable_irq(config->hw->irq); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - task_disable_irq(config->hw->irq); - - configs[config->hw->index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_ICR(config->hw->base) |= STM32_USART_ICR_TCCF; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART3) -void usart3_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h deleted file mode 100644 index 09f1ba608c..0000000000 --- a/chip/stm32/usart-stm32f3.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32F3_H -#define __CROS_EC_USART_STM32F3_H - -#include "usart.h" - -/* - * The STM32F3 series can have as many as three UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; - -#endif /* __CROS_EC_USART_STM32F3_H */ diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c deleted file mode 100644 index a554da147a..0000000000 --- a/chip/stm32/usart-stm32f4.c +++ /dev/null @@ -1,113 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "usart-stm32f4.h" - -#include "clock.h" -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 3 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - configs[config->hw->index] = config; - - - /* Use single-bit sampling */ - STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT; - - usart_set_baud_f0_l(config, config->baud, clock_get_freq()); - - task_enable_irq(config->hw->irq); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - task_disable_irq(config->hw->irq); - - configs[config->hw->index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; -#endif - -#if defined(CONFIG_STREAM_USART3) -void usart3_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32f4.h b/chip/stm32/usart-stm32f4.h deleted file mode 100644 index 49af2af405..0000000000 --- a/chip/stm32/usart-stm32f4.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32F4_H -#define __CROS_EC_USART_STM32F4_H - -#include "usart.h" - -/* - * The STM32F4 series can have as many as three UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - * CONFIG_STREAM_USART<X> enables the corresponding hardware instance. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; - -#endif /* __CROS_EC_USART_STM32F4_H */ diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c deleted file mode 100644 index 2b7406a0a4..0000000000 --- a/chip/stm32/usart-stm32l.c +++ /dev/null @@ -1,132 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32l.h" - -#include "clock.h" -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 3 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - /* Use single-bit sampling */ - STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT; - - /* - * Make sure we register this config before enabling the HW. - * If we did it the other way around the FREQ_CHANGE hook could be - * called before we update the configs array and we would miss the - * clock frequency change event, leaving our baud rate divisor wrong. - */ - configs[config->hw->index] = config; - - usart_set_baud_f0_l(config, config->baud, clock_get_freq()); - - task_enable_irq(config->hw->irq); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - task_disable_irq(config->hw->irq); - - configs[config->hw->index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -static void freq_change(void) -{ - size_t i; - - for (i = 0; i < ARRAY_SIZE(configs); ++i) - if (configs[i]) - usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); -} - -DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; - -void usart3_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h deleted file mode 100644 index eb1ae9db1d..0000000000 --- a/chip/stm32/usart-stm32l.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32L_H -#define __CROS_EC_USART_STM32L_H - -#include "usart.h" - -/* - * The STM32L series can have as many as three UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; - -#endif /* __CROS_EC_USART_STM32L_H */ diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c deleted file mode 100644 index 0245718e21..0000000000 --- a/chip/stm32/usart-stm32l5.c +++ /dev/null @@ -1,150 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart-stm32l.h" - -#include "clock.h" -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "registers.h" -#include "task.h" -#include "util.h" - -/* - * This configs array stores the currently active usart_config structure for - * each USART, an entry will be NULL if no USART driver is initialized for the - * corresponding hardware instance. - */ -#define STM32_USARTS_MAX 4 - -static struct usart_config const *configs[STM32_USARTS_MAX]; - -struct usart_configs usart_get_configs(void) -{ - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; -} - -static void usart_variant_enable(struct usart_config const *config) -{ - /* Use single-bit sampling */ - STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT; - - /* - * Make sure we register this config before enabling the HW. - * If we did it the other way around the FREQ_CHANGE hook could be - * called before we update the configs array and we would miss the - * clock frequency change event, leaving our baud rate divisor wrong. - */ - configs[config->hw->index] = config; - - usart_set_baud_f0_l(config, config->baud, clock_get_freq()); - - task_enable_irq(config->hw->irq); -} - -static void usart_variant_disable(struct usart_config const *config) -{ - task_disable_irq(config->hw->irq); - - configs[config->hw->index] = NULL; -} - -static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, - .disable = usart_variant_disable, -}; - -static void freq_change(void) -{ - size_t i; - - for (i = 0; i < ARRAY_SIZE(configs); ++i) - if (configs[i]) - usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); -} - -DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); - -void usart_clear_tc(struct usart_config const *config) -{ - STM32_USART_SR(config->hw->base) &= ~STM32_USART_SR_TC; -} - -/* - * USART interrupt bindings. These functions can not be defined as static or - * they will be removed by the linker because of the way that DECLARE_IRQ works. - */ -#if defined(CONFIG_STREAM_USART1) -struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, - .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, -}; - -void usart1_interrupt(void) -{ - usart_interrupt(configs[0]); -} - -DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART2) -struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, -}; - -void usart2_interrupt(void) -{ - usart_interrupt(configs[1]); -} - -DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART3) -struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, -}; - -void usart3_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2); -#endif - -#if defined(CONFIG_STREAM_USART4) -struct usart_hw_config const usart4_hw = { - .index = 2, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART4, - .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, -}; - -void usart4_interrupt(void) -{ - usart_interrupt(configs[2]); -} - -DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2); -#endif diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h deleted file mode 100644 index 564ffbc580..0000000000 --- a/chip/stm32/usart-stm32l5.h +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_STM32L5_H -#define __CROS_EC_USART_STM32L5_H - -#include "usart.h" - -/* - * The STM32L5 series can have as many as four UARTS. These are the HW configs - * for those UARTS. They can be used to initialize STM32 generic UART configs. - */ -extern struct usart_hw_config const usart1_hw; -extern struct usart_hw_config const usart2_hw; -extern struct usart_hw_config const usart3_hw; -extern struct usart_hw_config const usart4_hw; - -#endif /* __CROS_EC_USART_STM32L5_H */ diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c deleted file mode 100644 index 7f8c55aaa6..0000000000 --- a/chip/stm32/usart.c +++ /dev/null @@ -1,172 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* USART driver for Chrome EC */ - -#include "atomic.h" -#include "common.h" -#include "gpio.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "usart.h" -#include "util.h" - -void usart_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - uint32_t cr2, cr3; - - /* - * Enable clock to USART, this must be done first, before attempting - * to configure the USART. - */ - *(config->hw->clock_register) |= config->hw->clock_enable; - - /* - * For STM32F3, A delay of 1 APB clock cycles is needed before we - * can access any USART register. Fortunately, we have - * gpio_config_module() below and thus don't need to add the delay. - */ - - /* - * Switch all GPIOs assigned to the USART module over to their USART - * alternate functions. - */ - gpio_config_module(MODULE_USART, 1); - - /* - * 8N1, 16 samples per bit. error interrupts, and special modes - * disabled. - */ - - cr2 = 0x0000; - cr3 = 0x0000; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) - if (config->flags & USART_CONFIG_FLAG_RX_INV) - cr2 |= BIT(16); - if (config->flags & USART_CONFIG_FLAG_TX_INV) - cr2 |= BIT(17); -#endif - if (config->flags & USART_CONFIG_FLAG_HDSEL) - cr3 |= BIT(3); - - STM32_USART_CR1(base) = 0x0000; - STM32_USART_CR2(base) = cr2; - STM32_USART_CR3(base) = cr3; - - /* - * Enable the RX, TX, and variant specific HW. - */ - config->rx->init(config); - config->tx->init(config); - config->hw->ops->enable(config); - - /* - * Clear error counts. - */ - config->state->rx_overrun = 0; - config->state->rx_dropped = 0; - - /* - * Enable the USART, this must be done last since most of the - * configuration bits require that the USART be disabled for writes to - * succeed. - */ - STM32_USART_CR1(base) |= STM32_USART_CR1_UE; -} - -void usart_shutdown(struct usart_config const *config) -{ - STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_UE; - - config->hw->ops->disable(config); -} - -void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz) -{ - int div = DIV_ROUND_NEAREST(frequency_hz, baud); - intptr_t base = config->hw->base; - - if (div / 16 > 0) { - /* - * CPU clock is high enough to support x16 oversampling. - * BRR = (div mantissa)<<4 | (4-bit div fraction) - */ - STM32_USART_CR1(base) &= ~STM32_USART_CR1_OVER8; - STM32_USART_BRR(base) = div; - } else { - /* - * CPU clock is low; use x8 oversampling. - * BRR = (div mantissa)<<4 | (3-bit div fraction) - */ - STM32_USART_BRR(base) = ((div / 8) << 4) | (div & 7); - STM32_USART_CR1(base) |= STM32_USART_CR1_OVER8; - } -} - -void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz) -{ - int div = DIV_ROUND_NEAREST(frequency_hz, baud); - - /* STM32F only supports x16 oversampling */ - STM32_USART_BRR(config->hw->base) = div; -} - -int usart_get_parity(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - if (!(STM32_USART_CR1(base) & STM32_USART_CR1_PCE)) - return 0; - if (STM32_USART_CR1(base) & STM32_USART_CR1_PS) - return 1; - return 2; -} - -/* - * We only allow 8 bit word. CR1_PCE modifies parity enable, - * CR1_PS modifies even/odd, CR1_M modifies total word length - * to make room for parity. - */ -void usart_set_parity(struct usart_config const *config, int parity) -{ - uint32_t ue; - intptr_t base = config->hw->base; - - if ((parity < 0) || (parity > 2)) - return; - - /* Record active state and disable the UART. */ - ue = STM32_USART_CR1(base) & STM32_USART_CR1_UE; - STM32_USART_CR1(base) &= ~STM32_USART_CR1_UE; - - if (parity) { - /* Set parity control enable. */ - STM32_USART_CR1(base) |= - (STM32_USART_CR1_PCE | STM32_USART_CR1_M); - /* Set parity select even/odd bit. */ - if (parity == 2) - STM32_USART_CR1(base) &= ~STM32_USART_CR1_PS; - else - STM32_USART_CR1(base) |= STM32_USART_CR1_PS; - } else { - STM32_USART_CR1(base) &= - ~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS | - STM32_USART_CR1_M); - } - - /* Restore active state. */ - STM32_USART_CR1(base) |= ue; -} - -void usart_interrupt(struct usart_config const *config) -{ - config->tx->interrupt(config); - config->rx->interrupt(config); -} diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h deleted file mode 100644 index 491bd66a04..0000000000 --- a/chip/stm32/usart.h +++ /dev/null @@ -1,271 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USART_H -#define __CROS_EC_USART_H - -/* STM32 USART driver for Chrome EC */ - -#include "common.h" -#include "consumer.h" -#include "producer.h" -#include "queue.h" - -#include <stdint.h> - -/* - * Per-USART state stored in RAM. This structure will be zero initialized by - * BSS init. - */ -struct usart_state { - /* - * Counter of bytes received and then dropped because of lack of space - * in the RX queue. - */ - uint32_t rx_dropped; - - /* - * Counter of the number of times an receive overrun condition is - * detected. This will not usually be a count of the number of bytes - * that were lost due to overrun conditions. - */ - uint32_t rx_overrun; -}; - -struct usart_config; - -struct usart_hw_ops { - /* - * The generic USART initialization code calls this function to allow - * the variant HW specific code to perform any initialization. This - * function is called before the USART is enabled, and should among - * other things enable the USARTs interrupt. - */ - void (*enable)(struct usart_config const *config); - - /* - * The generic USART shutdown code calls this function, allowing the - * variant specific code an opportunity to do any variant specific - * shutdown tasks. - */ - void (*disable)(struct usart_config const *config); -}; - -/* - * The usart_rx/usart_tx structures contain functions pointers for the - * interrupt handler and producer/consumer operations required to implement a - * particular RX/TX strategy. - * - * These structures are defined by the various RX/TX implementations, and are - * used to initialize the usart_config structure to configure the USART driver - * for interrupt or DMA based transfer. - */ -struct usart_rx { - void (*init)(struct usart_config const *config); - void (*interrupt)(struct usart_config const *config); - - /* - * Print to the console any per-strategy diagnostic information, this - * is used by the usart_info command. This can be NULL if there is - * nothing interesting to display. - */ - void (*info)(struct usart_config const *config); - - struct producer_ops producer_ops; -}; - -struct usart_tx { - void (*init)(struct usart_config const *config); - void (*interrupt)(struct usart_config const *config); - - /* - * Print to the console any per-strategy diagnostic information, this - * is used by the usart_info command. This can be NULL if there is - * nothing interesting to display. - */ - void (*info)(struct usart_config const *config); - - struct consumer_ops consumer_ops; -}; - -extern struct usart_rx const usart_rx_interrupt; -extern struct usart_tx const usart_tx_interrupt; - -/* - * Per-USART hardware configuration stored in flash. Instances of this - * structure are provided by each variants driver, one per physical USART. - */ -struct usart_hw_config { - int index; - intptr_t base; - int irq; - - uint32_t volatile *clock_register; - uint32_t clock_enable; - - struct usart_hw_ops const *ops; -}; - -/* - * Compile time Per-USART configuration stored in flash. Instances of this - * structure are provided by the user of the USART. This structure binds - * together all information required to operate a USART. - */ -struct usart_config { - /* - * Pointer to USART HW configuration. There is one HW configuration - * per physical USART. - */ - struct usart_hw_config const *hw; - - struct usart_rx const *rx; - struct usart_tx const *tx; - - /* - * Pointer to USART state structure. The state structure maintains per - * USART information. - */ - struct usart_state volatile *state; - - /* - * Baud rate for USART. - */ - int baud; - - /* Other flags (rx/tx inversion, half-duplex). */ -#define USART_CONFIG_FLAG_RX_INV BIT(0) -#define USART_CONFIG_FLAG_TX_INV BIT(1) -#define USART_CONFIG_FLAG_HDSEL BIT(2) - unsigned int flags; - - struct consumer consumer; - struct producer producer; -}; - -/* - * Convenience macro for defining USARTs and their associated state and buffers. - * NAME is used to construct the names of the usart_state struct, and - * usart_config struct, the latter is just called NAME. - * - * HW is the name of the usart_hw_config provided by the variant specific code. - * - * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this USART - * should write to and read from respectively. - */ -/* - * The following assertions can not be made because they require access to - * non-const fields, but should be kept in mind. - * - * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); - * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); - */ -#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \ - ((struct usart_config const) { \ - .hw = &HW, \ - .rx = &RX, \ - .tx = &TX, \ - .state = &((struct usart_state){}), \ - .baud = BAUD, \ - .flags = FLAGS, \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &TX.consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &RX.producer_ops, \ - }, \ - }) - -/* - * Initialize the given USART. Once init is finished the USART streams are - * available for operating on. - */ -void usart_init(struct usart_config const *config); - -/* - * Shutdown the given USART. - */ -void usart_shutdown(struct usart_config const *config); - -/* - * Handle a USART interrupt. The per-variant USART code creates bindings - * for the variants interrupts to call this generic USART interrupt handler - * with the appropriate usart_config. - */ -void usart_interrupt(struct usart_config const *config); - -/* - * Trigger tx interrupt to process tx data. Calling this function will set - * TXIEIE of USART HW instance and trigger associated IRQ. - */ -void usart_tx_start(struct usart_config const *config); - -/* - * These are HW specific baud rate calculation and setting functions that the - * peripheral variant code uses during initialization and clock frequency - * change. The baud rate divisor input frequency is passed in Hertz. - */ -void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz); -void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz); - -/* - * Allow specification of parity for this usart. - * parity is 0: none, 1: odd, 2: even. - */ -void usart_set_parity(struct usart_config const *config, int parity); - -/* - * Check parity for this usart. - * parity is 0: none, 1: odd, 2: even. - */ -int usart_get_parity(struct usart_config const *config); - -/* - * Set baud rate for this usart. Note that baud rate will get reset on - * core frequency change, so this only makes sense if the board never - * goes to deep idle. - */ -void usart_set_baud(struct usart_config const *config, int baud); - -/* - * Different families provide different ways of clearing the transmit complete - * flag. This function will be provided by the family specific implementation. - */ -void usart_clear_tc(struct usart_config const *config); - -/* - * Each family implementation provides the usart_get_configs function to access - * a read only list of the configs that are currently enabled. - */ -struct usart_configs { - /* - * The family's usart_config array, entries in the array for disabled - * configs will be NULL, enabled configs will point to the usart_config - * that was enabled. And the following will be true: - * - * configs[i]->hw->index == i; - */ - struct usart_config const * const *configs; - - /* - * The total possible number of configs that this family supports. - * This will be the same as the number of usart_hw structs that the - * family provides in its family specific usart header. - */ - size_t count; -}; - -struct usart_configs usart_get_configs(void); - -/* - * This usart_tx structure contains function pointer to interrupt - * handler implemented to send host response. Generic queue based - * interrupt handler is not used for usart host transport. - */ -extern struct usart_tx const usart_host_command_tx_interrupt; - -#endif /* __CROS_EC_USART_H */ diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c deleted file mode 100644 index f4d6a65fc4..0000000000 --- a/chip/stm32/usart_host_command.c +++ /dev/null @@ -1,616 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "clock.h" -#include "dma.h" -#include "gpio.h" -#include "hooks.h" -#include "host_command.h" -#include "queue_policies.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "usart_rx_dma.h" -#include "usart_host_command.h" -#include "usart-stm32f4.h" -#include "util.h" - -/* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args) - -/* - * Timeout to wait for complete request packet - * - * This value determines how long we should wait for entire packet to arrive. - * USART host command handler should wait for at least 75% of - * EC_MSG_DEADLINE_MS, before declaring timeout and dropping the packet. - * - * This timeout should be less than host's driver timeout to make sure that - * last packet can be successfully discarded before AP attempts to resend - * request. AP driver waits for EC_MSG_DEADLINE_MS = 200 before attempting a - * retry. - */ -#define USART_REQ_RX_TIMEOUT (150 * MSEC) - -/* - * Timeout to wait for overrun bytes on USART - * - * This values determines how long call to process_request should be deferred - * in case host is sending extra bytes. This value is based on DMA buffer size. - * - * There is no guarantee that AP will send continuous bytes on usart. Wait - * for USART_DEFERRED_PROCESS_REQ_TIMEOUT_US to check if host is sending - * extra bytes. - * Note: This value affects the response latency. - */ -#define USART_DEFERRED_PROCESS_REQ_TIMEOUT 300 - -/* - * Max data size for a version 3 request/response packet. This is big enough - * to handle a request/response header, flash write offset/size and 512 bytes - * of request payload or 224 bytes of response payload. - */ -#define USART_MAX_REQUEST_SIZE 0x220 -#define USART_MAX_RESPONSE_SIZE 0x100 - -/* - * FIFO size for USART DMA. Should be big enough to handle worst case - * data processing - */ -#define USART_DMA_FIFO_SIZE 0x110 - -/* Local definitions */ - -/* - * Raw USART RX/TX byte buffers. - */ -static uint8_t usart_in_buffer[USART_MAX_REQUEST_SIZE] __aligned(4); -static uint8_t usart_out_buffer[USART_MAX_RESPONSE_SIZE] __aligned(4); - -/* - * Maintain head position of in buffer - * Head always starts with zero and goes up to max bytes. - * Once the buffer contents are read, it should go back to zero. - */ -static uint16_t usart_in_head; - -/* - * Maintain head position of out buffer - * Head always starts from zero and goes up to max bytes. - * Head is moved by tx interrupt handler to response size sent by host command - * task. Once all the bytes are sent (head == tail) both should go back to 0. - */ -static uint16_t usart_out_head; - -/* - * Once the response is ready, get the datalen - */ -static uint16_t usart_out_datalen; - -/* - * Enumeration to maintain different states of incoming request from - * host - */ -static enum uart_host_command_state { - /* - * USART host command handler not enabled. - */ - USART_HOST_CMD_STATE_DISABLED, - - /* - * Ready to receive next request - * This state represents USART layer is initialized and ready to - * receive host request. Once the response is sent, current_state is - * reset to this state to accept next packet. - */ - USART_HOST_CMD_READY_TO_RX, - - /* - * Receiving request - * After first byte is received current_state is moved to receiving - * state until all the header bytes + datalen bytes are received. - * If host_request_timeout was called in this state, it would be - * because of an underrun situation. - */ - USART_HOST_CMD_RECEIVING, - - /* - * Receiving complete - * Once all the header bytes + datalen bytes are received, current_state - * is moved to complete. Ideally, host should wait for response or retry - * timeout before sending anymore bytes, otherwise current_state will - * be moved to overrun to represent extra bytes sent by host. - */ - USART_HOST_CMD_COMPLETE, - - /* - * Processing request - * Once the process_request starts processing usart_in_buffer, - * current_state is moved to processing state. Host should not send - * any bytes in this state as it would be considered contiguous - * request. - */ - USART_HOST_CMD_PROCESSING, - - /* - * Sending response - * Once host task is ready with the response bytes, current_state is - * moved to sending state. - */ - USART_HOST_CMD_SENDING, - - /* - * Received bad data - * If bad packet header is received, current_state is moved to rx_bad - * state and after rx_timeout all the bytes are dropped. - */ - USART_HOST_CMD_RX_BAD, - - /* - * Receiving data overrun bytes - * If extra bytes are received after current_state is in complete, - * host is sending extra bytes which indicates data overrun. - */ - USART_HOST_CMD_RX_OVERRUN, - -} current_state __aligned(4); - -/* - * This diagram is the state machine representation of USART host - * command layer. - * - * This layer is responsible for checking packet integrity of incoming bytes - * on usart transceiver. It will only process packet header to check version, - * data_len. This layer will not process payload bytes. - * - * STATE = USART_HOST_CMD_STATE_DISABLED - * - * Initialize USART and local variables - * - * STATE = USART_HOST_CMD_READY_TO_RX - * - * |<---------- HOST RETRY TIMEOUT = 200 ms ---------->| - * | - * |--------------USART_REQ_RX_TIMEOUT------>| - * | Underrun if request not complete -->| - * | |<-- USART ready to rx - * |____REQUEST____ ____REQUEST____ - * | | | | | | - * | HDR | DATA | | HDR | DATA | - * |_____|_________| |_____|_________| - * | - * |<-- Request packet start - * | - * STATE = USART_HOST_CMD_RECEIVING - * | - * |<-- HDR received, now we will wait for data len bytes - * | - * If bad packet is received, move state to rx_bad - * STATE = USART_HOST_CMD_RX_BAD - * Ignore data processing, print status on console and reset layer ----------- - * | | - * |<-- Request packet end (data rx complete) | - * | | - * If request_timeout is called, it represents packet underrun | - * Ignore data processing, print status on console and reset layer ----------- - * | | - * STATE = USART_HOST_CMD_COMPLETE | - * | | - * |<-- Deferred call to process request | - * | | - * If extra byte is received, move state to overrun | - * STATE = USART_HOST_CMD_RX_OVERRUN | - * Ignore data processing, print status on console and reset layer ----------- - * | | - * -->| |<-- USART_DEFERRED_PROCESS_REQ_TIMEOUT | - * | Start process request | - * | | - * STATE = USART_HOST_CMD_PROCESSING | - * | | - * Send ec_host_request to host command task | - * |<-- Packet sent to host command task | - * >| |<-- host command task process time | - * |<-- host command task ready for response | - * | | - * STATE = USART_HOST_CMD_SENDING | - * | | - * |____RESPONSE____ | - * | | | | - * | HDR | DATA | | - * |_____|__________| | - * | | - * |<-- Response send complete | - * | - * STATE = USART_HOST_CMD_READY_TO_RX <------------------------------ - */ - -/* - * Local function definition - */ -static void usart_host_command_reset(void); -static void usart_host_command_request_timeout(void); -static void usart_host_command_process_request(void); -static void usart_host_command_process_response(struct host_packet *pkt); -/* - * Local variable declaration - */ - -/* - * Configure dma instance for rx - * - * STM32_DMAS_USART1_RX is the DMA channel to be used for reception. This DMA - * channel is for the USART peripheral. - * - * A unnamed, valid, empty usart_rx_dma_state structure is required to manage - * DMA based transmission. - * - * USART_DMA_FIFO_SIZE is size of the valid, unnamed DMA circular buffer. - * This buffer is large enough to process worst case interrupt latency this - * layer can encounter. - */ -static struct usart_rx_dma const usart_host_command_rx_dma = { - .usart_rx = { - .producer_ops = { - .read = NULL, - }, - .init = usart_rx_dma_init, - .interrupt = usart_host_command_rx_dma_interrupt, - .info = USART_RX_DMA_INFO, - }, - .state = &((struct usart_rx_dma_state) {}), - .fifo_buffer = ((uint8_t[USART_DMA_FIFO_SIZE]) {}), - .fifo_size = USART_DMA_FIFO_SIZE, - .channel = STM32_DMAS_USART1_RX, -}; - -/* - * Configure USART structure with hardware, interrupt handlers, baudrate. - */ -static struct usart_config const tl_usart = { - .hw = &CONFIG_UART_HOST_COMMAND_HW, - .rx = &usart_host_command_rx_dma.usart_rx, - .tx = &usart_host_command_tx_interrupt, - .state = &((struct usart_state){}), - .baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE, - .flags = 0, -}; - -/* - * Local function declaration - */ - -/* - * This function will be called only if request rx timed out. - * Drop the packet and put tl state into RX_READY - */ -static void usart_host_command_request_timeout(void) -{ - switch (current_state) { - case USART_HOST_CMD_RECEIVING: - /* If state is receiving then timeout was hit due to underrun */ - CPRINTS("USART HOST CMD ERROR: Request underrun detected."); - break; - - case USART_HOST_CMD_RX_OVERRUN: - /* If state is rx_overrun then timeout was hit because - * process request was cancelled and extra rx bytes were - * dropped - */ - CPRINTS("USART HOST CMD ERROR: Request overrun detected."); - break; - - case USART_HOST_CMD_RX_BAD: - /* If state is rx_bad then packet header was bad and process - * request was cancelled to drop all incoming bytes. - */ - CPRINTS("USART HOST CMD ERROR: Bad packet header detected."); - break; - - default: - CPRINTS("USART HOST CMD ERROR: Request timeout mishandled"); - } - - /* Reset host command layer to accept new request */ - usart_host_command_reset(); -} -DECLARE_DEFERRED(usart_host_command_request_timeout); - -/* - * This function is called from interrupt handler after entire packet is - * received. - */ -static void usart_host_command_process_request(void) -{ - /* Handle usart_in_buffer as ec_host_request */ - struct ec_host_request *ec_request = - (struct ec_host_request *)usart_in_buffer; - - /* Prepare host_packet for host command task */ - static struct host_packet uart_packet; - - /* - * Disable interrupts before processing request to be sent - * to host command task. - */ - interrupt_disable(); - - /* - * In case rx interrupt handler was called in this function's prologue, - * host was trying to send extra byte(s) exactly when - * USART_DEFERRED_PROCESS_REQ_TIMEOUT expired. If state is - * not USART_HOST_CMD_COMPLETE, overrun condition is already - * handled. - */ - if (current_state != USART_HOST_CMD_COMPLETE) { - /* Enable interrupts before exiting this function. */ - interrupt_enable(); - - return; - } - - /* Move current_state to USART_HOST_CMD_PROCESSING */ - current_state = USART_HOST_CMD_PROCESSING; - - /* Enable interrupts as current_state is safely handled. */ - interrupt_enable(); - - /* - * Cancel deferred call to timeout handler as request - * received was good. - */ - hook_call_deferred( - &usart_host_command_request_timeout_data, - -1); - - uart_packet.send_response = usart_host_command_process_response; - uart_packet.request = usart_in_buffer; - uart_packet.request_temp = NULL; - uart_packet.request_max = sizeof(usart_in_buffer); - uart_packet.request_size = - host_request_expected_size(ec_request); - uart_packet.response = usart_out_buffer; - uart_packet.response_max = sizeof(usart_out_buffer); - uart_packet.response_size = 0; - uart_packet.driver_result = EC_RES_SUCCESS; - - /* Process usart_packet */ - host_packet_receive(&uart_packet); -} -DECLARE_DEFERRED(usart_host_command_process_request); - -/* - * This function is called from host command task after it is ready with a - * response. - */ -static void usart_host_command_process_response(struct host_packet *pkt) -{ - /* Disable interrupts before entering critical section. */ - interrupt_disable(); - - /* - * Send host command response in usart_out_buffer via - * tx_interrupt_handler. - * - * Send response if current state is USART_HOST_CMD_PROCESSING - * state. If this layer is in any other state drop response and - * let request timeout handler handle state transitions. - */ - if (current_state != USART_HOST_CMD_PROCESSING) { - /* Enable interrupts before exiting critical section. */ - interrupt_enable(); - - return; - } - - /* Move to sending state. */ - current_state = USART_HOST_CMD_SENDING; - - /* Enable interrupts before exiting critical section. */ - interrupt_enable(); - - usart_out_datalen = pkt->response_size; - usart_out_head = 0; - - /* Start sending response to host via usart tx by - * triggering tx interrupt. - */ - usart_tx_start(&tl_usart); -} - -/* - * This function will drop current request, clear buffers. - */ -static void usart_host_command_reset(void) -{ - /* Cancel deferred call to process_request. */ - hook_call_deferred( - &usart_host_command_process_request_data, - -1); - - /* Cancel deferred call to timeout handler. */ - hook_call_deferred( - &usart_host_command_request_timeout_data, - -1); - - /* - * Disable interrupts before entering critical region - * Operations in this section should be minimum to avoid - * harming the real-time characteristics of the runtime. - */ - interrupt_disable(); - - /* Clear in buffer, head and datalen */ - usart_in_head = 0; - - /* Clear out buffer, head and datalen */ - usart_out_datalen = 0; - usart_out_head = 0; - - /* Move to ready state*/ - current_state = USART_HOST_CMD_READY_TO_RX; - - /* Enable interrupts before exiting critical region - */ - interrupt_enable(); -} - -/* - * Exported functions - */ - -/* - * Initialize USART host command layer. - */ -void usart_host_command_init(void) -{ - /* USART host command layer starts in DISABLED state */ - current_state = USART_HOST_CMD_STATE_DISABLED; - - /* Initialize transport uart */ - usart_init(&tl_usart); - - /* Initialize local variables */ - usart_in_head = 0; - usart_out_head = 0; - usart_out_datalen = 0; - - /* Move to ready state */ - current_state = USART_HOST_CMD_READY_TO_RX; -} - -/* - * Function to handle incoming bytes from DMA interrupt handler - * - */ -size_t usart_host_command_rx_append_data(struct usart_config const *config, - const uint8_t *src, size_t count) -{ - /* Define ec_host_request pointer to process in bytes later*/ - struct ec_host_request *ec_request = - (struct ec_host_request *) usart_in_buffer; - - /* Once the header is received, store the datalen */ - static int usart_in_datalen; - - /* - * Host can send extra bytes than in header data_len - * Only copy valid bytes in buffer - */ - if (current_state == USART_HOST_CMD_READY_TO_RX || - current_state == USART_HOST_CMD_RECEIVING || - (usart_in_head + count) < USART_MAX_REQUEST_SIZE) { - /* Copy all the bytes from DMA FIFO */ - memcpy(usart_in_buffer + usart_in_head, - src, count); - } - - /* - * Add incoming byte count to usart_in_head. - * Even if overflow bytes are not copied in buffer, maintain - * the overflow count so that packet can be dropped later in this - * function. - */ - usart_in_head += count; - - if (current_state == USART_HOST_CMD_READY_TO_RX) { - /* Kick deferred call to request timeout handler */ - hook_call_deferred(&usart_host_command_request_timeout_data, - USART_REQ_RX_TIMEOUT); - - /* Move current state to receiving */ - current_state = USART_HOST_CMD_RECEIVING; - } - - if (usart_in_head >= sizeof(struct ec_host_request)) { - /* Buffer has request header. Check header and get data_len */ - usart_in_datalen = host_request_expected_size(ec_request); - - if (usart_in_datalen == 0 || - usart_in_datalen > USART_MAX_REQUEST_SIZE) { - /* EC host request version not compatible or - * reserved byte is not zero. - */ - current_state = USART_HOST_CMD_RX_BAD; - } else if (usart_in_head == usart_in_datalen) { - /* - * Once all the datalen bytes are received, wait for - * USART_DEFERRED_PROCESS_REQ_TIMEOUT to call - * process_request function. This is to catch overrun - * bytes before processing the packet. - */ - hook_call_deferred( - &usart_host_command_process_request_data, - USART_DEFERRED_PROCESS_REQ_TIMEOUT); - - /* If no data in request, packet is complete */ - current_state = USART_HOST_CMD_COMPLETE; - } else if (usart_in_head > usart_in_datalen) { - /* Cancel deferred call to process_request */ - hook_call_deferred( - &usart_host_command_process_request_data, - -1); - - /* Move state to overrun*/ - current_state = USART_HOST_CMD_RX_OVERRUN; - } - } - - if (current_state == USART_HOST_CMD_PROCESSING) - /* Host should not send data before receiving a response. - * Since the request was already sent to host command task, - * just notify console about this. After response is sent - * dma will be cleared to handle next packet - */ - CPRINTS("USART HOST CMD ERROR: Contiguous packets detected."); - - /* Return count to show all incoming bytes were processed */ - return count; -} - -/* - * This function processes the outgoing bytes from tl usart. - */ -size_t usart_host_command_tx_remove_data(struct usart_config const *config, - uint8_t *dest) -{ - size_t bytes_remaining = 0; - - if (current_state == USART_HOST_CMD_SENDING && - usart_out_datalen != 0) { - /* Calculate byte_remaining in out_buffer */ - bytes_remaining = usart_out_datalen - usart_out_head; - - /* Get char on the head */ - *((uint8_t *) dest) = usart_out_buffer[usart_out_head++]; - - /* If no bytes remaining, reset layer to accept next - * request. - */ - if (bytes_remaining == 0) - usart_host_command_reset(); - } - - /* Return count of bytes remaining in out buffer */ - return bytes_remaining; -} - -/* - * Get protocol information - */ -enum ec_status usart_get_protocol_info(struct host_cmd_handler_args *args) -{ - struct ec_response_get_protocol_info *r = args->response; - - memset(r, 0, sizeof(*r)); - r->protocol_versions |= BIT(3); - r->max_request_packet_size = USART_MAX_REQUEST_SIZE; - r->max_response_packet_size = USART_MAX_RESPONSE_SIZE; - r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; - args->response_size = sizeof(*r); - - return EC_RES_SUCCESS; -} diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h deleted file mode 100644 index ee41d8a59b..0000000000 --- a/chip/stm32/usart_host_command.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USART_HOST_COMMAND_H -#define __CROS_EC_USART_HOST_COMMAND_H - -#include <stdarg.h> /* For va_list */ -#include "common.h" -#include "gpio.h" -#include "host_command.h" -#include "usart.h" - -/* - * Add data to host command layer buffer. - */ -size_t usart_host_command_rx_append_data(struct usart_config const *config, - const uint8_t *src, size_t count); - -/* - * Remove data from the host command layer buffer. - */ -size_t usart_host_command_tx_remove_data(struct usart_config const *config, - uint8_t *dest); - -/* - * Get USART protocol information. This function is called in runtime if - * board's host command transport is USART. - */ -enum ec_status usart_get_protocol_info(struct host_cmd_handler_args *args); - -/* - * Initialize USART host command layer. - */ -void usart_host_command_init(void); - -#endif /* __CROS_EC_USART_HOST_COMMAND_H */ diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c deleted file mode 100644 index 2649a97351..0000000000 --- a/chip/stm32/usart_info_command.c +++ /dev/null @@ -1,44 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Console command to query USART state - */ -#include "atomic.h" -#include "common.h" -#include "console.h" -#include "usart.h" - -static int command_usart_info(int argc, char **argv) -{ - struct usart_configs configs = usart_get_configs(); - size_t i; - - for (i = 0; i < configs.count; i++) { - struct usart_config const *config = configs.configs[i]; - - if (config == NULL) - continue; - - ccprintf( - "USART%d\n" - " dropped %d bytes\n" - " overran %d times\n", - config->hw->index + 1, - atomic_clear((uint32_t *)&(config->state->rx_dropped)), - atomic_clear((uint32_t *)&(config->state->rx_overrun))); - - if (config->rx->info) - config->rx->info(config); - - if (config->tx->info) - config->tx->info(config); - } - - return EC_SUCCESS; -} - -DECLARE_CONSOLE_COMMAND(usart_info, - command_usart_info, - NULL, - "Display USART info"); diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c deleted file mode 100644 index a185878261..0000000000 --- a/chip/stm32/usart_rx_dma.c +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "usart_rx_dma.h" - -#include "atomic.h" -#include "common.h" -#include "console.h" -#include "registers.h" -#include "system.h" -#include "usart_host_command.h" -#include "util.h" - -typedef size_t (*add_data_t)(struct usart_config const *config, - const uint8_t *src, size_t count); - -void usart_rx_dma_init(struct usart_config const *config) -{ - struct usart_rx_dma const *dma_config = - DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - - intptr_t base = config->hw->base; - - struct dma_option options = { - .channel = dma_config->channel, - .periph = (void *)&STM32_USART_RDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC), - }; - - if (IS_ENABLED(CHIP_FAMILY_STM32F4)) - options.flags |= STM32_DMA_CCR_CHANNEL(STM32_REQ_USART1_RX); - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; - STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR; - - dma_config->state->index = 0; - dma_config->state->max_bytes = 0; - - dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer); -} - -static void usart_rx_dma_interrupt_common( - struct usart_config const *config, - add_data_t add_data) -{ - struct usart_rx_dma const *dma_config = - DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - - dma_chan_t *channel = dma_get_channel(dma_config->channel); - size_t new_index = dma_bytes_done(channel, dma_config->fifo_size); - size_t old_index = dma_config->state->index; - size_t new_bytes = 0; - size_t added = 0; - - if (new_index > old_index) { - new_bytes = new_index - old_index; - - added = add_data(config, - dma_config->fifo_buffer + old_index, - new_bytes); - } else if (new_index < old_index) { - /* - * Handle the case where the received bytes are not contiguous - * in the circular DMA buffer. This is done with two queue - * adds. - */ - new_bytes = dma_config->fifo_size - (old_index - new_index); - - added = add_data(config, - dma_config->fifo_buffer + old_index, - dma_config->fifo_size - old_index) + - add_data(config, - dma_config->fifo_buffer, - new_index); - } else { - /* (new_index == old_index): nothing to add to the queue. */ - } - - atomic_add((uint32_t *)&(config->state->rx_dropped), new_bytes - added); - - if (dma_config->state->max_bytes < new_bytes) - dma_config->state->max_bytes = new_bytes; - - dma_config->state->index = new_index; -} - -static size_t queue_add(struct usart_config const *config, - const uint8_t *src, size_t count) -{ - return queue_add_units(config->producer.queue, (void *)src, count); -} - -void usart_rx_dma_interrupt(struct usart_config const *config) -{ - usart_rx_dma_interrupt_common(config, &queue_add); -} - - -#if defined(CONFIG_USART_HOST_COMMAND) -void usart_host_command_rx_dma_interrupt(struct usart_config const *config) -{ - usart_rx_dma_interrupt_common(config, - &usart_host_command_rx_append_data); -} -#endif /* CONFIG_USART_HOST_COMMAND */ - -void usart_rx_dma_info(struct usart_config const *config) -{ - struct usart_rx_dma const *dma_config = - DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - - ccprintf(" DMA RX max_bytes %d\n", - atomic_clear((uint32_t *)&dma_config->state->max_bytes)); -} diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h deleted file mode 100644 index 064ab8046c..0000000000 --- a/chip/stm32/usart_rx_dma.h +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Hybrid DMA/Interrupt based USART RX driver for STM32 - */ -#ifndef __CROS_EC_USART_RX_DMA_H -#define __CROS_EC_USART_RX_DMA_H - -#include "producer.h" -#include "dma.h" -#include "queue.h" -#include "usart.h" - -/* - * Only reference the usart_rx_dma_info function if CONFIG_CMD_USART_INFO - * is defined. This allows the compiler to remove this function as dead code - * when CONFIG_CMD_USART_INFO is not defined. - */ -#ifdef CONFIG_CMD_USART_INFO -#define USART_RX_DMA_INFO usart_rx_dma_info -#else -#define USART_RX_DMA_INFO NULL -#endif - -/* - * Construct a USART RX instance for DMA using the given DMA channel. - * - * This macro creates a new usart_rx_dma struct, complete with in RAM state, - * the contained usart_rx struct can be used in initializing a usart_config - * struct. - * - * CHANNEL is the DMA channel to be used for reception. This must be a valid - * DMA channel for the USART peripheral and any alternate channel mappings must - * be handled by the board specific code. - * - * FIFO_SIZE is the number of bytes (which does not need to be a power of two) - * to use for the DMA circular buffer. This buffer must be large enough to - * hide the worst case interrupt latency the system will encounter. The DMA - * RX driver adds to the output of the usart_info command a high water mark - * of how many bytes were transferred out of this FIFO on any one interrupt. - * This value can be used to correctly size the FIFO by setting the FIFO_SIZE - * to something large, stress test the USART, and run usart_info. After a - * reasonable stress test the "DMA RX max_bytes" value will be a reasonable - * size for the FIFO (perhaps +10% for safety). - */ -#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \ - ((struct usart_rx_dma const) { \ - .usart_rx = { \ - .producer_ops = { \ - .read = NULL, \ - }, \ - \ - .init = usart_rx_dma_init, \ - .interrupt = usart_rx_dma_interrupt, \ - .info = USART_RX_DMA_INFO, \ - }, \ - \ - .state = &((struct usart_rx_dma_state) {}), \ - .fifo_buffer = ((uint8_t[FIFO_SIZE]) {}), \ - .fifo_size = FIFO_SIZE, \ - .channel = CHANNEL, \ - }) - -/* - * In RAM state required to manage DMA based transmission. - */ -struct usart_rx_dma_state { - /* - * Previous value of dma_bytes_done. This will wrap when the DMA fills - * the queue. - */ - size_t index; - - /* - * Maximum number of bytes transferred in any one RX interrupt. - */ - uint32_t max_bytes; -}; - -/* - * Extension of the usart_rx struct to include required configuration for - * DMA based transmission. - */ -struct usart_rx_dma { - struct usart_rx usart_rx; - - struct usart_rx_dma_state volatile *state; - - uint8_t *fifo_buffer; - size_t fifo_size; - - enum dma_channel channel; -}; - -/* - * Function pointers needed to initialize a usart_rx struct. These shouldn't - * be called in any other context as they assume that the producer or config - * that they are passed was initialized with a complete usart_rx_dma struct. - */ -void usart_rx_dma_init(struct usart_config const *config); -void usart_rx_dma_interrupt(struct usart_config const *config); - -/* - * Function pointers needed to initialize host command rx dma interrupt. - * This should be only called from usart host command layer. - */ -void usart_host_command_rx_dma_interrupt(struct usart_config const *config); - -/* - * Debug function, used to print DMA RX statistics to the console. - */ -void usart_rx_dma_info(struct usart_config const *config); - -#endif /* __CROS_EC_USART_RX_DMA_H */ diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c deleted file mode 120000 index a756455f9b..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f0.c +++ /dev/null @@ -1 +0,0 @@ -usart_rx_interrupt.c
\ No newline at end of file diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c deleted file mode 120000 index a756455f9b..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -usart_rx_interrupt.c
\ No newline at end of file diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c deleted file mode 100644 index 198c6dd180..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* Copyright 2020 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART RX driver for STM32F0 and STM32F4 */ - -#include "usart.h" - -#include "atomic.h" -#include "common.h" -#include "queue.h" -#include "registers.h" - -static void usart_rx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) - STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; -#endif -} - -static void usart_rx_interrupt_handler(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); - - if (status & STM32_USART_SR_RXNE) { - uint8_t byte = STM32_USART_RDR(base); - - if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add((uint32_t *)&(config->state->rx_dropped), 1); - } -} - -struct usart_rx const usart_rx_interrupt = { - .producer_ops = { - /* - * Nothing to do here, we either had enough space in the queue - * when a character came in or we dropped it already. - */ - .read = NULL, - }, - - .init = usart_rx_init, - .interrupt = usart_rx_interrupt_handler, - .info = NULL, -}; diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c deleted file mode 100644 index 24ca7a0487..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32l.c +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART RX driver for STM32L */ - -#include "usart.h" - -#include "atomic.h" -#include "common.h" -#include "queue.h" -#include "registers.h" - -static void usart_rx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; -} - -static void usart_rx_interrupt_handler(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); - - /* - * We have to check and clear the overrun error flag on STM32L because - * we can't disable it. - */ - if (status & STM32_USART_SR_ORE) { - /* - * In the unlikely event that the overrun error bit was set but - * the RXNE bit was not (possibly because a read was done from - * RDR without first reading the status register) we do a read - * here to clear the overrun error bit. - */ - if (!(status & STM32_USART_SR_RXNE)) - (void)STM32_USART_RDR(config->hw->base); - - atomic_add((uint32_t *)&(config->state->rx_overrun), 1); - } - - if (status & STM32_USART_SR_RXNE) { - uint8_t byte = STM32_USART_RDR(base); - - if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add((uint32_t *)&(config->state->rx_dropped), 1); - } -} - -struct usart_rx const usart_rx_interrupt = { - .producer_ops = { - /* - * Nothing to do here, we either had enough space in the queue - * when a character came in or we dropped it already. - */ - .read = NULL, - }, - - .init = usart_rx_init, - .interrupt = usart_rx_interrupt_handler, - .info = NULL, -}; diff --git a/chip/stm32/usart_rx_interrupt-stm32l5.c b/chip/stm32/usart_rx_interrupt-stm32l5.c deleted file mode 100644 index fa644b6baf..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32l5.c +++ /dev/null @@ -1,6 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "usart_rx_interrupt-stm32l.c" diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c deleted file mode 100644 index 3bc30d4aaf..0000000000 --- a/chip/stm32/usart_rx_interrupt.c +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART RX driver for STM32F0 and STM32F3 */ - -#include "usart.h" - -#include "atomic.h" -#include "common.h" -#include "queue.h" -#include "registers.h" - -static void usart_rx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; - STM32_USART_CR1(base) |= STM32_USART_CR1_RE; - STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; -} - -static void usart_rx_interrupt_handler(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); - - if (status & STM32_USART_SR_RXNE) { - uint8_t byte = STM32_USART_RDR(base); - - if (!queue_add_unit(config->producer.queue, &byte)) - atomic_add((uint32_t *)&(config->state->rx_dropped), 1); - } -} - -struct usart_rx const usart_rx_interrupt = { - .producer_ops = { - /* - * Nothing to do here, we either had enough space in the queue - * when a character came in or we dropped it already. - */ - .read = NULL, - }, - - .init = usart_rx_init, - .interrupt = usart_rx_interrupt_handler, - .info = NULL, -}; diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c deleted file mode 100644 index 0c8e2c73d6..0000000000 --- a/chip/stm32/usart_tx_dma.c +++ /dev/null @@ -1,102 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#include "usart_tx_dma.h" - -#include "usart.h" -#include "common.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "util.h" - -void usart_tx_dma_written(struct consumer const *consumer, size_t count) -{ - struct usart_config const *config = - DOWNCAST(consumer, struct usart_config, consumer); - - task_trigger_irq(config->hw->irq); -} - -void usart_tx_dma_init(struct usart_config const *config) -{ - struct usart_tx_dma const *dma_config = - DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx); - - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_TE; - STM32_USART_CR3(base) |= STM32_USART_CR3_DMAT; - - dma_config->state->dma_active = 0; -} - -static void usart_tx_dma_start(struct usart_config const *config, - struct usart_tx_dma const *dma_config) -{ - struct usart_tx_dma_state volatile *state = dma_config->state; - intptr_t base = config->hw->base; - - struct dma_option options = { - .channel = dma_config->channel, - .periph = (void *)&STM32_USART_TDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT), - }; - - /* - * Limit our DMA transfer. If we didn't do this then it would be - * possible to start a large DMA transfer of an entirely full buffer - * that would hold up any additional writes to the TX queue - * unnecessarily. - */ - state->chunk.count = MIN(state->chunk.count, dma_config->max_bytes); - - dma_prepare_tx(&options, state->chunk.count, state->chunk.buffer); - - state->dma_active = 1; - - usart_clear_tc(config); - STM32_USART_CR1(base) |= STM32_USART_CR1_TCIE; - - dma_go(dma_get_channel(options.channel)); -} - -static void usart_tx_dma_stop(struct usart_config const *config, - struct usart_tx_dma const *dma_config) -{ - dma_config->state->dma_active = 0; - - STM32_USART_CR1(config->hw->base) &= ~STM32_USART_CR1_TCIE; -} - -void usart_tx_dma_interrupt(struct usart_config const *config) -{ - struct usart_tx_dma const *dma_config = - DOWNCAST(config->tx, struct usart_tx_dma const, usart_tx); - struct usart_tx_dma_state volatile *state = dma_config->state; - - /* - * If we have completed a DMA transaction, or if we haven't yet started - * one then we clean up and start one now. - */ - if ((STM32_USART_SR(config->hw->base) & STM32_USART_SR_TC) || - !state->dma_active) { - struct queue const *queue = config->consumer.queue; - - /* - * Only advance the queue head (indicating that we have read - * units from the queue if we had an active DMA transfer. - */ - if (state->dma_active) - queue_advance_head(queue, state->chunk.count); - - state->chunk = queue_get_read_chunk(queue); - - if (state->chunk.count) - usart_tx_dma_start(config, dma_config); - else - usart_tx_dma_stop(config, dma_config); - } -} diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h deleted file mode 100644 index c17164e04a..0000000000 --- a/chip/stm32/usart_tx_dma.h +++ /dev/null @@ -1,90 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * DMA based USART TX driver for STM32 - */ -#ifndef __CROS_EC_USART_TX_DMA_H -#define __CROS_EC_USART_TX_DMA_H - -#include "consumer.h" -#include "dma.h" -#include "queue.h" -#include "usart.h" - -/* - * Construct a USART TX instance for DMA using the given DMA channel. - * - * This macro creates a new usart_tx_dma struct, complete with in RAM state, - * the contained usart_tx struct can be used in initializing a usart_config - * struct. - * - * CHANNEL is the DMA channel to be used for transmission. This must be a - * valid DMA channel for the USART peripheral and any alternate channel - * mappings must be handled by the board specific code. - * - * MAX_BYTES is the maximum size in bytes of a single DMA transfer. This - * allows the board to tune how often the TX engine updates the queue state. - * A larger number here could cause the queue to appear full for longer than - * required because the queue isn't notified that it has been read from until - * after the DMA transfer completes. - */ -#define USART_TX_DMA(CHANNEL, MAX_BYTES) \ - ((struct usart_tx_dma const) { \ - .usart_tx = { \ - .consumer_ops = { \ - .written = usart_tx_dma_written,\ - }, \ - \ - .init = usart_tx_dma_init, \ - .interrupt = usart_tx_dma_interrupt, \ - .info = NULL, \ - }, \ - \ - .state = &((struct usart_tx_dma_state){}), \ - .channel = CHANNEL, \ - .max_bytes = MAX_BYTES, \ - }) - -/* - * In RAM state required to manage DMA based transmission. - */ -struct usart_tx_dma_state { - /* - * The current chunk of queue buffer being used for transmission. Once - * the transfer is complete, this is used to update the TX queue head - * pointer as well. - */ - struct queue_chunk chunk; - - /* - * Flag indicating whether a DMA transfer is currently active. - */ - int dma_active; -}; - -/* - * Extension of the usart_tx struct to include required configuration for - * DMA based transmission. - */ -struct usart_tx_dma { - struct usart_tx usart_tx; - - struct usart_tx_dma_state volatile *state; - - enum dma_channel channel; - - size_t max_bytes; -}; - -/* - * Function pointers needed to initialize a usart_tx struct. These shouldn't - * be called in any other context as they assume that the consumer or config - * that they are passed was initialized with a complete usart_tx_dma struct. - */ -void usart_tx_dma_written(struct consumer const *consumer, size_t count); -void usart_tx_dma_flush(struct consumer const *consumer); -void usart_tx_dma_init(struct usart_config const *config); -void usart_tx_dma_interrupt(struct usart_config const *config); - -#endif /* __CROS_EC_USART_TX_DMA_H */ diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c deleted file mode 100644 index d8d441ba1b..0000000000 --- a/chip/stm32/usart_tx_interrupt.c +++ /dev/null @@ -1,126 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Interrupt based USART TX driver for STM32 */ - -#include "usart.h" - -#include "common.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "usart_host_command.h" -#include "util.h" - -typedef size_t (*remove_data_t)(struct usart_config const *config, - uint8_t *dest); - -static void usart_tx_init(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - STM32_USART_CR1(base) |= STM32_USART_CR1_TE; -} - -static void usart_written(struct consumer const *consumer, size_t count) -{ - struct usart_config const *config = - DOWNCAST(consumer, struct usart_config, consumer); - - /* - * Enable USART interrupt. This causes the USART interrupt handler to - * start fetching from the TX queue if it wasn't already. - */ - if (count) - STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE; -} - -static void usart_tx_interrupt_handler_common( - struct usart_config const *config, - remove_data_t remove_data) -{ - intptr_t base = config->hw->base; - uint8_t byte; - - if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE)) - return; - - if (remove_data(config, &byte)) { - STM32_USART_TDR(base) = byte; - - /* - * Make sure the TXE interrupt is enabled and that we won't go - * into deep sleep. This invocation of the USART interrupt - * handler may have been manually triggered to start - * transmission. - */ - disable_sleep(SLEEP_MASK_UART); - - STM32_USART_CR1(base) |= STM32_USART_CR1_TXEIE; - } else { - /* - * The TX queue is empty, disable the TXE interrupt and enable - * deep sleep mode. The TXE interrupt will remain disabled - * until a write call happens. - */ - enable_sleep(SLEEP_MASK_UART); - - STM32_USART_CR1(base) &= ~STM32_USART_CR1_TXEIE; - } -} - -static size_t queue_remove(struct usart_config const *config, uint8_t *dest) -{ - return queue_remove_unit(config->consumer.queue, (void *) dest); -} - -static void usart_tx_interrupt_handler(struct usart_config const *config) -{ - usart_tx_interrupt_handler_common(config, &queue_remove); -} - -void usart_tx_start(struct usart_config const *config) -{ - intptr_t base = config->hw->base; - - /* If interrupt is already enabled, nothing to do */ - if (STM32_USART_CR1(base) & STM32_USART_CR1_TXEIE) - return; - - disable_sleep(SLEEP_MASK_UART); - STM32_USART_CR1(base) |= (STM32_USART_CR1_TXEIE); - - task_trigger_irq(config->hw->irq); -} - -struct usart_tx const usart_tx_interrupt = { - .consumer_ops = { - .written = usart_written, - }, - - .init = usart_tx_init, - .interrupt = usart_tx_interrupt_handler, - .info = NULL, -}; - -#if defined(CONFIG_USART_HOST_COMMAND) - -static void usart_host_command_tx_interrupt_handler( - struct usart_config const *config) -{ - usart_tx_interrupt_handler_common(config, - &usart_host_command_tx_remove_data); -} - -struct usart_tx const usart_host_command_tx_interrupt = { - .consumer_ops = { - .written = usart_written, - }, - - .init = usart_tx_init, - .interrupt = usart_host_command_tx_interrupt_handler, - .info = NULL, -}; -#endif /* CONFIG_USART_HOST_COMMAND */ diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c deleted file mode 100644 index 08c0a17455..0000000000 --- a/chip/stm32/usb-stm32f0.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32F0 Family specific USB functionality - */ - -#include "registers.h" -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - STM32_USB_BCDR |= BIT(15) /* DPPU */; -} - -void usb_disconnect(void) -{ - /* disable pull-up on DP to disconnect */ - STM32_USB_BCDR &= ~BIT(15) /* DPPU */; - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c deleted file mode 100644 index 2376d00b41..0000000000 --- a/chip/stm32/usb-stm32f3.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32F3 Family specific USB functionality - */ - -#include "usb-stm32f3.h" - -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - usb_board_connect(); -} - -void usb_disconnect(void) -{ - usb_board_disconnect(); - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h deleted file mode 100644 index 196c43a53a..0000000000 --- a/chip/stm32/usb-stm32f3.h +++ /dev/null @@ -1,17 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32F3 Family specific USB functionality - */ - -/* - * A device that uses an STM32F3 part will need to define these two functions - * which are used to connect and disconnect the device from the USB bus. This - * is usually accomplished by enabling a pullup on the DP USB line. The pullup - * should be enabled by default so that the STM32 will enumerate correctly in - * DFU mode (which doesn't know how to enable the DP pullup, so it assumes that - * the pullup is always there). - */ -void usb_board_connect(void); -void usb_board_disconnect(void); diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c deleted file mode 100644 index b4402f670d..0000000000 --- a/chip/stm32/usb-stm32g4.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32G4 Family specific USB functionality - */ - -#include "registers.h" -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - STM32_USB_BCDR |= STM32_USB_BCDR_DPPU; -} - -void usb_disconnect(void) -{ - /* disable pull-up on DP to disconnect */ - STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU; - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c deleted file mode 100644 index bb9838531b..0000000000 --- a/chip/stm32/usb-stm32l.c +++ /dev/null @@ -1,27 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * STM32L Family specific USB functionality - */ - -#include "registers.h" -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - STM32_SYSCFG_PMC |= 1; -} - -void usb_disconnect(void) -{ - /* disable pull-up on DP to disconnect */ - STM32_SYSCFG_PMC &= ~1; - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stm32l5.c b/chip/stm32/usb-stm32l5.c deleted file mode 100644 index 9eaa622815..0000000000 --- a/chip/stm32/usb-stm32l5.c +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "registers.h" -#include "system.h" -#include "usb_api.h" - -void usb_connect(void) -{ - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - STM32_USB_BCDR |= STM32_USB_BCDR_DPPU; -} - -void usb_disconnect(void) -{ - /* disable pull-up on DP to disconnect */ - STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU; - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c deleted file mode 100644 index 7429832f10..0000000000 --- a/chip/stm32/usb-stream.c +++ /dev/null @@ -1,180 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "common.h" -#include "config.h" -#include "link_defs.h" -#include "printf.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usart.h" -#include "usb_hw.h" -#include "usb-stream.h" - -static size_t rx_read(struct usb_stream_config const *config) -{ - uintptr_t address = btable_ep[config->endpoint].rx_addr; - size_t count = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK; - - /* - * Only read the received USB packet if there is enough space in the - * receive queue. - */ - if (count > queue_space(config->producer.queue)) - return 0; - - return queue_add_memcpy(config->producer.queue, - (void *) address, - count, - memcpy_from_usbram); -} - -static size_t tx_write(struct usb_stream_config const *config) -{ - uintptr_t address = btable_ep[config->endpoint].tx_addr; - size_t count = queue_remove_memcpy(config->consumer.queue, - (void *) address, - config->tx_size, - memcpy_to_usbram); - - btable_ep[config->endpoint].tx_count = count; - - return count; -} - -static int tx_valid(struct usb_stream_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) == EP_TX_VALID; -} - -static int rx_valid(struct usb_stream_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) == EP_RX_VALID; -} - -static int rx_disabled(struct usb_stream_config const *config) -{ - return config->state->rx_disabled; -} - -static void usb_read(struct producer const *producer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(producer, struct usb_stream_config, producer); - - hook_call_deferred(config->deferred, 0); -} - -static void usb_written(struct consumer const *consumer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(consumer, struct usb_stream_config, consumer); - - hook_call_deferred(config->deferred, 0); -} - -struct producer_ops const usb_stream_producer_ops = { - .read = usb_read, -}; - -struct consumer_ops const usb_stream_consumer_ops = { - .written = usb_written, -}; - -void usb_stream_deferred(struct usb_stream_config const *config) -{ - if (!tx_valid(config) && tx_write(config)) - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0); - - if (!rx_valid(config) && !rx_disabled(config) && rx_read(config)) - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); -} - -void usb_stream_tx(struct usb_stream_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, 0, 0, 0); - - hook_call_deferred(config->deferred, 0); -} - -void usb_stream_rx(struct usb_stream_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, 0, 0, 0); - - hook_call_deferred(config->deferred, 0); -} - -static usb_uint usb_ep_rx_size(size_t bytes) -{ - if (bytes < 64) - return bytes << 9; - else - return 0x8000 | ((bytes - 32) << 5); -} - -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt) -{ - int i; - - if (evt != USB_EVENT_RESET) - return; - - i = config->endpoint; - - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); - btable_ep[i].tx_count = 0; - - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); - btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size); - - config->state->rx_waiting = 0; - - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID)); -} - -int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, - usb_uint *rx_buf, usb_uint *tx_buf) -{ - struct usb_setup_packet req; - - usb_read_setup_packet(rx_buf, &req); - - if (req.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) - return -1; - - if (req.wIndex != interface || - req.wLength != 0) - return -1; - - switch (req.bRequest) { - /* Set parity. */ - case USB_USART_SET_PARITY: - usart_set_parity(usart, req.wValue); - break; - case USB_USART_SET_BAUD: - usart_set_baud(usart, req.wValue * 100); - break; - - /* TODO(nsanders): support reading parity. */ - /* TODO(nsanders): support reading baud. */ - default: - return -1; - } - - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT); - return 0; -} diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h deleted file mode 100644 index 915d8905cd..0000000000 --- a/chip/stm32/usb-stream.h +++ /dev/null @@ -1,301 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_STREAM_H -#define __CROS_EC_USB_STREAM_H - -#if defined(CHIP_FAMILY_STM32F4) -#include "usb_dwc_stream.h" -#else - -/* STM32 USB STREAM driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "consumer.h" -#include "hooks.h" -#include "producer.h" -#include "queue.h" -#include "usart.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -#include <stdint.h> - -/* - * Per-USB stream state stored in RAM. Zero initialization of this structure - * by the BSS initialization leaves it in a valid and correctly initialized - * state, so there is no need currently for a usb_stream_init style function. - */ -struct usb_stream_state { - /* - * Flag indicating that there is a full RX buffer in the USB packet RAM - * that we were not able to move into the RX queue because there was - * not enough room when the packet was initially received. The - * producer read operation checks this flag so that once there is - * room in the queue it can copy the RX buffer into the queue and - * restart USB reception by marking the RX buffer as VALID. - */ - int rx_waiting; - /* - * Flag indicating that the incoming data on the USB link are discarded. - */ - int rx_disabled; -}; - -/* - * Compile time Per-USB stream configuration stored in flash. Instances of this - * structure are provided by the user of the USB stream. This structure binds - * together all information required to operate a USB stream. - */ -struct usb_stream_config { - /* - * Pointer to usb_stream_state structure. The state structure - * maintains per USB stream information. - */ - struct usb_stream_state volatile *state; - - /* - * Endpoint index, and pointers to the USB packet RAM buffers. - */ - int endpoint; - - /* - * Deferred function to call to handle USB and Queue request. - */ - const struct deferred_data *deferred; - - size_t rx_size; - size_t tx_size; - - usb_uint *rx_ram; - usb_uint *tx_ram; - - struct consumer consumer; - struct producer producer; -}; - -/* - * These function tables are defined by the USB Stream driver and are used to - * initialize the consumer and producer in the usb_stream_config. - */ -extern struct consumer_ops const usb_stream_consumer_ops; -extern struct producer_ops const usb_stream_producer_ops; - -/* - * Convenience macro for defining USB streams and their associated state and - * buffers. - * - * NAME is used to construct the names of the packet RAM buffers, trampoline - * functions, usb_stream_state struct, and usb_stream_config struct, the - * latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * stream. - * - * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the - * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields - * respectively in the USB interface descriptor. - * - * INTERFACE_NAME is the index of the USB string descriptor (iInterface). - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - * - * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate - * for the RX and TX packets respectively. The valid values for these - * parameters are dictated by the USB peripheral. - * - * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver - * should write to and read from respectively. - */ -/* - * The following assertions can not be made because they require access to - * non-const fields, but should be kept in mind. - * - * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE); - * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE); - * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); - * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); - */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(RX_SIZE > 0); \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) || \ - (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0)); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \ - static struct usb_stream_state CONCAT2(NAME, _state); \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - struct usb_stream_config const NAME = { \ - .state = &CONCAT2(NAME, _state), \ - .endpoint = ENDPOINT, \ - .deferred = &CONCAT2(NAME, _deferred__data), \ - .rx_size = RX_SIZE, \ - .tx_size = TX_SIZE, \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &usb_stream_consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &usb_stream_producer_ops, \ - }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_stream_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_stream_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_stream_deferred(&NAME); } - -/* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) - -/* Declare a utility interface for setting parity/baud. */ -#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG) \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \ - rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)) - -/* This is a medium version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG_USART_IFACE(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE, \ - USART_CFG) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE); \ - USB_USART_IFACE(NAME, INTERFACE, USART_CFG) - -/* - * Handle USB and Queue request in a deferred callback. - */ -void usb_stream_deferred(struct usb_stream_config const *config); - -/* - * Handle control interface requests. - */ -enum usb_usart { - USB_USART_REQ_PARITY = 0, - USB_USART_SET_PARITY = 1, - USB_USART_REQ_BAUD = 2, - USB_USART_SET_BAUD = 3, -}; - -/* - * baud rate is req/set in multiples of 100, to avoid overflowing - * 16-bit integer. - */ -#define USB_USART_BAUD_MULTIPLIER 100 - -int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, usb_uint *rx_buf, usb_uint *tx_buf); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB stream driver. - */ -void usb_stream_tx(struct usb_stream_config const *config); -void usb_stream_rx(struct usb_stream_config const *config); -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt); - -#endif /* defined(CHIP_FAMILY_STM32F4) */ -#endif /* __CROS_EC_USB_STREAM_H */ diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c deleted file mode 100644 index 0077815a27..0000000000 --- a/chip/stm32/usb.c +++ /dev/null @@ -1,957 +0,0 @@ -/* Copyright 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "flash.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -#ifdef CONFIG_USB_BOS -/* v2.10 (vs 2.00) BOS Descriptor provided */ -#define USB_DEV_BCDUSB 0x0210 -#else -#define USB_DEV_BCDUSB 0x0200 -#endif - -#ifndef USB_DEV_CLASS -#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE -#endif - -#ifndef CONFIG_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ -#endif - -#ifndef CONFIG_USB_SERIALNO -#define USB_STR_SERIALNO 0 -#else -static int usb_load_serial(void); -#endif - -#define USB_RESUME_TIMEOUT_MS 3000 - -/* USB Standard Device Descriptor */ -static const struct usb_device_descriptor dev_desc = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = USB_DEV_BCDUSB, - .bDeviceClass = USB_DEV_CLASS, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = USB_MAX_PACKET_SIZE, - .idVendor = CONFIG_USB_VID, - .idProduct = CONFIG_USB_PID, - .bcdDevice = CONFIG_USB_BCD_DEV, - .iManufacturer = USB_STR_VENDOR, - .iProduct = USB_STR_PRODUCT, - .iSerialNumber = USB_STR_SERIALNO, - .bNumConfigurations = 1 -}; - -/* USB Configuration Descriptor */ -const struct usb_config_descriptor USB_CONF_DESC(conf) = { - .bLength = USB_DT_CONFIG_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0x0BAD, /* no of returned bytes, set at runtime */ - .bNumInterfaces = USB_IFACE_COUNT, - .bConfigurationValue = 1, - .iConfiguration = USB_STR_VERSION, - .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 -#endif -#ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 -#endif - , - .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), -}; - -const uint8_t usb_string_desc[] = { - 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ -}; - -/* Endpoint table in USB controller RAM */ -struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable; -/* Control endpoint (EP0) buffers */ -static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; -static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; - -#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx)) - -static int set_addr; -/* remaining size of descriptor data to transfer */ -static int desc_left; -/* pointer to descriptor data if any */ -static const uint8_t *desc_ptr; -/* interface that should handle the next tx transaction */ -static uint8_t iface_next = USB_IFACE_COUNT; -#ifdef CONFIG_USB_REMOTE_WAKEUP -/* remote wake up feature enabled */ -static int remote_wakeup_enabled; -#endif - -void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet) -{ - packet->bmRequestType = buffer[0] & 0xff; - packet->bRequest = buffer[0] >> 8; - packet->wValue = buffer[1]; - packet->wIndex = buffer[2]; - packet->wLength = buffer[3]; -} - -struct usb_descriptor_patch { - const void *address; - uint16_t data; -}; - -static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT]; - -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data) -{ - desc_patches[type].address = address; - desc_patches[type].data = data; -} - -void *memcpy_to_usbram_ep0_patch(const void *src, size_t n) -{ - int i; - void *ret; - - ret = memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), src, n); - - for (i = 0; i < USB_DESC_PATCH_COUNT; i++) { - unsigned int offset = desc_patches[i].address - src; - - if (offset >= n) - continue; - - memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset), - &desc_patches[i].data, sizeof(desc_patches[i].data)); - } - - return ret; -} - -static void ep0_send_descriptor(const uint8_t *desc, int len, - uint16_t fixup_size) -{ - /* do not send more than what the host asked for */ - len = MIN(ep0_buf_rx[3], len); - /* - * if we cannot transmit everything at once, - * keep the remainder for the next IN packet - */ - if (len >= USB_MAX_PACKET_SIZE) { - desc_left = len - USB_MAX_PACKET_SIZE; - desc_ptr = desc + USB_MAX_PACKET_SIZE; - len = USB_MAX_PACKET_SIZE; - } - memcpy_to_usbram_ep0_patch(desc, len); - if (fixup_size) /* set the real descriptor size */ - ep0_buf_tx[1] = fixup_size; - btable_ep[0].tx_count = len; - /* send the null OUT transaction if the transfer is complete */ - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - desc_left ? 0 : EP_STATUS_OUT); -} - -/* Requests on the control endpoint (aka EP0) */ -static void ep0_rx(void) -{ - uint16_t req = ep0_buf_rx[0]; /* bRequestType | bRequest */ - - /* reset any incomplete descriptor transfer */ - desc_ptr = NULL; - iface_next = USB_IFACE_COUNT; - - /* interface specific requests */ - if ((req & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { - uint8_t iface = ep0_buf_rx[2] & 0xff; - if (iface < USB_IFACE_COUNT) { - int ret; - - ret = usb_iface_request[iface](ep0_buf_rx, ep0_buf_tx); - if (ret < 0) - goto unknown_req; - if (ret == 1) - iface_next = iface; - return; - } - } - /* vendor specific request */ - if ((req & USB_TYPE_MASK) == USB_TYPE_VENDOR) { -#ifdef CONFIG_WEBUSB_URL - uint8_t b_req = req >> 8; /* bRequest in the transfer */ - uint16_t idx = ep0_buf_rx[2]; /* wIndex in the transfer */ - - if (b_req == 0x01 && idx == WEBUSB_REQ_GET_URL) { - int len = *(uint8_t *)webusb_url; - - ep0_send_descriptor(webusb_url, len, 0); - return; - } -#endif - goto unknown_req; - } - - /* TODO check setup bit ? */ - if (req == (USB_DIR_IN | (USB_REQ_GET_DESCRIPTOR << 8))) { - uint8_t type = ep0_buf_rx[1] >> 8; - uint8_t idx = ep0_buf_rx[1] & 0xff; - const uint8_t *desc; - int len; - - switch (type) { - case USB_DT_DEVICE: /* Setup : Get device descriptor */ - desc = (void *)&dev_desc; - len = sizeof(dev_desc); - break; - case USB_DT_CONFIGURATION: /* Setup : Get configuration desc */ - desc = __usb_desc; - len = USB_DESC_SIZE; - break; -#ifdef CONFIG_USB_BOS - case USB_DT_BOS: /* Setup : Get BOS descriptor */ - desc = bos_ctx.descp; - len = bos_ctx.size; - break; -#endif - case USB_DT_STRING: /* Setup : Get string descriptor */ - if (idx >= USB_STR_COUNT) - /* The string does not exist : STALL */ - goto unknown_req; -#ifdef CONFIG_USB_SERIALNO - if (idx == USB_STR_SERIALNO) - desc = (uint8_t *)usb_serialno_desc; - else -#endif - desc = usb_strings[idx]; - len = desc[0]; - break; - case USB_DT_DEVICE_QUALIFIER: /* Get device qualifier desc */ - /* Not high speed : STALL next IN used as handshake */ - goto unknown_req; - default: /* unhandled descriptor */ - goto unknown_req; - } - ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ? - USB_DESC_SIZE : 0); - } else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) { - uint16_t data = 0; - /* Get status */ -#ifdef CONFIG_USB_SELF_POWERED - data |= USB_REQ_GET_STATUS_SELF_POWERED; -#endif -#ifdef CONFIG_USB_REMOTE_WAKEUP - if (remote_wakeup_enabled) - data |= USB_REQ_GET_STATUS_REMOTE_WAKEUP; -#endif - memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2); - btable_ep[0].tx_count = 2; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - EP_STATUS_OUT /*null OUT transaction */); - } else if ((req & 0xff) == USB_DIR_OUT) { - switch (req >> 8) { - case USB_REQ_SET_FEATURE: - case USB_REQ_CLEAR_FEATURE: -#ifdef CONFIG_USB_REMOTE_WAKEUP - if (ep0_buf_rx[1] == - USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) { - remote_wakeup_enabled = - ((req >> 8) == USB_REQ_SET_FEATURE); - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, - EP_TX_RX_VALID, 0); - break; - } -#endif - goto unknown_req; - case USB_REQ_SET_ADDRESS: - /* set the address after we got IN packet handshake */ - set_addr = ep0_buf_rx[1] & 0xff; - /* need null IN transaction -> TX Valid */ - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - break; - case USB_REQ_SET_CONFIGURATION: - /* uint8_t cfg = ep0_buf_rx[1] & 0xff; */ - /* null IN for handshake */ - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - break; - default: /* unhandled request */ - goto unknown_req; - } - - } else { - goto unknown_req; - } - - return; -unknown_req: - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_RX_VALID | EP_TX_STALL, 0); -} - -static void ep0_tx(void) -{ - if (set_addr) { - STM32_USB_DADDR = set_addr | 0x80; - set_addr = 0; - CPRINTF("SETAD %02x\n", STM32_USB_DADDR); - } - if (desc_ptr) { - /* we have an on-going descriptor transfer */ - int len = MIN(desc_left, USB_MAX_PACKET_SIZE); - memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, desc_ptr, len); - btable_ep[0].tx_count = len; - desc_left -= len; - desc_ptr += len; - STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, - desc_left ? 0 : EP_STATUS_OUT); - /* send the null OUT transaction if the transfer is complete */ - return; - } - if (iface_next < USB_IFACE_COUNT) { - int ret; - - ret = usb_iface_request[iface_next](NULL, ep0_buf_tx); - if (ret < 0) - goto error; - if (ret == 0) - iface_next = USB_IFACE_COUNT; - return; - } - -error: - STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, 0); -} - -static void ep0_event(enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - STM32_USB_EP(0) = BIT(9) /* control EP */ | - (2 << 4) /* TX NAK */ | - (3 << 12) /* RX VALID */; - - btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx); - btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx); - btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10); - btable_ep[0].tx_count = 0; -} -USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event); - -static void usb_reset(void) -{ - int ep; - - for (ep = 0; ep < USB_EP_COUNT; ep++) - usb_ep_event[ep](USB_EVENT_RESET); - - /* - * set the default address : 0 - * as we are not configured yet - */ - STM32_USB_DADDR = 0 | 0x80; - CPRINTF("RST EP0 %04x\n", STM32_USB_EP(0)); -} - -#ifdef CONFIG_USB_SUSPEND -static void usb_pm_change_notify_hooks(void) -{ - hook_notify(HOOK_USB_PM_CHANGE); -} -DECLARE_DEFERRED(usb_pm_change_notify_hooks); - -/* See RM0091 Reference Manual 30.5.5 Suspend/Resume events */ -static void usb_suspend(void) -{ - CPRINTF("SUS%d\n", remote_wakeup_enabled); - - /* - * usb_suspend can be called from hook task, make sure no interrupt is - * modifying CNTR at the same time. - */ - interrupt_disable(); - /* Set FSUSP bit to activate suspend mode */ - STM32_USB_CNTR |= STM32_USB_CNTR_FSUSP; - - /* Set USB low power mode */ - STM32_USB_CNTR |= STM32_USB_CNTR_LP_MODE; - interrupt_enable(); - - clock_enable_module(MODULE_USB, 0); - - /* USB is not in use anymore, we can (hopefully) sleep now. */ - enable_sleep(SLEEP_MASK_USB_DEVICE); - - hook_call_deferred(&usb_pm_change_notify_hooks_data, 0); -} - -/* - * SOF was received (set in interrupt), reset in usb_resume in the - * unexpected state case. - */ -static volatile int sof_received; - -static void usb_resume_deferred(void) -{ - uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; - - CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received); - if (sof_received == 0 && (state == 2 || state == 3)) - usb_suspend(); - else - hook_call_deferred(&usb_pm_change_notify_hooks_data, 0); -} -DECLARE_DEFERRED(usb_resume_deferred); - -static void usb_resume(void) -{ - uint32_t state; - - clock_enable_module(MODULE_USB, 1); - - /* Clear FSUSP bit to exit suspend mode */ - STM32_USB_CNTR &= ~STM32_USB_CNTR_FSUSP; - - /* USB is in use again */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; - - CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR); - - /* - * Reference manual tells we should go back to sleep if state is 10 or - * 11. However, setting FSUSP and LP_MODE in this interrupt routine - * seems to lock the USB controller (see b/35775088 and b/71688150). - * Instead, we do it in a deferred routine. The host must assert the - * reset condition for 20ms, so reading D+/D- after ~3ms should be safe - * (there is no chance we end up sampling during a bus transaction). - */ - if (state == 2 || state == 3) { - /* - * This function is already called from interrupt context so - * there is no risk of race here. - */ - sof_received = 0; - STM32_USB_CNTR |= STM32_USB_CNTR_SOFM; - hook_call_deferred(&usb_resume_deferred_data, 3 * MSEC); - } else { - hook_call_deferred(&usb_pm_change_notify_hooks_data, 0); - } -} - -#ifdef CONFIG_USB_REMOTE_WAKEUP -/* - * Makes sure usb_wake is only run once. When 0, wake is in progress. - */ -static volatile int usb_wake_done = 1; - -/* - * ESOF counter (incremented in interrupt), RESUME bit is cleared when - * this reaches 0. Also used to detect resume timeout. - */ -static volatile int esof_count; - -__attribute__((weak)) -void board_usb_wake(void) -{ - /* Side-band USB wake, do nothing by default. */ -} - -/* Called 10ms after usb_wake started. */ -static void usb_wake_deferred(void) -{ - if (esof_count == 3) { - /* - * If we reach here, it means that we are not counting ESOF/SOF - * properly (either of these interrupts should occur every 1ms). - * This should never happen if we implemented the resume logic - * correctly. - * - * We reset the controller in that case, which recovers the - * interface. - */ - CPRINTF("USB stuck\n"); -#if defined(STM32_RCC_APB1RSTR2_USBFSRST) - STM32_RCC_APB1RSTR2 |= STM32_RCC_APB1RSTR2_USBFSRST; - STM32_RCC_APB1RSTR2 &= STM32_RCC_APB1RSTR2_USBFSRST; -#else - STM32_RCC_APB1RSTR |= STM32_RCC_PB1_USB; - STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_USB; -#endif - usb_init(); - } -} -DECLARE_DEFERRED(usb_wake_deferred); - -void usb_wake(void) -{ - if (!remote_wakeup_enabled || - !(STM32_USB_CNTR & STM32_USB_CNTR_FSUSP)) { - /* - * USB wake not enabled, or already woken up, or already waking - * up, nothing to do. - */ - return; - } - - /* Only allow one caller at a time. */ - if (!atomic_clear((int *)&usb_wake_done)) - return; - - CPRINTF("WAKE\n"); - - /* - * Sometimes the USB controller gets stuck, and does not count SOF/ESOF - * frames anymore, detect that. - */ - hook_call_deferred(&usb_wake_deferred_data, 10 * MSEC); - - /* - * Set RESUME bit for 1 to 15 ms, then clear it. We ask the interrupt - * routine to count 3 ESOF interrupts, which should take between - * 2 and 3 ms. - */ - esof_count = 3; - - /* STM32_USB_CNTR can also be updated from interrupt context. */ - interrupt_disable(); - STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | - STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM; - interrupt_enable(); - - /* Try side-band wake as well. */ - board_usb_wake(); -} -#endif - -int usb_is_suspended(void) -{ - /* Either hardware block is suspended... */ - if (STM32_USB_CNTR & STM32_USB_CNTR_FSUSP) - return 1; - -#ifdef CONFIG_USB_REMOTE_WAKEUP - /* ... or we are currently waking up. */ - if (!usb_wake_done) - return 1; -#endif - - return 0; -} - -int usb_is_remote_wakeup_enabled(void) -{ -#ifdef CONFIG_USB_REMOTE_WAKEUP - return remote_wakeup_enabled; -#else - return 0; -#endif -} -#endif /* CONFIG_USB_SUSPEND */ - -#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_USB_REMOTE_WAKEUP) -/* - * Called by usb_interrupt when usb_wake is asking us to count esof_count ESOF - * interrupts (one per millisecond), then disable RESUME, then wait for resume - * to complete. - */ -static void usb_interrupt_handle_wake(uint16_t status) -{ - int state; - int good; - - esof_count--; - - /* Keep counting. */ - if (esof_count > 0) - return; - - /* Clear RESUME bit. */ - if (esof_count == 0) - STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME; - - /* Then count down until state is resumed. */ - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; - - /* - * state 2, or receiving an SOF, means resume - * completed successfully. - */ - good = (status & STM32_USB_ISTR_SOF) || (state == 2); - - /* Either: state is ready, or we timed out. */ - if (good || state == 3 || esof_count <= -USB_RESUME_TIMEOUT_MS) { - int ep; - - STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM; - usb_wake_done = 1; - if (!good) { - CPRINTF("wake error: cnt=%d state=%d\n", - esof_count, state); - usb_suspend(); - return; - } - - CPRINTF("RSMOK%d %d\n", -esof_count, state); - - for (ep = 1; ep < USB_EP_COUNT; ep++) - usb_ep_event[ep](USB_EVENT_DEVICE_RESUME); - } -} -#endif /* CONFIG_USB_SUSPEND && CONFIG_USB_REMOTE_WAKEUP */ - -void usb_interrupt(void) -{ - uint16_t status = STM32_USB_ISTR; - - if (status & STM32_USB_ISTR_RESET) - usb_reset(); - -#ifdef CONFIG_USB_SUSPEND - if (status & STM32_USB_ISTR_SOF) { - sof_received = 1; - /* - * The wake handler also only cares about the _first_ SOF that - * is received, so we can disable that interrupt. - */ - STM32_USB_CNTR &= ~STM32_USB_CNTR_SOFM; - } - -#ifdef CONFIG_USB_REMOTE_WAKEUP - if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) && - !usb_wake_done) - usb_interrupt_handle_wake(status); -#endif - - if (status & STM32_USB_ISTR_SUSP) - usb_suspend(); - - if (status & STM32_USB_ISTR_WKUP) - usb_resume(); -#endif - - if (status & STM32_USB_ISTR_CTR) { - int ep = status & STM32_USB_ISTR_EP_ID_MASK; - if (ep < USB_EP_COUNT) { - if (status & STM32_USB_ISTR_DIR) - usb_ep_rx[ep](); - else - usb_ep_tx[ep](); - } - /* TODO: do it in a USB task */ - /* task_set_event(, 1 << ep_task); */ - } - - /* ack only interrupts that we handled */ - STM32_USB_ISTR = ~status; -} -DECLARE_IRQ(STM32_IRQ_USB_LP, usb_interrupt, 1); - -void usb_init(void) -{ - /* Enable USB device clock, possibly increasing system clock to 48MHz */ - clock_enable_module(MODULE_USB, 1); - - /* configure the pinmux */ - gpio_config_module(MODULE_USB, 1); - - /* power on sequence */ - - /* keep FRES (USB reset) and remove PDWN (power down) */ - STM32_USB_CNTR = STM32_USB_CNTR_FRES; - udelay(1); /* startup time */ - /* reset FRES and keep interrupts masked */ - STM32_USB_CNTR = 0x00; - /* clear pending interrupts */ - STM32_USB_ISTR = 0; - - /* set descriptors table offset in dedicated SRAM */ - STM32_USB_BTABLE = 0; - - /* EXTI18 is USB wake up interrupt */ - /* STM32_EXTI_RTSR |= BIT(18); */ - /* STM32_EXTI_IMR |= BIT(18); */ - - /* Enable interrupt handlers */ - task_enable_irq(STM32_IRQ_USB_LP); - /* set interrupts mask : reset/correct transfer/errors */ - STM32_USB_CNTR = STM32_USB_CNTR_CTRM | - STM32_USB_CNTR_PMAOVRM | - STM32_USB_CNTR_ERRM | -#ifdef CONFIG_USB_SUSPEND - STM32_USB_CNTR_WKUPM | - STM32_USB_CNTR_SUSPM | -#endif - STM32_USB_CNTR_RESETM; - -#ifdef CONFIG_USB_SERIALNO - usb_load_serial(); -#endif -#ifndef CONFIG_USB_INHIBIT_CONNECT - usb_connect(); -#endif - - CPRINTF("USB init done\n"); -} - -#ifndef CONFIG_USB_INHIBIT_INIT -DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT); -#endif - -void usb_release(void) -{ - /* signal disconnect to host */ - usb_disconnect(); - - /* power down USB */ - STM32_USB_CNTR = 0; - - /* disable interrupt handlers */ - task_disable_irq(STM32_IRQ_USB_LP); - - /* unset pinmux */ - gpio_config_module(MODULE_USB, 0); - - /* disable USB device clock, possibly slowing down system clock */ - clock_enable_module(MODULE_USB, 0); -} -/* ensure the host disconnects and reconnects over a sysjump */ -DECLARE_HOOK(HOOK_SYSJUMP, usb_release, HOOK_PRIO_DEFAULT); - -int usb_is_enabled(void) -{ - return clock_is_module_enabled(MODULE_USB); -} - -void *memcpy_to_usbram(void *dest, const void *src, size_t n) -{ - int unaligned = (((uintptr_t) dest) & 1); - usb_uint *d = &__usb_ram_start[((uintptr_t) dest) / 2]; - uint8_t *s = (uint8_t *) src; - int i; - - /* - * Handle unaligned leading byte via read/modify/write. - */ - if (unaligned && n) { - *d = (*d & ~0xff00) | (*s << 8); - n--; - s++; - d++; - } - - for (i = 0; i < n / 2; i++, s += 2) - *d++ = (s[1] << 8) | s[0]; - - /* - * There is a trailing byte to write into a final USB packet memory - * location, use a read/modify/write to be safe. - */ - if (n & 1) - *d = (*d & ~0x00ff) | *s; - - return dest; -} - -void *memcpy_from_usbram(void *dest, const void *src, size_t n) -{ - int unaligned = (((uintptr_t) src) & 1); - usb_uint const *s = &__usb_ram_start[((uintptr_t) src) / 2]; - uint8_t *d = (uint8_t *) dest; - int i; - - if (unaligned && n) { - *d = *s >> 8; - n--; - s++; - d++; - } - - for (i = 0; i < n / 2; i++) { - usb_uint value = *s++; - - *d++ = (value >> 0) & 0xff; - *d++ = (value >> 8) & 0xff; - } - - if (n & 1) - *d = *s; - - return dest; -} - -#ifdef CONFIG_USB_SERIALNO -/* This will be subbed into USB_STR_SERIALNO. */ -struct usb_string_desc *usb_serialno_desc = - USB_WR_STRING_DESC(DEFAULT_SERIALNO); - -/* Update serial number */ -static int usb_set_serial(const char *serialno) -{ - struct usb_string_desc *sd = usb_serialno_desc; - int i; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Convert into unicode usb string desc. */ - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) { - sd->_data[i] = serialno[i]; - if (serialno[i] == 0) - break; - } - /* Count wchars (w/o null terminator) plus size & type bytes. */ - sd->_len = (i * 2) + 2; - sd->_type = USB_DT_STRING; - - return EC_SUCCESS; -} - -/* Retrieve serial number from pstate flash. */ -static int usb_load_serial(void) -{ - const char *serialno; - int rv; - - serialno = board_read_serial(); - if (!serialno) - return EC_ERROR_ACCESS_DENIED; - - rv = usb_set_serial(serialno); - return rv; -} - -/* Save serial number into pstate region. */ -static int usb_save_serial(const char *serialno) -{ - int rv; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Save this new serial number to flash. */ - rv = board_write_serial(serialno); - if (rv) - return rv; - - /* Load this new serial number to memory. */ - rv = usb_load_serial(); - return rv; -} - -static int command_serialno(int argc, char **argv) -{ - struct usb_string_desc *sd = usb_serialno_desc; - char buf[CONFIG_SERIALNO_LEN]; - int rv = EC_SUCCESS; - int i; - - if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { - ccprintf("Saving serial number\n"); - rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { - ccprintf("Loading serial number\n"); - rv = usb_load_serial(); - } else - return EC_ERROR_INVAL; - } - - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) - buf[i] = sd->_data[i]; - ccprintf("Serial number: %s\n", buf); - return rv; -} - -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); - -#endif /* CONFIG_USB_SERIALNO */ - -#ifdef CONFIG_MAC_ADDR - -/* Save MAC address into pstate region. */ -static int usb_save_mac_addr(const char *mac_addr) -{ - int rv; - - if (!mac_addr) { - return EC_ERROR_INVAL; - } - - /* Save this new MAC address to flash. */ - rv = board_write_mac_addr(mac_addr); - if (rv) { - return rv; - } - - /* Load this new MAC address to memory. */ - if (board_read_mac_addr() != NULL) { - return EC_SUCCESS; - } else { - return EC_ERROR_UNKNOWN; - } -} - -static int command_macaddr(int argc, char **argv) -{ - const char* buf; - int rv = EC_SUCCESS; - - if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { - ccprintf("Saving MAC address\n"); - rv = usb_save_mac_addr(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { - ccprintf("Loading MAC address\n"); - } else { - return EC_ERROR_INVAL; - } - } - - buf = board_read_mac_addr(); - if (buf == NULL) { - buf = DEFAULT_MAC_ADDR; - } - ccprintf("MAC address: %s\n", buf); - return rv; -} - -DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, - "load/set [value]", - "Read and write MAC address"); - -#endif /* CONFIG_MAC_ADDR */ diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c deleted file mode 100644 index b5666c8fbf..0000000000 --- a/chip/stm32/usb_console.c +++ /dev/null @@ -1,279 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "config.h" -#include "console.h" -#include "link_defs.h" -#include "printf.h" -#include "queue.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define USB_CONSOLE_TIMEOUT_US (30 * MSEC) - -static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, - uint8_t); -static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); - -static int last_tx_ok = 1; - -static int is_reset; -static int is_enabled = 1; -static int is_readonly; - -/* USB-Serial descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10 -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 -}; - -static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; -static usb_uint ep_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; - -/* Forward declaration */ -static void handle_output(void); - -static void con_ep_tx(void) -{ - /* clear IT */ - STM32_TOGGLE_EP(USB_EP_CONSOLE, 0, 0, 0); - - /* Check bytes in the FIFO needed to transmitted */ - handle_output(); -} - -static void con_ep_rx(void) -{ - int i; - - for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK); - i++) { - int val = ((i & 1) ? - (ep_buf_rx[i >> 1] >> 8) : - (ep_buf_rx[i >> 1] & 0xff)); - - QUEUE_ADD_UNITS(&rx_q, &val, 1); - } - - /* clear IT */ - STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_RX_MASK, EP_RX_VALID, 0); - - /* wake-up the console task */ - console_has_input(); -} - -static void ep_event(enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx); - btable_ep[USB_EP_CONSOLE].tx_count = 0; - - btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx); - btable_ep[USB_EP_CONSOLE].rx_count = - 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - - STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (is_readonly ? EP_RX_NAK - : EP_RX_VALID)); - - is_reset = 1; -} - -USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event); - -static int __tx_char(void *context, int c) -{ - /* Do newline to CRLF translation */ - if (c == '\n' && __tx_char(context, '\r')) - return 1; - - /* Return 0 on success */ - return !QUEUE_ADD_UNITS(&tx_q, &c, 1); -} - -static void usb_enable_tx(int len) -{ - if (!is_enabled) - return; - - btable_ep[USB_EP_CONSOLE].tx_count = len; - STM32_TOGGLE_EP(USB_EP_CONSOLE, EP_TX_MASK, EP_TX_VALID, 0); -} - -static inline int usb_console_tx_valid(void) -{ - return (STM32_USB_EP(USB_EP_CONSOLE) & EP_TX_MASK) == EP_TX_VALID; -} - -static int usb_wait_console(void) -{ - timestamp_t deadline = get_time(); - int wait_time_us = 1; - - if (!is_enabled || !usb_is_enabled()) - return EC_SUCCESS; - - deadline.val += USB_CONSOLE_TIMEOUT_US; - - /* - * If the USB console is not used, Tx buffer would never free up. - * In this case, let's drop characters immediately instead of sitting - * for some time just to time out. On the other hand, if the last - * Tx is good, it's likely the host is there to receive data, and - * we should wait so that we don't clobber the buffer. - */ - if (last_tx_ok) { - while (usb_console_tx_valid() || !is_reset) { - if (timestamp_expired(deadline, NULL)) { - last_tx_ok = 0; - return EC_ERROR_TIMEOUT; - } - if (wait_time_us < MSEC) - udelay(wait_time_us); - else - usleep(wait_time_us); - wait_time_us *= 2; - } - - return EC_SUCCESS; - } else { - last_tx_ok = !usb_console_tx_valid(); - return EC_SUCCESS; - } -} - -/* Try to send some bytes from the Tx FIFO to the host */ -static void tx_fifo_handler(void) -{ - int ret; - size_t count; - usb_uint *buf = (usb_uint *)ep_buf_tx; - - if (!is_reset) - return; - - ret = usb_wait_console(); - if (ret) - return; - - count = 0; - while (count < USB_MAX_PACKET_SIZE) { - int val = 0; - - if (!QUEUE_REMOVE_UNITS(&tx_q, &val, 1)) - break; - - if (!(count & 1)) - buf[count/2] = val; - else - buf[count/2] |= val << 8; - count++; - } - - if (count) - usb_enable_tx(count); -} -DECLARE_DEFERRED(tx_fifo_handler); - -static void handle_output(void) -{ - /* Wake up the Tx FIFO handler */ - hook_call_deferred(&tx_fifo_handler_data, 0); -} - -/* - * Public USB console implementation below. - */ -int usb_getc(void) -{ - int c = 0; - - if (!is_enabled) - return -1; - - if (!QUEUE_REMOVE_UNITS(&rx_q, &c, 1)) - return -1; - - return c; -} - -int usb_putc(int c) -{ - int ret; - - ret = __tx_char(NULL, c); - handle_output(); - - return ret; -} - -int usb_puts(const char *outstr) -{ - /* Put all characters in the output buffer */ - while (*outstr) { - if (__tx_char(NULL, *outstr++) != 0) - break; - } - handle_output(); - - /* Successful if we consumed all output */ - return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS; -} - -int usb_vprintf(const char *format, va_list args) -{ - int ret; - - ret = vfnprintf(__tx_char, NULL, format, args); - handle_output(); - - return ret; -} - -void usb_console_enable(int enabled, int readonly) -{ - is_enabled = enabled; - is_readonly = readonly; -} - -int usb_console_tx_blocked(void) -{ - return is_enabled && usb_console_tx_valid(); -} diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c deleted file mode 100644 index f4ee89f1f0..0000000000 --- a/chip/stm32/usb_dwc.c +++ /dev/null @@ -1,1423 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "flash.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "usb_hw.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_descriptor.h" -#include "watchdog.h" - - -/****************************************************************************/ -/* Debug output */ - -/* Console output macro */ -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -/* TODO: Something unexpected happened. Figure out how to report & fix it. */ -#define report_error(val) \ - CPRINTS("Unhandled USB event at %s line %d: 0x%x", \ - __FILE__, __LINE__, val) - - -/****************************************************************************/ -/* Standard USB stuff */ - -#ifdef CONFIG_USB_BOS -/* v2.10 (vs 2.00) BOS Descriptor provided */ -#define USB_DEV_BCDUSB 0x0210 -#else -#define USB_DEV_BCDUSB 0x0200 -#endif - -#ifndef USB_DEV_CLASS -#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE -#endif - -#ifndef CONFIG_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ -#endif - -#ifndef CONFIG_USB_SERIALNO -#define USB_STR_SERIALNO 0 -#else -static int usb_load_serial(void); -#endif - - -/* USB Standard Device Descriptor */ -static const struct usb_device_descriptor dev_desc = { - .bLength = USB_DT_DEVICE_SIZE, - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = USB_DEV_BCDUSB, - .bDeviceClass = USB_DEV_CLASS, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = USB_MAX_PACKET_SIZE, - .idVendor = USB_VID_GOOGLE, - .idProduct = CONFIG_USB_PID, - .bcdDevice = CONFIG_USB_BCD_DEV, - .iManufacturer = USB_STR_VENDOR, - .iProduct = USB_STR_PRODUCT, - .iSerialNumber = USB_STR_SERIALNO, - .bNumConfigurations = 1 -}; - -/* USB Configuration Descriptor */ -const struct usb_config_descriptor USB_CONF_DESC(conf) = { - .bLength = USB_DT_CONFIG_SIZE, - .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */ - .bNumInterfaces = USB_IFACE_COUNT, - .bConfigurationValue = 1, /* Caution: hard-coded value */ - .iConfiguration = USB_STR_VERSION, - .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 -#endif -#ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 -#endif - , - .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), -}; - -const uint8_t usb_string_desc[] = { - 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ -}; - -/****************************************************************************/ -/* Packet-handling stuff, specific to this SoC */ - -/* Some internal state to keep track of what's going on */ -static enum { - WAITING_FOR_SETUP_PACKET, - DATA_STAGE_IN, - NO_DATA_STAGE, -} what_am_i_doing; - -#ifdef DEBUG_ME -static const char * const wat[3] = { - [WAITING_FOR_SETUP_PACKET] = "wait_for_setup", - [DATA_STAGE_IN] = "data_in", - [NO_DATA_STAGE] = "no_data", -}; -#endif - -/* Programmer's Guide, Table 10-7 */ -enum table_case { - BAD_0, - TABLE_CASE_COMPLETE, - TABLE_CASE_SETUP, - TABLE_CASE_WTF, - TABLE_CASE_D, - TABLE_CASE_E, - BAD_6, - BAD_7, -}; - -static enum table_case decode_table_10_7(uint32_t doepint) -{ - enum table_case val = BAD_0; - - /* Bits: SI, SPD, IOC */ - if (doepint & DOEPINT_XFERCOMPL) - val += 1; - if (doepint & DOEPINT_SETUP) - val += 2; - return val; -} - -/* For STATUS/OUT: Use two DMA descriptors, each with one-packet buffers */ -#define NUM_OUT_BUFFERS 2 -static uint8_t __aligned(4) ep0_setup_buf[USB_MAX_PACKET_SIZE]; - -/* For IN: Several DMA descriptors, all pointing into one large buffer, so that - * we can return the configuration descriptor as one big blob. - */ -#define NUM_IN_PACKETS_AT_ONCE 4 -#define IN_BUF_SIZE (NUM_IN_PACKETS_AT_ONCE * USB_MAX_PACKET_SIZE) -static uint8_t __aligned(4) ep0_in_buf[IN_BUF_SIZE]; - -struct dwc_usb_ep ep0_ctl = { - .max_packet = USB_MAX_PACKET_SIZE, - .tx_fifo = 0, - .out_pending = 0, - .out_expected = 0, - .out_data = 0, - .out_databuffer = ep0_setup_buf, - .out_databuffer_max = sizeof(ep0_setup_buf), - .rx_deferred = 0, - .in_packets = 0, - .in_pending = 0, - .in_data = 0, - .in_databuffer = ep0_in_buf, - .in_databuffer_max = sizeof(ep0_in_buf), - .tx_deferred = 0, -}; - -/* Overall device state (USB 2.0 spec, section 9.1.1). - * We only need a few, though. - */ -static enum { - DS_DEFAULT, - DS_ADDRESS, - DS_CONFIGURED, -} device_state; -static uint8_t configuration_value; - - -/* True if the HW Rx/OUT FIFO is currently listening. */ -int rx_ep_is_active(uint32_t ep_num) -{ - return (GR_USB_DOEPCTL(ep_num) & DXEPCTL_EPENA) ? 1 : 0; -} - -/* Number of bytes the HW Rx/OUT FIFO has for us. - * - * @param ep_num USB endpoint - * - * @returns number of bytes ready, zero if none. - */ -int rx_ep_pending(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - - return ep->out_pending; -} - -/* True if the Tx/IN FIFO can take some bytes from us. */ -int tx_ep_is_ready(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - int ready; - - /* Is the tx hw idle? */ - ready = !(GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA); - - /* Is there no pending data? */ - ready &= (ep->in_pending == 0); - return ready; -} - -/* Write packets of data IN to the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the write completion event. - * - * @param ep_num USB endpoint to write - * @param len number of bytes to write - * @param data pointer of data to write - * - * @return bytes written - */ -int usb_write_ep(uint32_t ep_num, int len, void *data) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - - if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) { - CPRINTS("usb_write_ep ep%d: FAIL: tx already in progress!", - ep_num); - return 0; - } - - /* We will send as many packets as necessary, including a final - * packet of < USB_MAX_PACKET_SIZE (maybe zero length) - */ - ep->in_packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE; - ep->in_pending = len; - ep->in_data = data; - - GR_USB_DIEPTSIZ(ep_num) = 0; - - GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(ep->in_packets); - GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DIEPDMA(ep_num) = (uint32_t)(ep->in_data); - - /* We could support longer multi-dma transfers here. */ - ep->in_pending -= len; - ep->in_packets -= ep->in_packets; - ep->in_data += len; - - /* We are ready to enable this endpoint to start transferring data. */ - GR_USB_DIEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA; - return len; -} - -/* Tx/IN interrupt handler */ -void usb_epN_tx(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - uint32_t dieptsiz = GR_USB_DIEPTSIZ(ep_num); - - if (GR_USB_DIEPCTL(ep_num) & DXEPCTL_EPENA) { - CPRINTS("usb_epN_tx ep%d: tx still active.", ep_num); - return; - } - - /* clear the Tx/IN interrupts */ - GR_USB_DIEPINT(ep_num) = 0xffffffff; - - /* - * Let's assume this is actually true. - * We could support multi-dma transfers here. - */ - ep->in_packets = 0; - ep->in_pending = dieptsiz & GC_USB_DIEPTSIZ1_XFERSIZE_MASK; - - if (ep->tx_deferred) - hook_call_deferred(ep->tx_deferred, 0); -} - -/* Read a packet of data OUT from the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the read completion event. - * - * @param ep_num USB endpoint to read - * @param len number of bytes to read - * @param data pointer of data to read - * - * @return EC_SUCCESS on success - */ -int usb_read_ep(uint32_t ep_num, int len, void *data) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - int packets = (len + USB_MAX_PACKET_SIZE - 1) / USB_MAX_PACKET_SIZE; - - ep->out_data = data; - ep->out_pending = 0; - ep->out_expected = len; - - GR_USB_DOEPTSIZ(ep_num) = 0; - GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(packets); - GR_USB_DOEPTSIZ(ep_num) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DOEPDMA(ep_num) = (uint32_t)ep->out_data; - - GR_USB_DOEPCTL(ep_num) |= DXEPCTL_CNAK | DXEPCTL_EPENA; - return EC_SUCCESS; -} - -/* Rx/OUT endpoint interrupt handler */ -void usb_epN_rx(uint32_t ep_num) -{ - struct dwc_usb_ep *ep = usb_ctl.ep[ep_num]; - - /* Still receiving data. Let's wait. */ - if (rx_ep_is_active(ep_num)) - return; - - /* Bytes received decrement DOEPTSIZ XFERSIZE */ - if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) { - if (ep->out_expected > 0) { - ep->out_pending = - ep->out_expected - - (GR_USB_DOEPTSIZ(ep_num) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); - } else { - CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n", - ep_num, GR_USB_DOEPTSIZ(ep_num)); - ep->out_pending = 0; - } - ep->out_expected = 0; - GR_USB_DOEPTSIZ(ep_num) = 0; - } - - /* clear the RX/OUT interrupts */ - GR_USB_DOEPINT(ep_num) = 0xffffffff; - - if (ep->rx_deferred) - hook_call_deferred(ep->rx_deferred, 0); -} - -/* Reset endpoint HW block. */ -void epN_reset(uint32_t ep_num) -{ - GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK; - GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK | - DXEPCTL_TXFNUM(ep_num); - GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | - DAINT_OUTEP(ep_num); -} - - -/****************************************************************************** - * Internal and EP0 functions. - */ - - -static void flush_all_fifos(void) -{ - /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; - while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) - ; -} - -int send_in_packet(uint32_t ep_num) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[ep_num]; - int len = MIN(USB_MAX_PACKET_SIZE, ep->in_pending); - - if (ep->in_packets == 0) { - report_error(ep_num); - return -1; - } - - GR_USB_DIEPTSIZ(ep_num) = 0; - - GR_USB_DIEPTSIZ(ep_num) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data; - - - /* We're sending this much. */ - ep->in_pending -= len; - ep->in_packets -= 1; - ep->in_data += len; - - /* We are ready to enable this endpoint to start transferring data. */ - return len; -} - - -/* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns - * len, or negative on error. - */ -int initialize_in_transfer(const void *source, uint32_t len) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - -#ifdef CONFIG_USB_DWC_FS - /* FS OTG port does not support DMA or external phy */ - ASSERT(!(usb->dma_en)); - ASSERT(usb->phy_type == USB_PHY_INTERNAL); - ASSERT(usb->speed == USB_SPEED_FS); - ASSERT(usb->irq == STM32_IRQ_OTG_FS); -#else - /* HS OTG port requires an external phy to support HS */ - ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) && - (usb->speed == USB_SPEED_HS))); - ASSERT(usb->irq == STM32_IRQ_OTG_HS); -#endif - - /* Copy the data into our FIFO buffer */ - if (len >= IN_BUF_SIZE) { - report_error(len); - return -1; - } - - /* Stage data in DMA buffer. */ - memcpy(ep->in_databuffer, source, len); - ep->in_data = ep->in_databuffer; - - /* We will send as many packets as necessary, including a final - * packet of < USB_MAX_PACKET_SIZE (maybe zero length) - */ - ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE; - ep->in_pending = len; - - send_in_packet(0); - return len; -} - -/* Prepare the EP0 OUT FIFO buffer to accept some data. Returns len, or - * negative on error. - */ -int accept_out_fifo(uint32_t len) -{ - /* TODO: This is not yet implemented */ - report_error(len); - return -1; -} - -/* The next packet from the host should be a Setup packet. Get ready for it. */ -static void expect_setup_packet(void) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - - what_am_i_doing = WAITING_FOR_SETUP_PACKET; - ep->out_data = ep->out_databuffer; - - /* We don't care about IN packets right now, only OUT. */ - GR_USB_DAINTMSK |= DAINT_OUTEP(0); - GR_USB_DAINTMSK &= ~DAINT_INEP(0); - - GR_USB_DOEPTSIZ(0) = 0; - GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(0x18); - GR_USB_DOEPTSIZ(0) |= DXEPTSIZ_SUPCNT(1); - GR_USB_DOEPCTL(0) = DXEPCTL_USBACTEP | DXEPCTL_EPENA; - GR_USB_DOEPDMA(0) = (uint32_t)ep->out_data; -} - -/* We're complaining about something by stalling both IN and OUT packets, - * but a SETUP packet will get through anyway, so prepare for it. - */ -static void stall_both_fifos(void) -{ - what_am_i_doing = WAITING_FOR_SETUP_PACKET; - /* We don't care about IN packets right now, only OUT. */ - GR_USB_DAINTMSK |= DAINT_OUTEP(0); - GR_USB_DAINTMSK &= ~DAINT_INEP(0); - - GR_USB_DOEPCTL(0) |= DXEPCTL_STALL; - GR_USB_DIEPCTL(0) |= DXEPCTL_STALL; - expect_setup_packet(); -} - -/* The TX FIFO buffer is loaded. Start the Data phase. */ -static void expect_data_phase_in(enum table_case tc) -{ - what_am_i_doing = DATA_STAGE_IN; - - /* Send the reply (data phase in) */ - if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | - DXEPCTL_CNAK | DXEPCTL_EPENA; - else - GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; - - /* We'll receive an empty packet back as a ack, I guess. */ - if (tc == TABLE_CASE_SETUP) - GR_USB_DOEPCTL(0) |= DXEPCTL_CNAK | DXEPCTL_EPENA; - else - GR_USB_DOEPCTL(0) |= DXEPCTL_EPENA; - - /* Get an interrupt when either IN or OUT arrives */ - GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0)); - -} - -static void expect_data_phase_out(enum table_case tc) -{ - /* TODO: This is not yet supported */ - report_error(tc); - expect_setup_packet(); -} - -/* No Data phase, just Status phase (which is IN, since Setup is OUT) */ -static void expect_status_phase_in(enum table_case tc) -{ - what_am_i_doing = NO_DATA_STAGE; - - /* Expect a zero-length IN for the Status phase */ - (void) initialize_in_transfer(0, 0); - - /* Blindly following instructions here, too. */ - if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP - | DXEPCTL_CNAK | DXEPCTL_EPENA; - else - GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; - - /* Get an interrupt when either IN or OUT arrives */ - GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0)); -} - -/* Handle a Setup packet that expects us to send back data in reply. Return the - * length of the data we're returning, or negative to indicate an error. - */ -static int handle_setup_with_in_stage(enum table_case tc, - struct usb_setup_packet *req) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - - const void *data = 0; - uint32_t len = 0; - int ugly_hack = 0; - static const uint16_t zero; /* == 0 */ - - switch (req->bRequest) { - case USB_REQ_GET_DESCRIPTOR: { - uint8_t type = req->wValue >> 8; - uint8_t idx = req->wValue & 0xff; - - switch (type) { - case USB_DT_DEVICE: - data = &dev_desc; - len = sizeof(dev_desc); - break; - case USB_DT_CONFIGURATION: - data = __usb_desc; - len = USB_DESC_SIZE; - ugly_hack = 1; /* see below */ - break; -#ifdef CONFIG_USB_BOS - case USB_DT_BOS: - data = bos_ctx.descp; - len = bos_ctx.size; - break; -#endif - case USB_DT_STRING: - if (idx >= USB_STR_COUNT) - return -1; -#ifdef CONFIG_USB_SERIALNO - if (idx == USB_STR_SERIALNO) - data = (uint8_t *)usb_serialno_desc; - else -#endif - data = usb_strings[idx]; - len = *(uint8_t *)data; - break; - case USB_DT_DEVICE_QUALIFIER: - /* We're not high speed */ - return -1; - case USB_DT_DEBUG: - /* Not supported */ - return -1; - default: - report_error(type); - return -1; - } - break; - } - case USB_REQ_GET_STATUS: { - /* TODO: Device Status: Remote Wakeup? Self Powered? */ - data = &zero; - len = sizeof(zero); - break; - } - case USB_REQ_GET_CONFIGURATION: - data = &configuration_value; - len = sizeof(configuration_value); - break; - - case USB_REQ_SYNCH_FRAME: - /* Unimplemented */ - return -1; - - default: - report_error(req->bRequest); - return -1; - } - - /* Don't send back more than we were asked for. */ - len = MIN(req->wLength, len); - - /* Prepare the TX FIFO. If we haven't preallocated enough room in the - * TX FIFO for the largest reply, we'll have to stall. This is a bug in - * our code, but detecting it easily at compile time is related to the - * ugly_hack directly below. - */ - if (initialize_in_transfer(data, len) < 0) - return -1; - - if (ugly_hack) { - /* - * TODO: Somebody figure out how to fix this, please. - * - * The USB configuration descriptor request is unique in that - * it not only returns the configuration descriptor, but also - * all the interface descriptors and all their endpoint - * descriptors as one enormous blob. We've set up some macros - * so we can declare and implement separate interfaces in - * separate files just by compiling them, and all the relevant - * descriptors are sorted and bundled up by the linker. But the - * total length of the entire blob needs to appear in the first - * configuration descriptor struct and because we don't know - * that value until after linking, it can't be initialized as a - * constant. So we have to compute it at run-time and shove it - * in here, which also means that we have to copy the whole - * blob into our TX FIFO buffer so that it's mutable. Otherwise - * we could just point at it (or pretty much any other constant - * struct that we wanted to send to the host). Bah. - */ - struct usb_config_descriptor *cfg = - (struct usb_config_descriptor *)ep->in_databuffer; - /* set the real descriptor size */ - cfg->wTotalLength = USB_DESC_SIZE; - } - - return len; -} - -/* Handle a Setup that comes with additional data for us. */ -static int handle_setup_with_out_stage(enum table_case tc, - struct usb_setup_packet *req) -{ - /* TODO: We don't support any of these. We should. */ - report_error(-1); - return -1; -} - -/* Some Setup packets don't have a data stage at all. */ -static int handle_setup_with_no_data_stage(enum table_case tc, - struct usb_setup_packet *req) -{ - uint8_t set_addr; - - switch (req->bRequest) { - case USB_REQ_SET_ADDRESS: - /* - * Set the address after the IN packet handshake. - * - * From the USB 2.0 spec, section 9.4.6: - * - * As noted elsewhere, requests actually may result in - * up to three stages. In the first stage, the Setup - * packet is sent to the device. In the optional second - * stage, data is transferred between the host and the - * device. In the final stage, status is transferred - * between the host and the device. The direction of - * data and status transfer depends on whether the host - * is sending data to the device or the device is - * sending data to the host. The Status stage transfer - * is always in the opposite direction of the Data - * stage. If there is no Data stage, the Status stage - * is from the device to the host. - * - * Stages after the initial Setup packet assume the - * same device address as the Setup packet. The USB - * device does not change its device address until - * after the Status stage of this request is completed - * successfully. Note that this is a difference between - * this request and all other requests. For all other - * requests, the operation indicated must be completed - * before the Status stage - */ - set_addr = req->wValue & 0xff; - /* - * NOTE: Now that we've said that, we don't do it. The - * hardware for this SoC knows that an IN packet will - * be following the SET ADDRESS, so it waits until it - * sees that happen before the address change takes - * effect. If we wait until after the IN packet to - * change the register, the hardware gets confused and - * doesn't respond to anything. - */ - GWRITE_FIELD(USB, DCFG, DEVADDR, set_addr); - CPRINTS("SETAD 0x%02x (%d)", set_addr, set_addr); - device_state = DS_ADDRESS; - break; - - case USB_REQ_SET_CONFIGURATION: - switch (req->wValue) { - case 0: - configuration_value = req->wValue; - device_state = DS_ADDRESS; - break; - case 1: /* Caution: Only one config descriptor TODAY */ - /* TODO: All endpoints set to DATA0 toggle state */ - configuration_value = req->wValue; - device_state = DS_CONFIGURED; - break; - default: - /* Nope. That's a paddlin. */ - report_error(-1); - return -1; - } - break; - - case USB_REQ_CLEAR_FEATURE: - case USB_REQ_SET_FEATURE: - /* TODO: Handle DEVICE_REMOTE_WAKEUP, ENDPOINT_HALT? */ - break; - - default: - /* Anything else is unsupported */ - report_error(-1); - return -1; - } - - /* No data to transfer, go straight to the Status phase. */ - return 0; -} - -/* Dispatch an incoming Setup packet according to its type */ -static void handle_setup(enum table_case tc) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - struct usb_setup_packet *req = - (struct usb_setup_packet *)ep->out_databuffer; - int data_phase_in = req->bmRequestType & USB_DIR_IN; - int data_phase_out = !data_phase_in && req->wLength; - int bytes = -1; /* default is to stall */ - - if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) { - /* Standard Device requests */ - if (data_phase_in) - bytes = handle_setup_with_in_stage(tc, req); - else if (data_phase_out) - bytes = handle_setup_with_out_stage(tc, req); - else - bytes = handle_setup_with_no_data_stage(tc, req); - } else if (USB_RECIP_INTERFACE == - (req->bmRequestType & USB_RECIP_MASK)) { - /* Interface-specific requests */ - uint8_t iface = req->wIndex & 0xff; - - if (iface < USB_IFACE_COUNT) - bytes = usb_iface_request[iface](req); - } else { - /* Something we need to add support for? */ - report_error(-1); - } - - /* We say "no" to unsupported and intentionally unhandled requests by - * stalling the Data and/or Status stage. - */ - if (bytes < 0) { - /* Stall both IN and OUT. SETUP will come through anyway. */ - stall_both_fifos(); - } else { - if (data_phase_in) - expect_data_phase_in(tc); - else if (data_phase_out) - expect_data_phase_out(tc); - else - expect_status_phase_in(tc); - } -} - -/* This handles both IN and OUT interrupts for EP0 */ -static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) -{ - struct dwc_usb *usb = &usb_ctl; - struct dwc_usb_ep *ep = usb->ep[0]; - uint32_t doepint, diepint; - enum table_case tc; - int out_complete, out_setup, in_complete; - - /* Determine the interrupt cause and clear the bits quickly, but only - * if they really apply. I don't think they're trustworthy if we didn't - * actually get an interrupt. - */ - doepint = GR_USB_DOEPINT(0) & GR_USB_DOEPMSK; - if (intr_on_out) - GR_USB_DOEPINT(0) = doepint; - diepint = GR_USB_DIEPINT(0) & GR_USB_DIEPMSK; - if (intr_on_in) - GR_USB_DIEPINT(0) = diepint; - - out_complete = doepint & DOEPINT_XFERCOMPL; - out_setup = doepint & DOEPINT_SETUP; - in_complete = diepint & DIEPINT_XFERCOMPL; - - /* Decode the situation according to Table 10-7 */ - tc = decode_table_10_7(doepint); - - switch (what_am_i_doing) { - case WAITING_FOR_SETUP_PACKET: - if (out_setup) - handle_setup(tc); - else - report_error(-1); - break; - - case DATA_STAGE_IN: - if (intr_on_in && in_complete) { - /* A packet is sent. Should we send another? */ - if (ep->in_packets > 0) { - /* Send another packet. */ - send_in_packet(0); - expect_data_phase_in(tc); - } - } - - /* But we should ignore the OUT endpoint if we didn't actually - * get an OUT interrupt. - */ - if (!intr_on_out) - break; - - if (out_setup) { - /* The first IN packet has been seen. Keep going. */ - break; - } - if (out_complete) { - /* We've handled the Status phase. All done. */ - expect_setup_packet(); - break; - } - - /* Anything else should be ignorable. Right? */ - break; - - case NO_DATA_STAGE: - if (intr_on_in && in_complete) { - /* We are not expecting an empty packet in - * return for our empty packet. - */ - expect_setup_packet(); - } - - /* Done unless we got an OUT interrupt */ - if (!intr_on_out) - break; - - if (out_setup) { - report_error(-1); - break; - } - - /* Anything else means get ready for a Setup packet */ - report_error(-1); - expect_setup_packet(); - break; - } -} - -/****************************************************************************/ -/* USB device initialization and shutdown routines */ - -/* - * DATA FIFO Setup. There is an internal SPRAM used to buffer the IN/OUT - * packets and track related state without hammering the AHB and system RAM - * during USB transactions. We have to specify where and how much of that SPRAM - * to use for what. - * - * See Programmer's Guide chapter 2, "Calculating FIFO Size". - * We're using Dedicated TxFIFO Operation, without enabling thresholding. - * - * Section 2.1.1.2, page 30: RXFIFO size is the same as for Shared FIFO, which - * is Section 2.1.1.1, page 28. This is also the same as Method 2 on page 45. - * - * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max - * data packet size is 64 bytes. Total SPRAM available is 1024 slots. - */ -#define MAX_CONTROL_EPS 3 -#define MAX_NORMAL_EPS 16 -#define FIFO_RAM_DEPTH 1024 -/* - * Device RX FIFO size is thus: - * (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85 - */ -#define RXFIFO_SIZE ((4 * MAX_CONTROL_EPS + 6) + \ - 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \ - (2 * MAX_NORMAL_EPS) + 1) -/* - * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46). - */ -#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4)) -/* - * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1, - * unconfigurable). - */ -#define EP_STATUS_SIZE (4 * MAX_NORMAL_EPS * 2) -/* - * Make sure all that fits. - */ -BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE < - FIFO_RAM_DEPTH); - - -/* Now put those constants into the correct registers */ -static void setup_data_fifos(void) -{ - int i; - - /* Programmer's Guide, p31 */ - GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */ - GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */ - - /* TXFIFO 1..15 */ - for (i = 1; i < MAX_NORMAL_EPS; i++) - GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) | - (RXFIFO_SIZE + i * TXFIFO_SIZE)); - - /* - * TODO: The Programmer's Guide is confusing about when or whether to - * flush the FIFOs. Section 2.1.1.2 (p31) just says to flush. Section - * 2.2.2 (p55) says to stop all the FIFOs first, then flush. Section - * 7.5.4 (p162) says that flushing the RXFIFO at reset is not - * recommended at all. - * - * I'm also unclear on whether or not the individual EPs are expected - * to be disabled already (DIEPCTLn/DOEPCTLn.EPENA == 0), and if so, - * whether by firmware or hardware. - */ - - /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; - while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) - ; /* TODO: timeout 100ms */ -} - -static void usb_init_endpoints(void) -{ - int ep; - - /* Prepare to receive packets on EP0 */ - expect_setup_packet(); - - /* Reset the other endpoints */ - for (ep = 1; ep < USB_EP_COUNT; ep++) - usb_ep_event[ep](USB_EVENT_RESET); -} - -static void usb_reset(void) -{ - /* Clear our internal state */ - device_state = DS_DEFAULT; - configuration_value = 0; - - /* Clear the device address */ - GWRITE_FIELD(USB, DCFG, DEVADDR, 0); - - /* Reinitialize all the endpoints */ - usb_init_endpoints(); -} - -static void usb_resetdet(void) -{ - /* TODO: Same as normal reset, right? I think we only get this if we're - * suspended (sleeping) and the host resets us. Try it and see. - */ - usb_reset(); -} - -static void usb_enumdone(void) -{ - /* We can change to HS here. We will not go to HS today */ - GR_USB_DCTL |= DCTL_CGOUTNAK; -} - - -void usb_interrupt(void) -{ - uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK; - uint32_t oepint = status & GINTSTS(OEPINT); - uint32_t iepint = status & GINTSTS(IEPINT); - int ep; - - if (status & GINTSTS(ENUMDONE)) - usb_enumdone(); - - if (status & GINTSTS(RESETDET)) - usb_resetdet(); - - if (status & GINTSTS(USBRST)) - usb_reset(); - - /* Endpoint interrupts */ - if (oepint || iepint) { - /* Note: It seems that the DAINT bits are only trustworthy for - * identifying interrupts when selected by the corresponding - * OEPINT and IEPINT bits from GINTSTS. - */ - uint32_t daint = GR_USB_DAINT; - - /* EP0 has a combined IN/OUT handler. Only call it once, but - * let it know which direction(s) had an interrupt. - */ - if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) { - uint32_t intr_on_out = (oepint && - (daint & DAINT_OUTEP(0))); - uint32_t intr_on_in = (iepint && - (daint & DAINT_INEP(0))); - ep0_interrupt(intr_on_out, intr_on_in); - } - - /* Invoke the unidirectional IN and OUT functions for the other - * endpoints. Each handler must clear their own bits in - * DIEPINTn/DOEPINTn. - */ - for (ep = 1; ep < USB_EP_COUNT; ep++) { - if (oepint && (daint & DAINT_OUTEP(ep))) - usb_ep_rx[ep](); - if (iepint && (daint & DAINT_INEP(ep))) - usb_ep_tx[ep](); - } - } - - GR_USB_GINTSTS = status; -} -DECLARE_IRQ(STM32_IRQ_OTG_FS, usb_interrupt, 1); -DECLARE_IRQ(STM32_IRQ_OTG_HS, usb_interrupt, 1); - -static void usb_softreset(void) -{ - int timeout; - - CPRINTS("%s", __func__); - - /* Wait for bus idle */ - timeout = 10000; - while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0) - ; - - /* Reset and wait for clear */ - GR_USB_GRSTCTL = GRSTCTL_CSFTRST; - timeout = 10000; - while ((GR_USB_GRSTCTL & GRSTCTL_CSFTRST) && timeout-- > 0) - ; - if (GR_USB_GRSTCTL & GRSTCTL_CSFTRST) { - CPRINTF("USB: reset failed\n"); - return; - } - - /* Some more idle? */ - timeout = 10000; - while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0) - ; - - if (!timeout) { - CPRINTF("USB: reset timeout\n"); - return; - } - /* TODO: Wait 3 PHY clocks before returning */ -} - -void usb_connect(void) -{ - GR_USB_DCTL &= ~DCTL_SFTDISCON; -} - -void usb_disconnect(void) -{ - GR_USB_DCTL |= DCTL_SFTDISCON; - - device_state = DS_DEFAULT; - configuration_value = 0; -} - -void usb_reset_init_phy(void) -{ - struct dwc_usb *usb = &usb_ctl; - - if (usb->phy_type == USB_PHY_ULPI) { - GR_USB_GCCFG &= ~GCCFG_PWRDWN; - GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS | - GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); - GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); - /* No suspend */ - GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR; - - usb_softreset(); - } else { - GR_USB_GUSBCFG |= GUSBCFG_PHYSEL; - usb_softreset(); - GR_USB_GCCFG |= GCCFG_PWRDWN; - } -} - -void usb_init(void) -{ - int i; - struct dwc_usb *usb = &usb_ctl; - - CPRINTS("%s", __func__); - -#ifdef CONFIG_USB_SERIALNO - usb_load_serial(); -#endif - - /* USB is in use */ - disable_sleep(SLEEP_MASK_USB_DEVICE); - - /* Enable clocks */ - clock_enable_module(MODULE_USB, 0); - clock_enable_module(MODULE_USB, 1); - - /* TODO(crbug.com/496888): set up pinmux */ - gpio_config_module(MODULE_USB, 1); - - /* Make sure interrupts are disabled */ - GR_USB_GINTMSK = 0; - GR_USB_DAINTMSK = 0; - GR_USB_DIEPMSK = 0; - GR_USB_DOEPMSK = 0; - - /* Full-Speed Serial PHY */ - usb_reset_init_phy(); - - /* Global + DMA configuration */ - GR_USB_GAHBCFG = GAHBCFG_GLB_INTR_EN; - GR_USB_GAHBCFG |= GAHBCFG_HBSTLEN_INCR4; - if (usb->dma_en) - GR_USB_GAHBCFG |= GAHBCFG_DMA_EN; - - /* Device only, no SRP */ - GR_USB_GUSBCFG |= GUSBCFG_FDMOD; - GR_USB_GUSBCFG |= GUSBCFG_SRPCAP | GUSBCFG_HNPCAP; - - GR_USB_GCCFG &= ~GCCFG_VBDEN; - GR_USB_GOTGCTL |= GOTGCTL_BVALOEN; - GR_USB_GOTGCTL |= GOTGCTL_BVALOVAL; - - GR_USB_PCGCCTL = 0; - - if (usb->phy_type == USB_PHY_ULPI) { - /* TODO(nsanders): add HS support like so. - * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - * | DCFG_DEVSPD_HSULPI; - */ - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FSULPI; - } else { - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FS48; - } - - GR_USB_DCFG |= DCFG_NZLSOHSK; - - flush_all_fifos(); - - /* Clear pending interrupts again */ - GR_USB_GINTMSK = 0; - GR_USB_DIEPMSK = 0; - GR_USB_DOEPMSK = 0; - GR_USB_DAINT = 0xffffffff; - GR_USB_DAINTMSK = 0; - - /* TODO: What about the AHB Burst Length Field? It's 0 now. */ - GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL; - - /* Device only, no SRP */ - GR_USB_GUSBCFG |= GUSBCFG_FDMOD - | GUSBCFG_TOUTCAL(7) - /* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */ - | GUSBCFG_USBTRDTIM(14); - - /* Be in disconnected state until we are ready */ - usb_disconnect(); - - /* If we've restored a nonzero device address, update our state. */ - if (GR_USB_DCFG & GC_USB_DCFG_DEVADDR_MASK) { - /* Caution: We only have one config TODAY, so there's no real - * difference between DS_CONFIGURED and DS_ADDRESS. - */ - device_state = DS_CONFIGURED; - configuration_value = 1; - } else { - device_state = DS_DEFAULT; - configuration_value = 0; - } - - /* Now that DCFG.DesDMA is accurate, prepare the FIFOs */ - setup_data_fifos(); - - usb_init_endpoints(); - - /* Clear any pending interrupts */ - for (i = 0; i < 16; i++) { - GR_USB_DIEPINT(i) = 0xffffffff; - GR_USB_DIEPTSIZ(i) = 0; - GR_USB_DOEPINT(i) = 0xffffffff; - GR_USB_DOEPTSIZ(i) = 0; - } - - if (usb->dma_en) { - GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6; - GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN - | DTHRCTL_NONISOTHREN; - i = GR_USB_DTHRCTL; - } - - GR_USB_GINTSTS = 0xFFFFFFFF; - - GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL - | GAHBCFG_PTXFELVL; - - if (!(usb->dma_en)) - GR_USB_GINTMSK |= GINTMSK(RXFLVL); - - /* Unmask some endpoint interrupt causes */ - GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK; - GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK | - DOEPMSK_SETUPMSK; - - /* Enable interrupt handlers */ - task_enable_irq(usb->irq); - - /* Allow USB interrupts to come in */ - GR_USB_GINTMSK |= - /* NAK bits that must be cleared by the DCTL register */ - GINTMSK(GOUTNAKEFF) | GINTMSK(GINNAKEFF) | - /* Initialization events */ - GINTMSK(USBRST) | GINTMSK(ENUMDONE) | - /* Reset detected while suspended. Need to wake up. */ - GINTMSK(RESETDET) | /* TODO: Do we need this? */ - /* Idle, Suspend detected. Should go to sleep. */ - GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP); - - GR_USB_GINTMSK |= - /* Endpoint activity, cleared by the DOEPINT/DIEPINT regs */ - GINTMSK(OEPINT) | GINTMSK(IEPINT); - - /* Device registers have been setup */ - GR_USB_DCTL |= DCTL_PWRONPRGDONE; - udelay(10); - GR_USB_DCTL &= ~DCTL_PWRONPRGDONE; - - /* Clear global NAKs */ - GR_USB_DCTL |= DCTL_CGOUTNAK | DCTL_CGNPINNAK; - -#ifndef CONFIG_USB_INHIBIT_CONNECT - /* Indicate our presence to the USB host */ - usb_connect(); -#endif -} -#ifndef CONFIG_USB_INHIBIT_INIT -DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT); -#endif - -void usb_release(void) -{ - struct dwc_usb *usb = &usb_ctl; - - /* signal disconnect to host */ - usb_disconnect(); - - /* disable interrupt handlers */ - task_disable_irq(usb->irq); - - /* disable clocks */ - clock_enable_module(MODULE_USB, 0); - /* TODO: pin-mux */ - - /* USB is off, so sleep whenever */ - enable_sleep(SLEEP_MASK_USB_DEVICE); -} - -/* Print USB info and stats */ -static void usb_info(void) -{ - struct dwc_usb *usb = &usb_ctl; - int i; - - CPRINTF("USB settings: %s%s%s\n", - usb->speed == USB_SPEED_FS ? "FS " : "HS ", - usb->phy_type == USB_PHY_INTERNAL ? "Internal Phy " : "ULPI ", - usb->dma_en ? "DMA " : ""); - - for (i = 0; i < USB_EP_COUNT; i++) { - CPRINTF("Endpoint %d activity: %s%s\n", i, - rx_ep_is_active(i) ? "RX " : "", - tx_ep_is_ready(i) ? "" : "TX "); - } -} - -static int command_usb(int argc, char **argv) -{ - if (argc > 1) { - if (!strcasecmp("on", argv[1])) - usb_init(); - else if (!strcasecmp("off", argv[1])) - usb_release(); - else if (!strcasecmp("info", argv[1])) - usb_info(); - return EC_SUCCESS; - } - - return EC_ERROR_PARAM1; -} -DECLARE_CONSOLE_COMMAND(usb, command_usb, - "[on|off|info]", - "Get/set the USB connection state and PHY selection"); - -#ifdef CONFIG_USB_SERIALNO -/* This will be subbed into USB_STR_SERIALNO. */ -struct usb_string_desc *usb_serialno_desc = - USB_WR_STRING_DESC(DEFAULT_SERIALNO); - -/* Update serial number */ -static int usb_set_serial(const char *serialno) -{ - struct usb_string_desc *sd = usb_serialno_desc; - int i; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Convert into unicode usb string desc. */ - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) { - sd->_data[i] = serialno[i]; - if (serialno[i] == 0) - break; - } - /* Count wchars (w/o null terminator) plus size & type bytes. */ - sd->_len = (i * 2) + 2; - sd->_type = USB_DT_STRING; - - return EC_SUCCESS; -} - -/* Retrieve serial number from pstate flash. */ -static int usb_load_serial(void) -{ - const char *serialno; - int rv; - - serialno = board_read_serial(); - if (!serialno) - return EC_ERROR_ACCESS_DENIED; - - rv = usb_set_serial(serialno); - return rv; -} - -/* Save serial number into pstate region. */ -static int usb_save_serial(const char *serialno) -{ - int rv; - - if (!serialno) - return EC_ERROR_INVAL; - - /* Save this new serial number to flash. */ - rv = board_write_serial(serialno); - if (rv) - return rv; - - /* Load this new serial number to memory. */ - rv = usb_load_serial(); - return rv; -} - -static int command_serialno(int argc, char **argv) -{ - struct usb_string_desc *sd = usb_serialno_desc; - char buf[CONFIG_SERIALNO_LEN]; - int rv = EC_SUCCESS; - int i; - - if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { - ccprintf("Saving serial number\n"); - rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { - ccprintf("Loading serial number\n"); - rv = usb_load_serial(); - } else - return EC_ERROR_INVAL; - } - - for (i = 0; i < CONFIG_SERIALNO_LEN; i++) - buf[i] = sd->_data[i]; - ccprintf("Serial number: %s\n", buf); - return rv; -} - -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c deleted file mode 100644 index 0d1340fb83..0000000000 --- a/chip/stm32/usb_dwc_console.c +++ /dev/null @@ -1,360 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "config.h" -#include "console.h" -#include "link_defs.h" -#include "printf.h" -#include "queue.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define USB_CONSOLE_TIMEOUT_US (30 * MSEC) - -static int last_tx_ok = 1; - -static int is_reset; -static int is_enabled = 1; -static int is_readonly; - -/* USB-Serial descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 -}; - -static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE]; -static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE]; - -static struct queue const tx_q = QUEUE_NULL(256, uint8_t); -static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); - - -struct dwc_usb_ep ep_console_ctl = { - .max_packet = USB_MAX_PACKET_SIZE, - .tx_fifo = USB_EP_CONSOLE, - .out_pending = 0, - .out_data = 0, - .out_databuffer = ep_buf_tx, - .out_databuffer_max = sizeof(ep_buf_tx), - .in_packets = 0, - .in_pending = 0, - .in_data = 0, - .in_databuffer = ep_buf_rx, - .in_databuffer_max = sizeof(ep_buf_rx), -}; - - - -/* Let the USB HW IN-to-host FIFO transmit some bytes */ -static void usb_enable_tx(int len) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - ep->in_data = ep->in_databuffer; - ep->in_packets = 1; - ep->in_pending = len; - - GR_USB_DIEPTSIZ(USB_EP_CONSOLE) = 0; - - GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DIEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DIEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->in_data; - - GR_USB_DIEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA; -} - -/* Let the USB HW OUT-from-host FIFO receive some bytes */ -static void usb_enable_rx(int len) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - ep->out_data = ep->out_databuffer; - ep->out_pending = 0; - - GR_USB_DOEPTSIZ(USB_EP_CONSOLE) = 0; - GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1); - GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len); - GR_USB_DOEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->out_data; - - GR_USB_DOEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA; -} - -/* True if the HW Rx/OUT FIFO has bytes for us. */ -static inline int rx_fifo_is_ready(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - return ep->out_pending; -} - -/* - * This function tries to shove new bytes from the USB host into the queue for - * consumption elsewhere. It is invoked either by a HW interrupt (telling us we - * have new bytes from the USB host), or by whoever is reading bytes out of the - * other end of the queue (telling us that there's now more room in the queue - * if we still have bytes to shove in there). - */ -char buffer[65]; -static void rx_fifo_handler(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - int rx_in_fifo; - size_t added; - - if (!rx_fifo_is_ready()) - return; - - rx_in_fifo = ep->out_pending; - added = QUEUE_ADD_UNITS(&rx_q, ep->out_databuffer, rx_in_fifo); - - if (added != rx_in_fifo) - CPRINTF("DROP CONSOLE: %d/%d process\n", added, rx_in_fifo); - - /* wake-up the console task */ - console_has_input(); - - usb_enable_rx(USB_MAX_PACKET_SIZE); -} -DECLARE_DEFERRED(rx_fifo_handler); - -/* Rx/OUT interrupt handler */ -static void con_ep_rx(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - - if (GR_USB_DOEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA) - return; - - /* Bytes received decrement DOEPTSIZ XFERSIZE */ - if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) { - ep->out_pending = - ep->max_packet - - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); - } - - /* Wake up the Rx FIFO handler */ - hook_call_deferred(&rx_fifo_handler_data, 0); - - /* clear the RX/OUT interrupts */ - GR_USB_DOEPINT(USB_EP_CONSOLE) = 0xffffffff; -} - -/* True if the Tx/IN FIFO can take some bytes from us. */ -static inline int tx_fifo_is_ready(void) -{ - return !(GR_USB_DIEPCTL(USB_EP_CONSOLE) & DXEPCTL_EPENA); -} - -/* Try to send some bytes to the host */ -static void tx_fifo_handler(void) -{ - struct dwc_usb_ep *ep = &ep_console_ctl; - size_t count; - - if (!is_reset) - return; - - /* If the HW FIFO isn't ready, then we can't do anything right now. */ - if (!tx_fifo_is_ready()) - return; - - count = QUEUE_REMOVE_UNITS(&tx_q, - ep->in_databuffer, USB_MAX_PACKET_SIZE); - if (count) - usb_enable_tx(count); -} -DECLARE_DEFERRED(tx_fifo_handler); - -static void handle_output(void) -{ - /* Wake up the Tx FIFO handler */ - hook_call_deferred(&tx_fifo_handler_data, 0); -} - -/* Tx/IN interrupt handler */ -static void con_ep_tx(void) -{ - /* Wake up the Tx FIFO handler */ - hook_call_deferred(&tx_fifo_handler_data, 0); - - /* clear the Tx/IN interrupts */ - GR_USB_DIEPINT(USB_EP_CONSOLE) = 0xffffffff; -} - -static void ep_event(enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - epN_reset(USB_EP_CONSOLE); - - is_reset = 1; - - /* Flush any queued data */ - hook_call_deferred(&tx_fifo_handler_data, 0); - hook_call_deferred(&rx_fifo_handler_data, 0); - - usb_enable_rx(USB_MAX_PACKET_SIZE); -} - - -USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event); - -static int usb_wait_console(void) -{ - timestamp_t deadline = get_time(); - int wait_time_us = 1; - - if (!is_enabled || !tx_fifo_is_ready()) - return EC_SUCCESS; - - deadline.val += USB_CONSOLE_TIMEOUT_US; - - /* - * If the USB console is not used, Tx buffer would never free up. - * In this case, let's drop characters immediately instead of sitting - * for some time just to time out. On the other hand, if the last - * Tx is good, it's likely the host is there to receive data, and - * we should wait so that we don't clobber the buffer. - */ - if (last_tx_ok) { - while (queue_space(&tx_q) < USB_MAX_PACKET_SIZE || !is_reset) { - if (timestamp_expired(deadline, NULL) || - in_interrupt_context()) { - last_tx_ok = 0; - return EC_ERROR_TIMEOUT; - } - if (wait_time_us < MSEC) - udelay(wait_time_us); - else - usleep(wait_time_us); - wait_time_us *= 2; - } - - return EC_SUCCESS; - } - - last_tx_ok = queue_space(&tx_q); - return EC_SUCCESS; -} -static int __tx_char(void *context, int c) -{ - struct queue *state = - (struct queue *) context; - - if (c == '\n' && __tx_char(state, '\r')) - return 1; - - QUEUE_ADD_UNITS(state, &c, 1); - return 0; -} - -/* - * Public USB console implementation below. - */ -int usb_getc(void) -{ - int c; - - if (!is_enabled) - return -1; - - if (QUEUE_REMOVE_UNITS(&rx_q, &c, 1)) - return c; - - return -1; -} - -int usb_puts(const char *outstr) -{ - int ret; - struct queue state; - - if (is_readonly) - return EC_SUCCESS; - - ret = usb_wait_console(); - if (ret) - return ret; - - state = tx_q; - while (*outstr) - if (__tx_char(&state, *outstr++)) - break; - - if (queue_count(&state)) - handle_output(); - - return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS; -} - -int usb_putc(int c) -{ - char string[2]; - - string[0] = c; - string[1] = '\0'; - return usb_puts(string); -} - -int usb_vprintf(const char *format, va_list args) -{ - int ret; - struct queue state; - - if (is_readonly) - return EC_SUCCESS; - - ret = usb_wait_console(); - if (ret) - return ret; - - state = tx_q; - ret = vfnprintf(__tx_char, &state, format, args); - - if (queue_count(&state)) - handle_output(); - - return ret; -} - -void usb_console_enable(int enabled, int readonly) -{ - is_enabled = enabled; - is_readonly = readonly; -} diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h deleted file mode 100644 index ab2206d359..0000000000 --- a/chip/stm32/usb_dwc_console.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CHIP_STM32_USB_DWC_CONSOLE_H -#define __CHIP_STM32_USB_DWC_CONSOLE_H - -#include "usb_hw.h" - -extern struct dwc_usb_ep ep_console_ctl; - -#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */ diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h deleted file mode 100644 index d1fe07cb87..0000000000 --- a/chip/stm32/usb_dwc_hw.h +++ /dev/null @@ -1,106 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_DWC_HW_H -#define __CROS_EC_USB_DWC_HW_H - -#include "usb_dwc_registers.h" - -/* Helpers for endpoint declaration */ -#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix) -#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx) -#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx) -#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt) -/* Used to check function types are correct (attribute alias does not do it) */ -#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck) -#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) -#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) - -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler - -/* Endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); -struct usb_setup_packet; -/* EP0 Interface handler callbacks */ -extern int (*usb_iface_request[]) (struct usb_setup_packet *req); - - -/* True if the HW Rx/OUT FIFO is currently listening. */ -int rx_ep_is_active(uint32_t ep_num); - -/* Number of bytes the HW Rx/OUT FIFO has for us. - * - * @param ep_num USB endpoint - * - * @returns number of bytes ready, zero if none. - */ -int rx_ep_pending(uint32_t ep_num); - -/* True if the Tx/IN FIFO can take some bytes from us. */ -int tx_ep_is_ready(uint32_t ep_num); - -/* Write packets of data IN to the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the write completion event. - * - * @param ep_num USB endpoint to write - * @param len number of bytes to write - * @param data pointer of data to write - * - * @return bytes written - */ -int usb_write_ep(uint32_t ep_num, int len, void *data); - -/* Read a packet of data OUT from the host. - * - * This function uses DMA, so the *data write buffer - * must persist until the read completion event. - * - * @param ep_num USB endpoint to read - * @param len number of bytes to read - * @param data pointer of data to read - * - * @return EC_SUCCESS on success - */ -int usb_read_ep(uint32_t ep_num, int len, void *data); - -/* Tx/IN interrupt handler */ -void usb_epN_tx(uint32_t ep_num); - -/* Rx/OUT endpoint interrupt handler */ -void usb_epN_rx(uint32_t ep_num); - -/* Reset endpoint HW block. */ -void epN_reset(uint32_t ep_num); - -/* - * Declare any interface-specific control request handlers. These Setup packets - * arrive on the control endpoint (EP0), but are handled by the interface code. - * The callback must prepare the EP0 IN or OUT FIFOs and return the number of - * bytes placed in the IN FIFO. A negative return value will STALL the response - * (and thus indicate error to the host). - */ -#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(struct usb_setup_packet *req) \ - __attribute__ ((alias(STRINGIFY(handler)))) - -#endif /* __CROS_EC_USB_DWC_HW_H */ diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h deleted file mode 100644 index e44002268a..0000000000 --- a/chip/stm32/usb_dwc_i2c.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_DWC_I2C_H -#define __CROS_EC_USB_DWC_I2C_H -#include "usb_i2c.h" - -/* I2C over USB interface. This gets declared in usb_i2c.c */ -extern struct dwc_usb_ep i2c_usb__ep_ctl; - -#endif /* __CROS_EC_USB_DWC_I2C_H */ diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h deleted file mode 100644 index faac9ca775..0000000000 --- a/chip/stm32/usb_dwc_registers.h +++ /dev/null @@ -1,7533 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Register map for STM32F446 USB - */ - -#ifndef __CHIP_STM32_USB_DWC_REGISTERS_H -#define __CHIP_STM32_USB_DWC_REGISTERS_H - -/* Endpoint state */ -struct dwc_usb_ep { - int max_packet; - int tx_fifo; - - int out_pending; - int out_expected; - uint8_t *out_data; - uint8_t *out_databuffer; - int out_databuffer_max; - const struct deferred_data *rx_deferred; - - int in_packets; - int in_pending; - uint8_t *in_data; - uint8_t *in_databuffer; - int in_databuffer_max; - const struct deferred_data *tx_deferred; -}; - -/* USB state */ -enum dwc_usb_speed { - USB_SPEED_FS = 0, - USB_SPEED_HS, -}; - -enum dwc_usb_phy { - USB_PHY_INTERNAL = 0, - USB_PHY_ULPI, -}; - -struct dwc_usb { - struct dwc_usb_ep *ep[USB_EP_COUNT]; - enum dwc_usb_speed speed; - enum dwc_usb_phy phy_type; - int dma_en; - /* IRQ must be STM32_IRQ_OTG_FS / STM32_IRQ_OTG_HS */ - int irq; -}; - -extern struct dwc_usb_ep ep0_ctl; -extern struct dwc_usb usb_ctl; - -/* - * Added Alias Module Family Base Address to 0-instance Module Base Address - * Simplify GBASE(mname) macro - */ -#define GC_MODULE_OFFSET 0x10000 - -#define GBASE(mname) \ - GC_ ## mname ## _BASE_ADDR -#define GOFFSET(mname, rname) \ - GC_ ## mname ## _ ## rname ## _OFFSET - -#define GREG8(mname, rname) \ - REG8(GBASE(mname) + GOFFSET(mname, rname)) -#define GREG32(mname, rname) \ - REG32(GBASE(mname) + GOFFSET(mname, rname)) -#define GREG32_ADDR(mname, rname) \ - REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname)) -#define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value)) -#define GREAD(mname, rname) GREG32(mname, rname) - -#define GFIELD_MASK(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK - -#define GFIELD_LSB(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB - -#define GREAD_FIELD(mname, rname, fname) \ - ((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) - -#define GWRITE_FIELD(mname, rname, fname, fval) \ - (GREG32(mname, rname) = \ - ((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) - - -#define GBASE_I(mname, i) (GBASE(mname) + i*GC_MODULE_OFFSET) - -#define GREG32_I(mname, i, rname) \ - REG32(GBASE_I(mname, i) + GOFFSET(mname, rname)) - -#define GREG32_ADDR_I(mname, i, rname) \ - REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname)) - -#define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value)) -#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname) - -#define GREAD_FIELD_I(mname, i, rname, fname) \ - ((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) - -#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \ - (GREG32_I(mname, i, rname) = \ - ((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) - -/* Replace masked bits with val << lsb */ -#define REG_WRITE_MLV(reg, mask, lsb, val) \ - (reg = ((reg & ~mask) | ((val << lsb) & mask))) - - -/* USB device controller */ -#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off)) -#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET) -#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET) -#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET) -#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET) -#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET) -#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET) -#define GINTSTS(bit) (1 << GC_USB_GINTSTS_ ## bit ## _LSB) -#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET) -#define GINTMSK(bit) (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB) -#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET) -#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET) -#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET) -#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) -/*#define GR_USB_GGPIO GR_USB_REG(GC_USB_GGPIO_OFFSET)*/ -#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) -#define GCCFG_VBDEN BIT(21) -#define GCCFG_PWRDWN BIT(16) -#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) - -#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) -#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET) -#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET) -#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET) -#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET) -#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET) -#define GR_USB_DIEPTXF(n) \ - GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4) -#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET) -#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET) -#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET) -#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET) -#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET) -#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET) -#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET) -#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB)) -#define DAINT_OUTEP(ep) \ - (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB)) -#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) -#define DTHRCTL_TXTHRLEN_6 (0x40 << 2) -#define DTHRCTL_RXTHRLEN_6 (0x40 << 17) -#define DTHRCTL_RXTHREN BIT(16) -#define DTHRCTL_ISOTHREN BIT(1) -#define DTHRCTL_NONISOTHREN BIT(0) -#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) - -#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n) * 0x20 + (off)) -#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n) * 0x20 + (off)) -#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n) -#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n) -#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n) -#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n) -#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n) -#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n) -#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n) -#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n) -#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n) -#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) -#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) - -#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) -#define GOTGCTL_BVALOVAL BIT(7) - -/* Bit 5 */ -#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) -/* Bit 1 */ -#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) -/* HS Burst Len */ -#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) -/* Bit 7 */ -#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) -#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL -#define GAHBCFG_PTXFELVL BIT(8) - -#define GUSBCFG_TOUTCAL(n) (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \ - & GC_USB_GUSBCFG_TOUTCAL_MASK) -#define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ - & GC_USB_GUSBCFG_USBTRDTIM_MASK) -/* Force device mode */ -#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) -#define GUSBCFG_PHYSEL BIT(6) -#define GUSBCFG_SRPCAP BIT(8) -#define GUSBCFG_HNPCAP BIT(9) -#define GUSBCFG_ULPIFSLS BIT(17) -#define GUSBCFG_ULPIAR BIT(18) -#define GUSBCFG_ULPICSM BIT(19) -#define GUSBCFG_ULPIEVBUSD BIT(20) -#define GUSBCFG_ULPIEVBUSI BIT(21) -#define GUSBCFG_TSDPS BIT(22) -#define GUSBCFG_PCCI BIT(23) -#define GUSBCFG_PTCI BIT(24) -#define GUSBCFG_ULPIIPD BIT(25) -#define GUSBCFG_TSDPS BIT(22) - - -#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) -#define GRSTCTL_TXFNUM(n) \ - (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) - -#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVADDR(a) \ - (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) - -#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) - -/* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) - -/* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) - -/* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) - -/* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) - -#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK -#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) -#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) -#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) -#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) - -#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) -#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) -#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB) - -#define DOEPDMA_BS_HOST_RDY (0 << 30) -#define DOEPDMA_BS_DMA_BSY (1 << 30) -#define DOEPDMA_BS_DMA_DONE (2 << 30) -#define DOEPDMA_BS_HOST_BSY (3 << 30) -#define DOEPDMA_BS_MASK (3 << 30) -#define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST BIT(27) -#define DOEPDMA_SP BIT(26) -#define DOEPDMA_IOC BIT(25) -#define DOEPDMA_SR BIT(24) -#define DOEPDMA_MTRF BIT(23) -#define DOEPDMA_NAK BIT(16) -#define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) -#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) - -#define DIEPDMA_BS_HOST_RDY (0 << 30) -#define DIEPDMA_BS_DMA_BSY (1 << 30) -#define DIEPDMA_BS_DMA_DONE (2 << 30) -#define DIEPDMA_BS_HOST_BSY (3 << 30) -#define DIEPDMA_BS_MASK (3 << 30) -#define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST BIT(27) -#define DIEPDMA_SP BIT(26) -#define DIEPDMA_IOC BIT(25) -#define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) -#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) - - - -/* Register defs referenced from DWC block in CR50. This is not a native - * ST block, so we'll use this modified regdefs list. - */ - -#define GC_USB_FS_BASE_ADDR 0x50000000 -#define GC_USB_HS_BASE_ADDR 0x40040000 -#ifdef CONFIG_USB_DWC_FS -#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR -#else -#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR -#endif - -#define GC_USB_GOTGCTL_OFFSET 0x0 -#define GC_USB_GOTGCTL_DEFAULT 0x0 -#define GC_USB_GOTGINT_OFFSET 0x4 -#define GC_USB_GOTGINT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_OFFSET 0x8 -#define GC_USB_GAHBCFG_DEFAULT 0x0 -#define GC_USB_GUSBCFG_OFFSET 0xc -#define GC_USB_GUSBCFG_DEFAULT 0x0 -#define GC_USB_GRSTCTL_OFFSET 0x10 -#define GC_USB_GRSTCTL_DEFAULT 0x0 -#define GC_USB_GINTSTS_OFFSET 0x14 -#define GC_USB_GINTSTS_DEFAULT 0x0 -#define GC_USB_GINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DEFAULT 0x0 -#define GC_USB_GRXSTSR_OFFSET 0x1c -#define GC_USB_GRXSTSR_DEFAULT 0x0 -#define GC_USB_GRXSTSP_OFFSET 0x20 -#define GC_USB_GRXSTSP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_OFFSET 0x24 -#define GC_USB_GRXFSIZ_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 - -#define GC_USB_GCCFG_OFFSET 0x38 -#define GC_USB_GCCFG_DEFAULT 0x0 -#define GC_USB_GUID_OFFSET 0x3c -#define GC_USB_GUID_DEFAULT 0x0 -#define GC_USB_GSNPSID_OFFSET 0x40 -#define GC_USB_GSNPSID_DEFAULT 0x0 -#define GC_USB_GHWCFG1_OFFSET 0x44 -#define GC_USB_GHWCFG1_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OFFSET 0x48 -#define GC_USB_GHWCFG2_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OFFSET 0x4c -#define GC_USB_GHWCFG3_DEFAULT 0x0 -#define GC_USB_GHWCFG4_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_OFFSET 0x104 -#define GC_USB_DIEPTXF1_DEFAULT 0x1000 -#define GC_USB_DIEPTXF2_OFFSET 0x108 -#define GC_USB_DIEPTXF2_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_OFFSET 0x10c -#define GC_USB_DIEPTXF3_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_OFFSET 0x110 -#define GC_USB_DIEPTXF4_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_OFFSET 0x114 -#define GC_USB_DIEPTXF5_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_OFFSET 0x118 -#define GC_USB_DIEPTXF6_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_OFFSET 0x11c -#define GC_USB_DIEPTXF7_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_OFFSET 0x120 -#define GC_USB_DIEPTXF8_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_OFFSET 0x124 -#define GC_USB_DIEPTXF9_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_OFFSET 0x128 -#define GC_USB_DIEPTXF10_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_OFFSET 0x12c -#define GC_USB_DIEPTXF11_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_OFFSET 0x130 -#define GC_USB_DIEPTXF12_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_OFFSET 0x134 -#define GC_USB_DIEPTXF13_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_OFFSET 0x138 -#define GC_USB_DIEPTXF14_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_OFFSET 0x13c -#define GC_USB_DIEPTXF15_DEFAULT 0x0 -#define GC_USB_DCFG_OFFSET 0x800 -#define GC_USB_DCFG_DEFAULT 0x8000000 -#define GC_USB_DCTL_OFFSET 0x804 -#define GC_USB_DCTL_DEFAULT 0x0 -#define GC_USB_DSTS_OFFSET 0x808 -#define GC_USB_DSTS_DEFAULT 0x0 -#define GC_USB_DIEPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_DEFAULT 0x80 -#define GC_USB_DOEPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_DEFAULT 0x0 -#define GC_USB_DAINT_OFFSET 0x818 -#define GC_USB_DAINT_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OFFSET 0x81c -#define GC_USB_DAINTMSK_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DTHRCTL_OFFSET 0x830 -#define GC_USB_DTHRCTL_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_OFFSET 0x900 -#define GC_USB_DIEPCTL0_DEFAULT 0x0 -#define GC_USB_DIEPINT0_OFFSET 0x908 -#define GC_USB_DIEPINT0_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_OFFSET 0x914 -#define GC_USB_DIEPDMA0_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_OFFSET 0x918 -#define GC_USB_DTXFSTS0_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_OFFSET 0x91c -#define GC_USB_DIEPDMAB0_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DEFAULT 0x0 -#define GC_USB_DIEPINT1_OFFSET 0x928 -#define GC_USB_DIEPINT1_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_OFFSET 0x934 -#define GC_USB_DIEPDMA1_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_OFFSET 0x938 -#define GC_USB_DTXFSTS1_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_OFFSET 0x93c -#define GC_USB_DIEPDMAB1_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DEFAULT 0x0 -#define GC_USB_DIEPINT2_OFFSET 0x948 -#define GC_USB_DIEPINT2_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_OFFSET 0x954 -#define GC_USB_DIEPDMA2_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_OFFSET 0x958 -#define GC_USB_DTXFSTS2_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_OFFSET 0x95c -#define GC_USB_DIEPDMAB2_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DEFAULT 0x0 -#define GC_USB_DIEPINT3_OFFSET 0x968 -#define GC_USB_DIEPINT3_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_OFFSET 0x974 -#define GC_USB_DIEPDMA3_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_OFFSET 0x978 -#define GC_USB_DTXFSTS3_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_OFFSET 0x97c -#define GC_USB_DIEPDMAB3_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DEFAULT 0x0 -#define GC_USB_DIEPINT4_OFFSET 0x988 -#define GC_USB_DIEPINT4_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_OFFSET 0x994 -#define GC_USB_DIEPDMA4_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_OFFSET 0x998 -#define GC_USB_DTXFSTS4_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_OFFSET 0x99c -#define GC_USB_DIEPDMAB4_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DEFAULT 0x0 -#define GC_USB_DIEPINT5_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_OFFSET 0x9b4 -#define GC_USB_DIEPDMA5_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_OFFSET 0x9b8 -#define GC_USB_DTXFSTS5_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_OFFSET 0x9bc -#define GC_USB_DIEPDMAB5_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DEFAULT 0x0 -#define GC_USB_DIEPINT6_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_OFFSET 0x9d4 -#define GC_USB_DIEPDMA6_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_OFFSET 0x9d8 -#define GC_USB_DTXFSTS6_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_OFFSET 0x9dc -#define GC_USB_DIEPDMAB6_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DEFAULT 0x0 -#define GC_USB_DIEPINT7_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_OFFSET 0x9f4 -#define GC_USB_DIEPDMA7_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_OFFSET 0x9f8 -#define GC_USB_DTXFSTS7_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_OFFSET 0x9fc -#define GC_USB_DIEPDMAB7_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DEFAULT 0x0 -#define GC_USB_DIEPINT8_OFFSET 0xa08 -#define GC_USB_DIEPINT8_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_OFFSET 0xa14 -#define GC_USB_DIEPDMA8_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_OFFSET 0xa18 -#define GC_USB_DTXFSTS8_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_OFFSET 0xa1c -#define GC_USB_DIEPDMAB8_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DEFAULT 0x0 -#define GC_USB_DIEPINT9_OFFSET 0xa28 -#define GC_USB_DIEPINT9_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_OFFSET 0xa34 -#define GC_USB_DIEPDMA9_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_OFFSET 0xa38 -#define GC_USB_DTXFSTS9_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_OFFSET 0xa3c -#define GC_USB_DIEPDMAB9_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DEFAULT 0x0 -#define GC_USB_DIEPINT10_OFFSET 0xa48 -#define GC_USB_DIEPINT10_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_OFFSET 0xa54 -#define GC_USB_DIEPDMA10_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_OFFSET 0xa58 -#define GC_USB_DTXFSTS10_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_OFFSET 0xa5c -#define GC_USB_DIEPDMAB10_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DEFAULT 0x0 -#define GC_USB_DIEPINT11_OFFSET 0xa68 -#define GC_USB_DIEPINT11_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_OFFSET 0xa74 -#define GC_USB_DIEPDMA11_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_OFFSET 0xa78 -#define GC_USB_DTXFSTS11_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_OFFSET 0xa7c -#define GC_USB_DIEPDMAB11_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DEFAULT 0x0 -#define GC_USB_DIEPINT12_OFFSET 0xa88 -#define GC_USB_DIEPINT12_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_OFFSET 0xa94 -#define GC_USB_DIEPDMA12_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_OFFSET 0xa98 -#define GC_USB_DTXFSTS12_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_OFFSET 0xa9c -#define GC_USB_DIEPDMAB12_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DEFAULT 0x0 -#define GC_USB_DIEPINT13_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_OFFSET 0xab4 -#define GC_USB_DIEPDMA13_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_OFFSET 0xab8 -#define GC_USB_DTXFSTS13_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_OFFSET 0xabc -#define GC_USB_DIEPDMAB13_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DEFAULT 0x0 -#define GC_USB_DIEPINT14_OFFSET 0xac8 -#define GC_USB_DIEPINT14_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_OFFSET 0xad4 -#define GC_USB_DIEPDMA14_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_OFFSET 0xad8 -#define GC_USB_DTXFSTS14_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_OFFSET 0xadc -#define GC_USB_DIEPDMAB14_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DEFAULT 0x0 -#define GC_USB_DIEPINT15_OFFSET 0xae8 -#define GC_USB_DIEPINT15_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_OFFSET 0xaf4 -#define GC_USB_DIEPDMA15_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_OFFSET 0xaf8 -#define GC_USB_DTXFSTS15_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_OFFSET 0xafc -#define GC_USB_DIEPDMAB15_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OFFSET 0xb08 -#define GC_USB_DOEPINT0_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_OFFSET 0xb14 -#define GC_USB_DOEPDMA0_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_OFFSET 0xb1c -#define GC_USB_DOEPDMAB0_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OFFSET 0xb28 -#define GC_USB_DOEPINT1_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_OFFSET 0xb34 -#define GC_USB_DOEPDMA1_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_OFFSET 0xb3c -#define GC_USB_DOEPDMAB1_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OFFSET 0xb48 -#define GC_USB_DOEPINT2_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_OFFSET 0xb54 -#define GC_USB_DOEPDMA2_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_OFFSET 0xb5c -#define GC_USB_DOEPDMAB2_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OFFSET 0xb68 -#define GC_USB_DOEPINT3_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_OFFSET 0xb74 -#define GC_USB_DOEPDMA3_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_OFFSET 0xb7c -#define GC_USB_DOEPDMAB3_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OFFSET 0xb88 -#define GC_USB_DOEPINT4_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_OFFSET 0xb94 -#define GC_USB_DOEPDMA4_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_OFFSET 0xb9c -#define GC_USB_DOEPDMAB4_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OFFSET 0xba8 -#define GC_USB_DOEPINT5_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_OFFSET 0xbb4 -#define GC_USB_DOEPDMA5_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_OFFSET 0xbbc -#define GC_USB_DOEPDMAB5_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_OFFSET 0xbd4 -#define GC_USB_DOEPDMA6_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_OFFSET 0xbdc -#define GC_USB_DOEPDMAB6_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_OFFSET 0xbf4 -#define GC_USB_DOEPDMA7_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_OFFSET 0xbfc -#define GC_USB_DOEPDMAB7_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OFFSET 0xc08 -#define GC_USB_DOEPINT8_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_OFFSET 0xc14 -#define GC_USB_DOEPDMA8_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_OFFSET 0xc1c -#define GC_USB_DOEPDMAB8_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OFFSET 0xc28 -#define GC_USB_DOEPINT9_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_OFFSET 0xc34 -#define GC_USB_DOEPDMA9_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_OFFSET 0xc3c -#define GC_USB_DOEPDMAB9_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OFFSET 0xc48 -#define GC_USB_DOEPINT10_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_OFFSET 0xc54 -#define GC_USB_DOEPDMA10_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_OFFSET 0xc5c -#define GC_USB_DOEPDMAB10_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OFFSET 0xc68 -#define GC_USB_DOEPINT11_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_OFFSET 0xc74 -#define GC_USB_DOEPDMA11_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_OFFSET 0xc7c -#define GC_USB_DOEPDMAB11_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OFFSET 0xc88 -#define GC_USB_DOEPINT12_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_OFFSET 0xc94 -#define GC_USB_DOEPDMA12_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_OFFSET 0xc9c -#define GC_USB_DOEPDMAB12_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OFFSET 0xca8 -#define GC_USB_DOEPINT13_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_OFFSET 0xcb4 -#define GC_USB_DOEPDMA13_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_OFFSET 0xcbc -#define GC_USB_DOEPDMAB13_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_OFFSET 0xcd4 -#define GC_USB_DOEPDMA14_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_OFFSET 0xcdc -#define GC_USB_DOEPDMAB14_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OFFSET 0xce8 -#define GC_USB_DOEPINT15_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_OFFSET 0xcf4 -#define GC_USB_DOEPDMA15_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_OFFSET 0xcfc -#define GC_USB_DOEPDMAB15_DEFAULT 0x0 -#define GC_USB_PCGCCTL_OFFSET 0xe00 -#define GC_USB_PCGCCTL_DEFAULT 0x0 -#define GC_USB_DFIFO_OFFSET 0x20000 -#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 -#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 -#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 -#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 -#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 -#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 -#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 -#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 -#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 -#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 -#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 -#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 -#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 -#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 -#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 -#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 -#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 -#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 -#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 -#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 -#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 -#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 -#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 -#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 -#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 -#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 -#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 -#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 -#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 -#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 -#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 -#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 -#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 -#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 -#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e -#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 -#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 -#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 -#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 -#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 -#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 - -#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 - -#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 -#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 -#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 -#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 -#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 -#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 -#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 -#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 -#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 -#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 -#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 -#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 -#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc - -#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa -#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 -#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 -#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17 -#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 -#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18 -#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 -#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19 -#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 -#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc - -#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20 -#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000 -#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc - -#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21 -#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000 -#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc - -#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc - -#define GC_USB_GUSBCFG_PCCI_LSB 23 -#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) -#define GC_USB_GUSBCFG_PCCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc - -#define GC_USB_GUSBCFG_PTCI_LSB 24 -#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) -#define GC_USB_GUSBCFG_PTCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc - -#define GC_USB_GUSBCFG_ULPIIPD_LSB 25 -#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) -#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc - -#define GC_USB_GUSBCFG_FHMOD_LSB 29 -#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) -#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc - -#define GC_USB_GUSBCFG_FDMOD_LSB 30 -#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) -#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc - -#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 -#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 -#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 -#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 -#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 -#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 -#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 -#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 -#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 -#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 -#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e -#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 -#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 -#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 -#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 -#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f -#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 -#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 -#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 -#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 -#define GC_USB_GINTSTS_CURMOD_LSB 0x0 -#define GC_USB_GINTSTS_CURMOD_MASK 0x1 -#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 -#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 -#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 -#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 -#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 -#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 -#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_OTGINT_LSB 0x2 -#define GC_USB_GINTSTS_OTGINT_MASK 0x4 -#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 -#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 -#define GC_USB_GINTSTS_SOF_LSB 0x3 -#define GC_USB_GINTSTS_SOF_MASK 0x8 -#define GC_USB_GINTSTS_SOF_SIZE 0x1 -#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 -#define GC_USB_GINTSTS_SOF_OFFSET 0x14 -#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 -#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 -#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 -#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 -#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 -#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 -#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 -#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 -#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 -#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa -#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 -#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBSUSP_LSB 0xb -#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 -#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBRST_LSB 0xc -#define GC_USB_GINTSTS_USBRST_MASK 0x1000 -#define GC_USB_GINTSTS_USBRST_SIZE 0x1 -#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 -#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd -#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 -#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 -#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 -#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 -#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe -#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 -#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 -#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 -#define GC_USB_GINTSTS_EOPF_LSB 0xf -#define GC_USB_GINTSTS_EOPF_MASK 0x8000 -#define GC_USB_GINTSTS_EOPF_SIZE 0x1 -#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 -#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 -#define GC_USB_GINTSTS_EPMIS_LSB 0x11 -#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 -#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 -#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_IEPINT_LSB 0x12 -#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 -#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_OEPINT_LSB 0x13 -#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 -#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 -#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 -#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 -#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 -#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 -#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 -#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_RESETDET_LSB 0x17 -#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 -#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 -#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 -#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 -#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c -#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 -#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 -#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 -#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 -#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e -#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 -#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 -#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 -#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f -#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 -#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 -#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 -#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 -#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 -#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 -#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 -#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 -#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 -#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 -#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 -#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 -#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 -#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 -#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 -#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa -#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 -#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb -#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 -#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc -#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 -#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd -#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 -#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe -#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf -#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 -#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 -#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 -#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 -#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 -#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 -#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 -#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 -#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 -#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 -#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 -#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 -#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 -#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 -#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 -#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 -#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d -#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 -#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e -#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 -#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f -#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 -#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 -#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSR_CHNUM_MASK 0xf -#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c -#define GC_USB_GRXSTSR_BCNT_LSB 0x4 -#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSR_BCNT_SIZE 0xb -#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c -#define GC_USB_GRXSTSR_DPID_LSB 0xf -#define GC_USB_GRXSTSR_DPID_MASK 0x18000 -#define GC_USB_GRXSTSR_DPID_SIZE 0x2 -#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c -#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c -#define GC_USB_GRXSTSR_FN_LSB 0x15 -#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSR_FN_SIZE 0x4 -#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSR_FN_OFFSET 0x1c -#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSP_CHNUM_MASK 0xf -#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 -#define GC_USB_GRXSTSP_BCNT_LSB 0x4 -#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSP_BCNT_SIZE 0xb -#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 -#define GC_USB_GRXSTSP_DPID_LSB 0xf -#define GC_USB_GRXSTSP_DPID_MASK 0x18000 -#define GC_USB_GRXSTSP_DPID_SIZE 0x2 -#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 -#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 -#define GC_USB_GRXSTSP_FN_LSB 0x15 -#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSP_FN_SIZE 0x4 -#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSP_FN_OFFSET 0x20 -#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff -#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb -#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 - -#define GC_USB_GUID_GUID_LSB 0x0 -#define GC_USB_GUID_GUID_MASK 0xffffffff -#define GC_USB_GUID_GUID_SIZE 0x20 -#define GC_USB_GUID_GUID_DEFAULT 0x0 -#define GC_USB_GUID_GUID_OFFSET 0x3c -#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff -#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 -#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 -#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 -#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff -#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 -#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 -#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 -#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 -#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 -#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 -#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 -#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 -#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 -#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 -#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 -#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 -#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 -#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 -#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 -#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 -#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 -#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 -#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 -#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa -#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 -#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe -#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 -#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 -#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 -#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 -#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 -#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 -#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 -#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 -#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 -#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a -#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 -#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 -#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 -#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 -#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 -#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c -#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 -#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 -#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 -#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 -#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c -#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 -#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 -#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 -#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c -#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa -#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 -#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 -#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c -#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb -#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 -#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 -#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c -#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc -#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 -#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd -#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 -#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe -#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 -#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf -#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 -#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 -#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 -#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 -#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 -#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 -#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 -#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 -#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 -#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 -#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 -#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 -#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 -#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 -#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe -#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 -#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 -#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 -#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 -#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 -#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 -#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 -#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 -#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 -#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 -#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 -#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 -#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 -#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 -#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 -#define GC_USB_GHWCFG4_INEPS_LSB 0x1a -#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 -#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e -#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 -#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f -#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 -#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff -#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 -#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc -#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 -#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c -#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c -#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c -#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c -#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c -#define GC_USB_DCFG_DEVSPD_LSB 0x0 -#define GC_USB_DCFG_DEVSPD_MASK 0x3 -#define GC_USB_DCFG_DEVSPD_SIZE 0x2 -#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 -#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 -#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 -#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 -#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 -#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 -#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 -#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 -#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 -#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 -#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 -#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 -#define GC_USB_DCFG_DEVADDR_LSB 0x4 -#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 -#define GC_USB_DCFG_DEVADDR_SIZE 0x7 -#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 -#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 -#define GC_USB_DCFG_PERFRINT_LSB 0xb -#define GC_USB_DCFG_PERFRINT_MASK 0x1800 -#define GC_USB_DCFG_PERFRINT_SIZE 0x2 -#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 -#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 -#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd -#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 -#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 -#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 -#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 -#define GC_USB_DCFG_XCVRDLY_LSB 0xe -#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 -#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 -#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 -#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 -#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf -#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 -#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 -#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 -#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 -#define GC_USB_DCFG_DESCDMA_LSB 0x17 -#define GC_USB_DCFG_DESCDMA_MASK 0x800000 -#define GC_USB_DCFG_DESCDMA_SIZE 0x1 -#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 -#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 -#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 -#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 -#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 -#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 -#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 -#define GC_USB_DCFG_RESVALID_LSB 0x1a -#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 -#define GC_USB_DCFG_RESVALID_SIZE 0x6 -#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 -#define GC_USB_DCFG_RESVALID_OFFSET 0x800 -#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 -#define GC_USB_DCTL_SFTDISCON_LSB 0x1 -#define GC_USB_DCTL_SFTDISCON_MASK 0x2 -#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 -#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 -#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 -#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 -#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 -#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 -#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 -#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_TSTCTL_LSB 0x4 -#define GC_USB_DCTL_TSTCTL_MASK 0x70 -#define GC_USB_DCTL_TSTCTL_SIZE 0x3 -#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 -#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 -#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 -#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 -#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 -#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 -#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 -#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 -#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGOUTNAK_LSB 0xa -#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 -#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb -#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 -#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 -#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 -#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 -#define GC_USB_DCTL_GMC_LSB 0xd -#define GC_USB_DCTL_GMC_MASK 0x6000 -#define GC_USB_DCTL_GMC_SIZE 0x2 -#define GC_USB_DCTL_GMC_DEFAULT 0x0 -#define GC_USB_DCTL_GMC_OFFSET 0x804 -#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf -#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 -#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 -#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 -#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 -#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 -#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 -#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 -#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 -#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 -#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 -#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 -#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 -#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 -#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 -#define GC_USB_DSTS_SUSPSTS_LSB 0x0 -#define GC_USB_DSTS_SUSPSTS_MASK 0x1 -#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 -#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 -#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 -#define GC_USB_DSTS_ENUMSPD_LSB 0x1 -#define GC_USB_DSTS_ENUMSPD_MASK 0x6 -#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 -#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 -#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 -#define GC_USB_DSTS_ERRTICERR_LSB 0x3 -#define GC_USB_DSTS_ERRTICERR_MASK 0x8 -#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 -#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 -#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 -#define GC_USB_DSTS_SOFFN_LSB 0x8 -#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 -#define GC_USB_DSTS_SOFFN_SIZE 0xe -#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 -#define GC_USB_DSTS_SOFFN_OFFSET 0x808 -#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 -#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 -#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 -#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 -#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 -#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 -#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 -#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 -#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 -#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 -#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 -#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 -#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 -#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 -#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc -#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 -#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe -#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 -#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 -#define GC_USB_DAINT_INEPINT0_LSB 0x0 -#define GC_USB_DAINT_INEPINT0_MASK 0x1 -#define GC_USB_DAINT_INEPINT0_SIZE 0x1 -#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT1_LSB 0x1 -#define GC_USB_DAINT_INEPINT1_MASK 0x2 -#define GC_USB_DAINT_INEPINT1_SIZE 0x1 -#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT2_LSB 0x2 -#define GC_USB_DAINT_INEPINT2_MASK 0x4 -#define GC_USB_DAINT_INEPINT2_SIZE 0x1 -#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT3_LSB 0x3 -#define GC_USB_DAINT_INEPINT3_MASK 0x8 -#define GC_USB_DAINT_INEPINT3_SIZE 0x1 -#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT4_LSB 0x4 -#define GC_USB_DAINT_INEPINT4_MASK 0x10 -#define GC_USB_DAINT_INEPINT4_SIZE 0x1 -#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT5_LSB 0x5 -#define GC_USB_DAINT_INEPINT5_MASK 0x20 -#define GC_USB_DAINT_INEPINT5_SIZE 0x1 -#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT6_LSB 0x6 -#define GC_USB_DAINT_INEPINT6_MASK 0x40 -#define GC_USB_DAINT_INEPINT6_SIZE 0x1 -#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT7_LSB 0x7 -#define GC_USB_DAINT_INEPINT7_MASK 0x80 -#define GC_USB_DAINT_INEPINT7_SIZE 0x1 -#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT8_LSB 0x8 -#define GC_USB_DAINT_INEPINT8_MASK 0x100 -#define GC_USB_DAINT_INEPINT8_SIZE 0x1 -#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT9_LSB 0x9 -#define GC_USB_DAINT_INEPINT9_MASK 0x200 -#define GC_USB_DAINT_INEPINT9_SIZE 0x1 -#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT10_LSB 0xa -#define GC_USB_DAINT_INEPINT10_MASK 0x400 -#define GC_USB_DAINT_INEPINT10_SIZE 0x1 -#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT11_LSB 0xb -#define GC_USB_DAINT_INEPINT11_MASK 0x800 -#define GC_USB_DAINT_INEPINT11_SIZE 0x1 -#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT12_LSB 0xc -#define GC_USB_DAINT_INEPINT12_MASK 0x1000 -#define GC_USB_DAINT_INEPINT12_SIZE 0x1 -#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT13_LSB 0xd -#define GC_USB_DAINT_INEPINT13_MASK 0x2000 -#define GC_USB_DAINT_INEPINT13_SIZE 0x1 -#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT14_LSB 0xe -#define GC_USB_DAINT_INEPINT14_MASK 0x4000 -#define GC_USB_DAINT_INEPINT14_SIZE 0x1 -#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT15_LSB 0xf -#define GC_USB_DAINT_INEPINT15_MASK 0x8000 -#define GC_USB_DAINT_INEPINT15_SIZE 0x1 -#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 -#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 -#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 -#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 -#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 -#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 -#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 -#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 -#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 -#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 -#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 -#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 -#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 -#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 -#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 -#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 -#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 -#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 -#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 -#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 -#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a -#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 -#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b -#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 -#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c -#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 -#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d -#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 -#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e -#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 -#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f -#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 -#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 -#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 -#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 -#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 -#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 -#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 -#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 -#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 -#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 -#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 -#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 -#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 -#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 -#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 -#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 -#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 -#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 -#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 -#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa -#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 -#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb -#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 -#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc -#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 -#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd -#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 -#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe -#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 -#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf -#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 -#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 -#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 -#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 -#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 -#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 -#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 -#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 -#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 -#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 -#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 -#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 -#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 -#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 -#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 -#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 -#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 -#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 -#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 -#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 -#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 -#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a -#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 -#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b -#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 -#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c -#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 -#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d -#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 -#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e -#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 -#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f -#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 -#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c -#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff -#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 -#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff -#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc -#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 -#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 -#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc -#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb -#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 -#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 -#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 -#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 -#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 -#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 -#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 -#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b -#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 -#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 -#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPCTL0_MPS_LSB 0x0 -#define GC_USB_DIEPCTL0_MPS_MASK 0x3 -#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 -#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 -#define GC_USB_DIEPCTL0_STALL_LSB 0x15 -#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 -#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 -#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 -#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 -#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 -#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 -#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 -#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 -#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 -#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 -#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 -#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 -#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 -#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 -#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c -#define GC_USB_DIEPCTL1_MPS_LSB 0x0 -#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL1_MPS_SIZE 0xb -#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DPID_LSB 0x10 -#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 -#define GC_USB_DIEPCTL1_STALL_LSB 0x15 -#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 -#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 -#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 -#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 -#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 -#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 -#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 -#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 -#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 -#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 -#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 -#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 -#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c -#define GC_USB_DIEPCTL2_MPS_LSB 0x0 -#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL2_MPS_SIZE 0xb -#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DPID_LSB 0x10 -#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 -#define GC_USB_DIEPCTL2_STALL_LSB 0x15 -#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 -#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 -#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 -#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 -#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 -#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 -#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 -#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 -#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 -#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 -#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 -#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 -#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c -#define GC_USB_DIEPCTL3_MPS_LSB 0x0 -#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL3_MPS_SIZE 0xb -#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DPID_LSB 0x10 -#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 -#define GC_USB_DIEPCTL3_STALL_LSB 0x15 -#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 -#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 -#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 -#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 -#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 -#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 -#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 -#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 -#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 -#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 -#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 -#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 -#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c -#define GC_USB_DIEPCTL4_MPS_LSB 0x0 -#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL4_MPS_SIZE 0xb -#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DPID_LSB 0x10 -#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 -#define GC_USB_DIEPCTL4_STALL_LSB 0x15 -#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 -#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 -#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 -#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 -#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 -#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 -#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 -#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 -#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 -#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 -#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 -#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 -#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c -#define GC_USB_DIEPCTL5_MPS_LSB 0x0 -#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL5_MPS_SIZE 0xb -#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DPID_LSB 0x10 -#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_STALL_LSB 0x15 -#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 -#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 -#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc -#define GC_USB_DIEPCTL6_MPS_LSB 0x0 -#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL6_MPS_SIZE 0xb -#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DPID_LSB 0x10 -#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_STALL_LSB 0x15 -#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 -#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 -#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc -#define GC_USB_DIEPCTL7_MPS_LSB 0x0 -#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL7_MPS_SIZE 0xb -#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DPID_LSB 0x10 -#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_STALL_LSB 0x15 -#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 -#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 -#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc -#define GC_USB_DIEPCTL8_MPS_LSB 0x0 -#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL8_MPS_SIZE 0xb -#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DPID_LSB 0x10 -#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_STALL_LSB 0x15 -#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 -#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 -#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 -#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 -#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c -#define GC_USB_DIEPCTL9_MPS_LSB 0x0 -#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL9_MPS_SIZE 0xb -#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DPID_LSB 0x10 -#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_STALL_LSB 0x15 -#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 -#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 -#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 -#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 -#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c -#define GC_USB_DIEPCTL10_MPS_LSB 0x0 -#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL10_MPS_SIZE 0xb -#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DPID_LSB 0x10 -#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_STALL_LSB 0x15 -#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 -#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 -#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 -#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 -#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c -#define GC_USB_DIEPCTL11_MPS_LSB 0x0 -#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL11_MPS_SIZE 0xb -#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DPID_LSB 0x10 -#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_STALL_LSB 0x15 -#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 -#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 -#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 -#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 -#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c -#define GC_USB_DIEPCTL12_MPS_LSB 0x0 -#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL12_MPS_SIZE 0xb -#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DPID_LSB 0x10 -#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_STALL_LSB 0x15 -#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 -#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 -#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 -#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 -#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c -#define GC_USB_DIEPCTL13_MPS_LSB 0x0 -#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL13_MPS_SIZE 0xb -#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DPID_LSB 0x10 -#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_STALL_LSB 0x15 -#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 -#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 -#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc -#define GC_USB_DIEPCTL14_MPS_LSB 0x0 -#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL14_MPS_SIZE 0xb -#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DPID_LSB 0x10 -#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_STALL_LSB 0x15 -#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 -#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 -#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 -#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 -#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc -#define GC_USB_DIEPCTL15_MPS_LSB 0x0 -#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL15_MPS_SIZE 0xb -#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DPID_LSB 0x10 -#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_STALL_LSB 0x15 -#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 -#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 -#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 -#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 -#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc -#define GC_USB_DOEPCTL0_MPS_LSB 0x0 -#define GC_USB_DOEPCTL0_MPS_MASK 0x3 -#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNP_LSB 0x14 -#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_STALL_LSB 0x15 -#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 -#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 -#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_SETUP_LSB 0x3 -#define GC_USB_DOEPINT0_SETUP_MASK 0x8 -#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 -#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 -#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 -#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d -#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 -#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 -#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 -#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c -#define GC_USB_DOEPCTL1_MPS_LSB 0x0 -#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL1_MPS_SIZE 0xb -#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DPID_LSB 0x10 -#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNP_LSB 0x14 -#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_STALL_LSB 0x15 -#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 -#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 -#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_SETUP_LSB 0x3 -#define GC_USB_DOEPINT1_SETUP_MASK 0x8 -#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 -#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 -#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c -#define GC_USB_DOEPCTL2_MPS_LSB 0x0 -#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL2_MPS_SIZE 0xb -#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DPID_LSB 0x10 -#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNP_LSB 0x14 -#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_STALL_LSB 0x15 -#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 -#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 -#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_SETUP_LSB 0x3 -#define GC_USB_DOEPINT2_SETUP_MASK 0x8 -#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 -#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 -#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c -#define GC_USB_DOEPCTL3_MPS_LSB 0x0 -#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL3_MPS_SIZE 0xb -#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DPID_LSB 0x10 -#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNP_LSB 0x14 -#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_STALL_LSB 0x15 -#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 -#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 -#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_SETUP_LSB 0x3 -#define GC_USB_DOEPINT3_SETUP_MASK 0x8 -#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 -#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 -#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c -#define GC_USB_DOEPCTL4_MPS_LSB 0x0 -#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL4_MPS_SIZE 0xb -#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DPID_LSB 0x10 -#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNP_LSB 0x14 -#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_STALL_LSB 0x15 -#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 -#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 -#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_SETUP_LSB 0x3 -#define GC_USB_DOEPINT4_SETUP_MASK 0x8 -#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 -#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 -#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c -#define GC_USB_DOEPCTL5_MPS_LSB 0x0 -#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL5_MPS_SIZE 0xb -#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DPID_LSB 0x10 -#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNP_LSB 0x14 -#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_STALL_LSB 0x15 -#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 -#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 -#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_SETUP_LSB 0x3 -#define GC_USB_DOEPINT5_SETUP_MASK 0x8 -#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 -#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 -#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc -#define GC_USB_DOEPCTL6_MPS_LSB 0x0 -#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL6_MPS_SIZE 0xb -#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DPID_LSB 0x10 -#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNP_LSB 0x14 -#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_STALL_LSB 0x15 -#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 -#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_SETUP_LSB 0x3 -#define GC_USB_DOEPINT6_SETUP_MASK 0x8 -#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 -#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 -#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc -#define GC_USB_DOEPCTL7_MPS_LSB 0x0 -#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL7_MPS_SIZE 0xb -#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DPID_LSB 0x10 -#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNP_LSB 0x14 -#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_STALL_LSB 0x15 -#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 -#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_SETUP_LSB 0x3 -#define GC_USB_DOEPINT7_SETUP_MASK 0x8 -#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 -#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 -#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc -#define GC_USB_DOEPCTL8_MPS_LSB 0x0 -#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL8_MPS_SIZE 0xb -#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DPID_LSB 0x10 -#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNP_LSB 0x14 -#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_STALL_LSB 0x15 -#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 -#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 -#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_SETUP_LSB 0x3 -#define GC_USB_DOEPINT8_SETUP_MASK 0x8 -#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 -#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 -#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c -#define GC_USB_DOEPCTL9_MPS_LSB 0x0 -#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL9_MPS_SIZE 0xb -#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DPID_LSB 0x10 -#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNP_LSB 0x14 -#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_STALL_LSB 0x15 -#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 -#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 -#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_SETUP_LSB 0x3 -#define GC_USB_DOEPINT9_SETUP_MASK 0x8 -#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 -#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 -#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c -#define GC_USB_DOEPCTL10_MPS_LSB 0x0 -#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL10_MPS_SIZE 0xb -#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DPID_LSB 0x10 -#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNP_LSB 0x14 -#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_STALL_LSB 0x15 -#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 -#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 -#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_SETUP_LSB 0x3 -#define GC_USB_DOEPINT10_SETUP_MASK 0x8 -#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 -#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 -#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c -#define GC_USB_DOEPCTL11_MPS_LSB 0x0 -#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL11_MPS_SIZE 0xb -#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DPID_LSB 0x10 -#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNP_LSB 0x14 -#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_STALL_LSB 0x15 -#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 -#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 -#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_SETUP_LSB 0x3 -#define GC_USB_DOEPINT11_SETUP_MASK 0x8 -#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 -#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 -#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c -#define GC_USB_DOEPCTL12_MPS_LSB 0x0 -#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL12_MPS_SIZE 0xb -#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DPID_LSB 0x10 -#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNP_LSB 0x14 -#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_STALL_LSB 0x15 -#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 -#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 -#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_SETUP_LSB 0x3 -#define GC_USB_DOEPINT12_SETUP_MASK 0x8 -#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 -#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 -#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c -#define GC_USB_DOEPCTL13_MPS_LSB 0x0 -#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL13_MPS_SIZE 0xb -#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DPID_LSB 0x10 -#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNP_LSB 0x14 -#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_STALL_LSB 0x15 -#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 -#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 -#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_SETUP_LSB 0x3 -#define GC_USB_DOEPINT13_SETUP_MASK 0x8 -#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 -#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 -#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc -#define GC_USB_DOEPCTL14_MPS_LSB 0x0 -#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL14_MPS_SIZE 0xb -#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DPID_LSB 0x10 -#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNP_LSB 0x14 -#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_STALL_LSB 0x15 -#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 -#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_SETUP_LSB 0x3 -#define GC_USB_DOEPINT14_SETUP_MASK 0x8 -#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 -#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 -#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc -#define GC_USB_DOEPCTL15_MPS_LSB 0x0 -#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL15_MPS_SIZE 0xb -#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DPID_LSB 0x10 -#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNP_LSB 0x14 -#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_STALL_LSB 0x15 -#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 -#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 -#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_SETUP_LSB 0x3 -#define GC_USB_DOEPINT15_SETUP_MASK 0x8 -#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 -#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 -#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc -#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2 -#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2 -#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4 -#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1 -#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6 -#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40 -#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1 -#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7 -#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80 -#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1 -#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0 -#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00 -#define GC_USB_DFIFO_SIZE 0x1000 - - -#endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */ diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c deleted file mode 100644 index 2f20d88dda..0000000000 --- a/chip/stm32/usb_dwc_stream.c +++ /dev/null @@ -1,99 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "registers.h" -#include "timer.h" -#include "usb_dwc_stream.h" -#include "util.h" - -#include "console.h" -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -/* - * This function tries to shove new bytes from the USB host into the queue for - * consumption elsewhere. It is invoked either by a HW interrupt (telling us we - * have new bytes from the USB host), or by whoever is reading bytes out of the - * other end of the queue (telling us that there's now more room in the queue - * if we still have bytes to shove in there). - */ -int rx_stream_handler(struct usb_stream_config const *config) -{ - int rx_count = rx_ep_pending(config->endpoint); - - /* If we have some, try to shove them into the queue */ - if (rx_count) { - size_t added = QUEUE_ADD_UNITS( - config->producer.queue, config->rx_ram, - rx_count); - if (added != rx_count) { - CPRINTF("rx_stream_handler: failed ep%d " - "queue %d bytes, accepted %d\n", - config->endpoint, rx_count, added); - } - } - - if (!rx_ep_is_active(config->endpoint)) - usb_read_ep(config->endpoint, config->rx_size, config->rx_ram); - - return rx_count; -} - -/* Try to send some bytes to the host */ -int tx_stream_handler(struct usb_stream_config const *config) -{ - size_t count; - - if (!*(config->is_reset)) - return 0; - if (!tx_ep_is_ready(config->endpoint)) - return 0; - - count = QUEUE_REMOVE_UNITS(config->consumer.queue, config->tx_ram, - config->tx_size); - if (count) - usb_write_ep(config->endpoint, count, config->tx_ram); - - return count; -} - -/* Reset stream */ -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - epN_reset(config->endpoint); - - *(config->is_reset) = 1; - - /* Flush any queued data */ - hook_call_deferred(config->deferred_tx, 0); - hook_call_deferred(config->deferred_rx, 0); -} - -static void usb_read(struct producer const *producer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(producer, struct usb_stream_config, producer); - - hook_call_deferred(config->deferred_rx, 0); -} - -static void usb_written(struct consumer const *consumer, size_t count) -{ - struct usb_stream_config const *config = - DOWNCAST(consumer, struct usb_stream_config, consumer); - - hook_call_deferred(config->deferred_tx, 0); -} - -struct producer_ops const usb_stream_producer_ops = { - .read = usb_read, -}; - -struct consumer_ops const usb_stream_consumer_ops = { - .written = usb_written, -}; diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h deleted file mode 100644 index e46e7a929c..0000000000 --- a/chip/stm32/usb_dwc_stream.h +++ /dev/null @@ -1,237 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_DWC_STREAM_H -#define __CROS_EC_USB_DWC_STREAM_H - -/* USB STREAM driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "consumer.h" -#include "hooks.h" -#include "registers.h" -#include "producer.h" -#include "queue.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* - * Compile time Per-USB stream configuration stored in flash. Instances of this - * structure are provided by the user of the USB stream. This structure binds - * together all information required to operate a USB stream. - */ -struct usb_stream_config { - /* - * Endpoint index, and pointers to the USB packet RAM buffers. - */ - int endpoint; - struct dwc_usb_ep *ep; - - int *is_reset; - int *overflow; - - /* - * Deferred function to call to handle USB and Queue request. - */ - const struct deferred_data *deferred_tx; - const struct deferred_data *deferred_rx; - - int tx_size; - int rx_size; - - uint8_t *tx_ram; - uint8_t *rx_ram; - - struct consumer consumer; - struct producer producer; -}; - -/* - * These function tables are defined by the USB Stream driver and are used to - * initialize the consumer and producer in the usb_stream_config. - */ -extern struct consumer_ops const usb_stream_consumer_ops; -extern struct producer_ops const usb_stream_producer_ops; - - -/* - * Convenience macro for defining USB streams and their associated state and - * buffers. - * - * NAME is used to construct the names of the packet RAM buffers, trampoline - * functions, usb_stream_state struct, and usb_stream_config struct, the - * latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * stream. - * - * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the - * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields - * respectively in the USB interface descriptor. - * - * INTERFACE_NAME is the index of the USB string descriptor (iInterface). - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - * - * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate - * for the RX and TX packets respectively. The valid values for these - * parameters are dictated by the USB peripheral. - * - * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver - * should write to and read from respectively. - */ - -/* - * The following assertions can not be made because they require access to - * non-const fields, but should be kept in mind. - * - * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE); - * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE); - * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); - * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); - */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE]; \ - static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE]; \ - static int CONCAT2(NAME, _is_reset_); \ - static int CONCAT2(NAME, _overflow_); \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ - struct usb_stream_config const NAME = { \ - .endpoint = ENDPOINT, \ - .is_reset = &CONCAT2(NAME, _is_reset_), \ - .overflow = &CONCAT2(NAME, _overflow_), \ - .deferred_tx = &CONCAT2(NAME, _deferred_tx__data), \ - .deferred_rx = &CONCAT2(NAME, _deferred_rx__data), \ - .tx_size = TX_SIZE, \ - .rx_size = RX_SIZE, \ - .tx_ram = CONCAT2(NAME, _buf_tx_), \ - .rx_ram = CONCAT2(NAME, _buf_rx_), \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &usb_stream_consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &usb_stream_producer_ops, \ - }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { tx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { rx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_epN_tx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_epN_rx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_expected = 0, \ - .out_data = 0, \ - .out_databuffer = CONCAT2(NAME, _buf_rx_), \ - .out_databuffer_max = RX_SIZE, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = CONCAT2(NAME, _buf_tx_), \ - .in_databuffer_max = TX_SIZE, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)); - -/* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) - -/* - * Handle USB and Queue request in a deferred callback. - */ -int rx_stream_handler(struct usb_stream_config const *config); -int tx_stream_handler(struct usb_stream_config const *config); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB stream driver. - */ -void usb_stream_tx(struct usb_stream_config const *config); -void usb_stream_rx(struct usb_stream_config const *config); -void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt); - -#endif /* __CROS_EC_USB_STREAM_H */ diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h deleted file mode 100644 index 6d79f3aca9..0000000000 --- a/chip/stm32/usb_dwc_update.h +++ /dev/null @@ -1,10 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_STM32_USB_DWC_UPDATE_H -#define __CROS_EC_STM32_USB_DWC_UPDATE_H - -extern struct dwc_usb_ep usb_update_ep_ctl; - -#endif /* __CROS_EC_STM32_USB_DWC_UPDATE_H */ diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c deleted file mode 100644 index 85952a1387..0000000000 --- a/chip/stm32/usb_endpoints.c +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * USB endpoints/interfaces callbacks declaration - */ - -#include <stdint.h> -#include <stddef.h> -#include "config.h" -#include "common.h" -#include "usb_hw.h" - -typedef void (*xfer_func)(void); -typedef void (*evt_func) (enum usb_ep_event evt); - -#if defined(CHIP_FAMILY_STM32F4) -#define iface_arguments struct usb_setup_packet *req -#else -#define iface_arguments usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx -#endif -typedef int (*iface_func)(iface_arguments); - -#ifndef PASS -#define PASS 1 -#endif - -#if PASS == 1 -void ep_undefined(void) -{ - return; -} - -void ep_evt_undefined(enum usb_ep_event evt) -{ - return; -} - -/* Undefined interface callbacks fail by returning non-zero*/ -int iface_undefined(iface_arguments) -{ - return 1; -} - -#define table(type, name, x) x - -#define endpoint_tx(number) \ - extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _tx(void); -#define endpoint_rx(number) \ - extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _rx(void); -#define endpoint_evt(number) \ - extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \ - ep_ ## number ## _evt(enum usb_ep_event evt); -#define interface(number) \ - extern int __attribute__((used, weak, alias("iface_undefined"))) \ - iface_ ## number ## _request(iface_arguments); - -#define null - -#endif /* PASS 1 */ - -#if PASS == 2 -#undef table -#undef endpoint_tx -#undef endpoint_rx -#undef endpoint_evt -#undef interface -#undef null - -/* align function pointers on a 32-bit boundary */ -#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x }; -#define null (void*)0 - -#define ep_(num, suf) CONCAT3(ep_, num, suf) -#define ep(num, suf) ep_(num, suf) - -#define endpoint_tx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx, -#define endpoint_rx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx, -#define endpoint_evt(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt, -#define interface(number) \ - [number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request, -#endif /* PASS 2 */ - -/* - * The initializers are listed backwards, but that's so that the items beyond - * the chip's limit are first assigned to the last field, then overwritten by - * its actual value due to the designated initializers in the macros above. - * It all sorts out nicely - */ -table(xfer_func, usb_ep_tx, - endpoint_tx(15) - endpoint_tx(14) - endpoint_tx(13) - endpoint_tx(12) - endpoint_tx(11) - endpoint_tx(10) - endpoint_tx(9) - endpoint_tx(8) - endpoint_tx(7) - endpoint_tx(6) - endpoint_tx(5) - endpoint_tx(4) - endpoint_tx(3) - endpoint_tx(2) - endpoint_tx(1) - endpoint_tx(0) -) - -table(xfer_func, usb_ep_rx, - endpoint_rx(15) - endpoint_rx(14) - endpoint_rx(13) - endpoint_rx(12) - endpoint_rx(11) - endpoint_rx(10) - endpoint_rx(9) - endpoint_rx(8) - endpoint_rx(7) - endpoint_rx(6) - endpoint_rx(5) - endpoint_rx(4) - endpoint_rx(3) - endpoint_rx(2) - endpoint_rx(1) - endpoint_rx(0) -) - -table(evt_func, usb_ep_event, - endpoint_evt(15) - endpoint_evt(14) - endpoint_evt(13) - endpoint_evt(12) - endpoint_evt(11) - endpoint_evt(10) - endpoint_evt(9) - endpoint_evt(8) - endpoint_evt(7) - endpoint_evt(6) - endpoint_evt(5) - endpoint_evt(4) - endpoint_evt(3) - endpoint_evt(2) - endpoint_evt(1) - endpoint_evt(0) -) - -#if USB_IFACE_COUNT > 0 -table(iface_func, usb_iface_request, - interface(7) - interface(6) - interface(5) - interface(4) - interface(3) - interface(2) - interface(1) - interface(0) -) -#endif - -#if PASS == 1 -#undef PASS -#define PASS 2 -#include "usb_endpoints.c" -#endif diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c deleted file mode 100644 index 64d46875b5..0000000000 --- a/chip/stm32/usb_gpio.c +++ /dev/null @@ -1,89 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "gpio.h" -#include "link_defs.h" -#include "registers.h" -#include "usb_gpio.h" - -void usb_gpio_tx(struct usb_gpio_config const *config) -{ - size_t i; - uint32_t mask = 1; - uint32_t value = 0; - - for (i = 0; i < config->num_gpios; ++i, mask <<= 1) - value |= (gpio_get_level(config->gpios[i])) ? mask : 0; - - config->tx_ram[0] = value; - config->tx_ram[1] = value >> 16; - - btable_ep[config->endpoint].tx_count = USB_GPIO_TX_PACKET_SIZE; - - /* - * TX packet updated, mark the packet as VALID. - */ - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0); -} - -void usb_gpio_rx(struct usb_gpio_config const *config) -{ - size_t i; - uint32_t mask = 1; - uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) | - (uint32_t)(config->rx_ram[1]) << 16); - uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) | - (uint32_t)(config->rx_ram[3]) << 16); - uint32_t ignore_mask = set_mask & clear_mask; - - config->state->set_mask = set_mask; - config->state->clear_mask = clear_mask; - - if ((btable_ep[config->endpoint].rx_count & RX_COUNT_MASK) == - USB_GPIO_RX_PACKET_SIZE) { - for (i = 0; i < config->num_gpios; ++i, mask <<= 1) { - if (ignore_mask & mask) - ; - else if (set_mask & mask) - gpio_set_level(config->gpios[i], 1); - else if (clear_mask & mask) - gpio_set_level(config->gpios[i], 0); - } - } - - /* - * RX packet consumed, mark the packet as VALID. - */ - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); -} - -void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt) -{ - int i; - - if (evt != USB_EVENT_RESET) - return; - - i = config->endpoint; - - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); - btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE; - - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); - btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10); - - /* - * Initialize TX buffer with zero, the first IN transaction will fill - * this in with a valid value. - */ - config->tx_ram[0] = 0; - config->tx_ram[1] = 0; - - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (3 << 4) | /* TX Valid */ - (0 << 9) | /* Bulk EP */ - (3 << 12)); /* RX Valid */ -} diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h deleted file mode 100644 index b27c7f9485..0000000000 --- a/chip/stm32/usb_gpio.h +++ /dev/null @@ -1,130 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_GPIO_H -#define __CROS_EC_USB_GPIO_H - -/* STM32 USB GPIO driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -struct usb_gpio_state { - uint32_t set_mask; - uint32_t clear_mask; -}; - -/* - * Compile time Per-USB gpio configuration stored in flash. Instances of this - * structure are provided by the user of the USB gpio. This structure binds - * together all information required to operate a USB gpio. - */ -struct usb_gpio_config { - struct usb_gpio_state *state; - - /* - * Endpoint index, and pointers to the USB packet RAM buffers. - */ - int endpoint; - - usb_uint *rx_ram; - usb_uint *tx_ram; - - /* - * GPIO list - */ - enum gpio_signal const *gpios; - size_t num_gpios; -}; - -#define USB_GPIO_RX_PACKET_SIZE 8 -#define USB_GPIO_TX_PACKET_SIZE 4 - -/* - * Convenience macro for defining a USB GPIO driver and its associated state. - * - * NAME is used to construct the names of the trampoline functions, - * usb_gpio_state struct, and usb_gpio_config struct, the latter is just - * called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * GPIO driver. - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - */ -#define USB_GPIO_CONFIG(NAME, \ - GPIO_LIST, \ - INTERFACE, \ - ENDPOINT) \ - BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32); \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram; \ - struct usb_gpio_config const NAME = { \ - .state = &((struct usb_gpio_state){}), \ - .endpoint = ENDPOINT, \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ - .gpios = GPIO_LIST, \ - .num_gpios = ARRAY_SIZE(GPIO_LIST), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = 0, \ - .bInterfaceProtocol = 0, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_gpio_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_gpio_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_gpio_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)) - - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB GPIO driver. - */ -void usb_gpio_tx(struct usb_gpio_config const *config); -void usb_gpio_rx(struct usb_gpio_config const *config); -void usb_gpio_event(struct usb_gpio_config const *config, - enum usb_ep_event evt); - -#endif /* __CROS_EC_USB_GPIO_H */ diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c deleted file mode 100644 index b8336fa0a0..0000000000 --- a/chip/stm32/usb_hid.c +++ /dev/null @@ -1,156 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "link_defs.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_hid.h" -#include "usb_hid_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -void hid_tx(int ep) -{ - /* clear IT */ - STM32_USB_EP(ep) = (STM32_USB_EP(ep) & EP_MASK); -} - -void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len, - usb_uint *hid_ep_rx_buf, int rx_len) -{ - int i; - uint16_t ep_reg; - - btable_ep[ep].tx_addr = usb_sram_addr(hid_ep_tx_buf); - btable_ep[ep].tx_count = tx_len; - - /* STM32 USB SRAM needs to be accessed one U16 at a time */ - for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++) - hid_ep_tx_buf[i] = 0; - - ep_reg = (ep << 0) /* Endpoint Address */ | - EP_TX_VALID | - (3 << 9) /* interrupt EP */ | - EP_RX_DISAB; - - /* Enable RX for output reports */ - if (hid_ep_rx_buf && rx_len > 0) { - btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf); - btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10; - - ep_reg |= EP_RX_VALID; /* RX Valid */ - } - - STM32_USB_EP(ep) = ep_reg; -} - -/* - * Keep track of state in case we need to be called multiple times, - * if the report length is bigger than 64 bytes. - */ -static int report_left; -static const uint8_t *report_ptr; - -/* - * Send report through ep0_buf_tx. - * - * If report size is greater than USB packet size (64 bytes), rest of the - * reports will be saved in `report_ptr` and `report_left`, so we can call this - * function again to send the remain parts. - * - * @return 0 if entire report is sent, 1 if there are remaining data. - */ -static int send_report(usb_uint *ep0_buf_tx, - const uint8_t *report, - int report_size) -{ - int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE); - - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report, packet_size); - btable_ep[0].tx_count = packet_size; - /* report_left != 0 if report doesn't fit in 1 packet. */ - report_left = report_size - packet_size; - report_ptr = report + packet_size; - - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - report_left ? 0 : EP_STATUS_OUT); - - return report_left ? 1 : 0; -} - -int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, - const struct usb_hid_config_t *config) -{ - const uint8_t *report_desc = config->report_desc; - int report_size = config->report_size; - const struct usb_hid_descriptor *hid_desc = config->hid_desc; - - if (!ep0_buf_rx) { - /* - * Continue previous transfer. We ignore report_desc/size here, - * which is fine as only one GET_DESCRIPTOR command comes at a - * time. - */ - if (report_left == 0) - return -1; - report_size = MIN(USB_MAX_PACKET_SIZE, report_left); - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report_ptr, report_size); - btable_ep[0].tx_count = report_size; - report_left -= report_size; - report_ptr += report_size; - STM32_TOGGLE_EP(0, EP_TX_MASK, EP_TX_VALID, - report_left ? 0 : EP_STATUS_OUT); - return report_left ? 1 : 0; - } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE | - (USB_REQ_GET_DESCRIPTOR << 8))) { - if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) { - /* Setup : HID specific : Get Report descriptor */ - return send_report(ep0_buf_tx, report_desc, - MIN(ep0_buf_rx[3], report_size)); - } else if (ep0_buf_rx[1] == (USB_HID_DT_HID << 8)) { - /* Setup : HID specific : Get HID descriptor */ - memcpy_to_usbram_ep0_patch(hid_desc, sizeof(*hid_desc)); - btable_ep[0].tx_count = sizeof(*hid_desc); - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - EP_STATUS_OUT); - return 0; - } - } else if (ep0_buf_rx[0] == (USB_DIR_IN | - USB_RECIP_INTERFACE | - USB_TYPE_CLASS | - (USB_HID_REQ_GET_REPORT << 8))) { - const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF; - const uint8_t report_id = ep0_buf_rx[1] & 0xFF; - int retval; - - report_left = ep0_buf_rx[3]; - if (!config->get_report) /* not supported */ - return -1; - - retval = config->get_report(report_id, - report_type, - &report_ptr, - &report_left); - if (retval) - return retval; - - return send_report(ep0_buf_tx, report_ptr, report_left); - } - - return -1; -} diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h deleted file mode 100644 index a36a66567e..0000000000 --- a/chip/stm32/usb_hid_hw.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * USB HID HW definitions, to be used by class drivers. - */ - -#ifndef __CROS_EC_USB_HID_HW_H -#define __CROS_EC_USB_HID_HW_H - -#include <common.h> - -struct usb_hid_config_t { - const uint8_t *report_desc; - int report_size; - const struct usb_hid_descriptor *hid_desc; - - /* - * Handle USB HID Get_Report request, can be NULL if not supported. - * - * @param report_id: ID of the report being requested - * @param report_type: 0x1 (INPUT) / 0x2 (OUTPUT) / 0x3 (FEATURE) - * @param buffer_ptr: handler should set it to the pointer of buffer to - * return. - * @param buffer_size: handler should set it to the size of returned - * buffer. - */ - int (*get_report)(uint8_t report_id, - uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size); -}; - -/* internal callbacks for HID class drivers */ -void hid_tx(int ep); -void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len, - usb_uint *hid_ep_rx_buf, int rx_len); -int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, - const struct usb_hid_config_t *hid_config); - -#endif diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c deleted file mode 100644 index e2a8d675e9..0000000000 --- a/chip/stm32/usb_hid_keyboard.c +++ /dev/null @@ -1,841 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "atomic.h" -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "keyboard_config.h" -#include "keyboard_protocol.h" -#include "link_defs.h" -#include "pwm.h" -#include "queue.h" -#include "registers.h" -#include "tablet_mode.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_hid.h" -#include "usb_hid_hw.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) - -static const int keyboard_debug; - -struct key_event { - uint32_t time; - uint8_t keycode; - uint8_t pressed; -}; - -static struct queue const key_queue = QUEUE_NULL(16, struct key_event); -static struct mutex key_queue_mutex; - -enum hid_protocol { - HID_BOOT_PROTOCOL = 0, - HID_REPORT_PROTOCOL = 1, - HID_PROTOCOL_COUNT = 2, -}; - -/* Current protocol, behaviour is identical in both modes. */ -static enum hid_protocol protocol = HID_REPORT_PROTOCOL; - -#if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \ - defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH) -#define HID_KEYBOARD_EXTRA_FIELD -#endif - -/* - * Note: This first 8 bytes of this report format cannot be changed, as that - * would break HID Boot protocol compatibility (see HID 1.11 "Appendix B: Boot - * Interface Descriptors"). - */ -struct usb_hid_keyboard_report { - uint8_t modifiers; /* bitmap of modifiers 224-231 */ - uint8_t reserved; /* 0x0 */ - uint8_t keys[6]; - /* Non-boot protocol fields below */ -#ifdef HID_KEYBOARD_EXTRA_FIELD - /* Assistant/tablet mode switch bitmask */ - uint8_t extra; -#endif -#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - uint32_t top_row; /* bitmap of top row action keys */ -#endif -} __packed; - -struct usb_hid_keyboard_output_report { - uint8_t brightness; -} __packed; - -#define HID_KEYBOARD_BOOT_SIZE 8 - -#define HID_KEYBOARD_REPORT_SIZE sizeof(struct usb_hid_keyboard_report) -#define HID_KEYBOARD_OUTPUT_REPORT_SIZE \ - sizeof(struct usb_hid_keyboard_output_report) - -#define HID_KEYBOARD_EP_INTERVAL_MS 16 /* ms */ - -/* - * Coalesce events happening within some interval. The value must be greater - * than EP interval to ensure we cannot have a backlog of keys. - * It must also be short enough to ensure that the intended order of key presses - * is passed to AP, and that we do not coalesce press and release events (which - * would result in lost keys). - */ -#define COALESCE_INTERVAL (18 * MSEC) - -/* - * Discard key events in the FIFO buffer that are older than this amount of - * time. Note that we do not fully drop them, we still update the report, - * but we do not send the events individually anymore (so an old key press - * and release will be dropped altogether, but a single press/release will - * still be reported correctly). - */ -#define KEY_DISCARD_MAX_TIME (1 * SECOND) - -/* Modifiers keycode range */ -#define HID_KEYBOARD_MODIFIER_LOW 0xe0 -#define HID_KEYBOARD_MODIFIER_HIGH 0xe7 - -/* Supported function key range */ -#define HID_F1 0x3a -#define HID_F12 0x45 -#define HID_F13 0x68 -#define HID_F15 0x6a - -/* Special keys/switches */ -#define HID_KEYBOARD_EXTRA_LOW 0xf0 -#define HID_KEYBOARD_ASSISTANT_KEY 0xf0 -#define HID_KEYBOARD_TABLET_MODE_SWITCH 0xf1 -#define HID_KEYBOARD_EXTRA_HIGH 0xf1 - -/* The standard Chrome OS keyboard matrix table. See HUT 1.12v2 Table 12 and - * https://www.w3.org/TR/DOM-Level-3-Events-code . - * - * Assistant key is mapped as 0xf0, but this key code is never actually send. - */ -const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00}, - {0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14}, - {0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08}, - {0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15}, - {0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a}, - {0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c}, - {0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18}, - {0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5}, - {0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13}, - {0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12}, - {0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00}, - {0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52}, - {0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50}, -}; - -/* HID descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_KEYBOARD) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_HID_KEYBOARD, - .bAlternateSetting = 0, -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - .bNumEndpoints = 2, -#else - .bNumEndpoints = 1, -#endif - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT, - .bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD, - .iInterface = 0, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 81) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_HID_KEYBOARD, - .bmAttributes = 0x03 /* Interrupt endpoint */, - .wMaxPacketSize = HID_KEYBOARD_REPORT_SIZE, - .bInterval = HID_KEYBOARD_EP_INTERVAL_MS /* ms polling interval */ -}; - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_HID_KEYBOARD, - .bmAttributes = 0x03 /* Interrupt endpoint */, - .wMaxPacketSize = HID_KEYBOARD_OUTPUT_REPORT_SIZE, - .bInterval = HID_KEYBOARD_EP_INTERVAL_MS -}; -#endif - -#define KEYBOARD_BASE_DESC \ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ - 0x09, 0x06, /* Usage (Keyboard) */ \ - 0xA1, 0x01, /* Collection (Application) */ \ - \ - /* Modifiers */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */ \ - 0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x08, /* Report Count (8) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x81, 0x01, /* Input (Constant), ;Reserved byte */ \ - \ - /* Normal keys */ \ - 0x95, 0x06, /* Report Count (6) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0xa4, /* Logical Maximum (164) */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, 0x00, /* Usage Minimum (0) */ \ - 0x29, 0xa4, /* Usage Maximum (164) */ \ - 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ - -#define KEYBOARD_TOP_ROW_DESC \ - /* Modifiers */ \ - 0x05, 0x0C, /* Consumer Page */ \ - 0x0A, 0x24, 0x02, /* AC Back (0x224) */ \ - 0x0A, 0x25, 0x02, /* AC Forward (0x225) */ \ - 0x0A, 0x27, 0x02, /* AC Refresh (0x227) */ \ - 0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */ \ - 0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */ \ - 0x09, 0x70, /* Display Brightness Decrement (0x70) */ \ - 0x09, 0x6F, /* Display Brightness Increment (0x6F) */ \ - 0x09, 0xE2, /* Mute (0xE2) */ \ - 0x09, 0xEA, /* Volume Decrement (0xEA) */ \ - 0x09, 0xE9, /* Volume Increment (0xE9) */ \ - 0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage 0x46) */ \ - 0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */ \ - 0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */ \ - 0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/ \ - 0x09, 0xCD, /* Play / Pause (0xCD) */ \ - 0x09, 0xB5, /* Scan Next Track (0xB5) */ \ - 0x09, 0xB6, /* Scan Previous Track (0xB6) */ \ - 0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */ \ - 0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage 0x2F) */ \ - 0x09, 0x32, /* Sleep (0x32) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x14, /* Report Count (20) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - /* 12-bit padding */ \ - 0x95, 0x0C, /* Report Count (12) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ - -#define KEYBOARD_TOP_ROW_FEATURE_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Google) */ \ - 0x09, 0x01, /* Usage (Top Row List) */ \ - 0xa1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x0a, /* Usage Page (Ordinal) */ \ - 0x19, 0x01, /* Usage Minimum (1) */ \ - 0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \ - 0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */ \ - 0x75, 0x20, /* Report Size (32) */ \ - 0xb1, 0x03, /* Feature (Cnst,Var,Abs) */ \ - 0xc0, /* End Collection */ - -/* - * Vendor-defined Usage Page 0xffd1: - * - 0x18: Assistant key - * - 0x19: Tablet mode switch - */ -#ifdef HID_KEYBOARD_EXTRA_FIELD -#ifdef CONFIG_KEYBOARD_ASSISTANT_KEY -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x19, 0x18, /* Usage Minimum */ \ - 0x29, 0x18, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ -#else -/* No assistant key: just pad 1 bit. */ -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ -#endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */ - -#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x19, 0x19, /* Usage Minimum */ \ - 0x29, 0x19, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ -#else -/* No tablet mode swtch: just pad 1 bit. */ -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ -#endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */ - -#define KEYBOARD_VENDOR_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */ \ - \ - KEYBOARD_ASSISTANT_KEY_DESC \ - KEYBOARD_TABLET_MODE_SWITCH_DESC \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x06, /* Report Size (6) */ \ - 0x81, 0x01, /* Input (Constant), ;6-bit padding */ -#endif /* HID_KEYBOARD_EXTRA_FIELD */ - -#define KEYBOARD_BACKLIGHT_DESC \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x14, /* Usage Page (Alphanumeric Display) */ \ - 0x09, 0x46, /* Usage (Display Brightness) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x64, /* Logical Maximum (100) */ \ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ \ - 0xC0, /* End Collection */ - -/* - * To allow dynamic detection of keyboard backlights, we define two descriptors. - * One has keyboard backlight, and the other one does not. - */ - -/* HID : Report Descriptor */ -static const uint8_t report_desc[] = { - - KEYBOARD_BASE_DESC - -#ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC -#endif - -#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - KEYBOARD_TOP_ROW_DESC - KEYBOARD_TOP_ROW_FEATURE_DESC -#endif - 0xC0 /* End Collection */ -}; - - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - -/* HID : Report Descriptor with keyboard backlight */ -static const uint8_t report_desc_with_backlight[] = { - - KEYBOARD_BASE_DESC - -#ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC -#endif - -#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - KEYBOARD_TOP_ROW_DESC - KEYBOARD_TOP_ROW_FEATURE_DESC -#endif - KEYBOARD_BACKLIGHT_DESC - - 0xC0 /* End Collection */ -}; - -#endif - -/* HID: HID Descriptor */ -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, - hid, hid_desc_kb) = { - .bLength = 9, - .bDescriptorType = USB_HID_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0x00, /* Hardware target country */ - .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} -}; - -#define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2) - -static usb_uint hid_ep_tx_buf[EP_TX_BUF_SIZE] __usb_ram; -static volatile int hid_current_buf; - -static volatile int hid_ep_data_ready; - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT -#define EP_RX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_OUTPUT_REPORT_SIZE, 2) -static usb_uint hid_ep_rx_buf[EP_RX_BUF_SIZE] __usb_ram; -#endif - -static struct usb_hid_keyboard_report report; - -static void keyboard_process_queue(void); -DECLARE_DEFERRED(keyboard_process_queue); - -static void write_keyboard_report(void) -{ - /* Tell the interrupt handler to send the next buffer. */ - hid_ep_data_ready = 1; - if ((STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) == EP_TX_VALID) { - /* Endpoint is busy */ - return; - } - - if (atomic_clear((int *)&hid_ep_data_ready)) { - /* - * Endpoint is not busy, and interrupt handler did not just - * send the buffer: enable TX. - */ - - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); - } - - /* - * Wake the host. This is required to prevent a race between EP getting - * reloaded and host suspending the device, as, ideally, we never want - * to have EP loaded during suspend, to avoid reporting stale data. - */ - usb_wake(); -} - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - -static void hid_keyboard_rx(void) -{ - struct usb_hid_keyboard_output_report report; - memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf), - HID_KEYBOARD_OUTPUT_REPORT_SIZE); - - CPRINTF("Keyboard backlight set to %d%%\n", report.brightness); - - pwm_enable(PWM_CH_KBLIGHT, report.brightness > 0); - pwm_set_duty(PWM_CH_KBLIGHT, report.brightness); - - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); -} - -#endif - -static void hid_keyboard_tx(void) -{ - hid_tx(USB_EP_HID_KEYBOARD); - if (hid_ep_data_ready) { - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); - hid_ep_data_ready = 0; - } - - if (queue_count(&key_queue) > 0) - hook_call_deferred(&keyboard_process_queue_data, 0); -} - -static void hid_keyboard_event(enum usb_ep_event evt) -{ - if (evt == USB_EVENT_RESET) { - protocol = HID_REPORT_PROTOCOL; - - hid_reset(USB_EP_HID_KEYBOARD, - hid_ep_tx_buf, - HID_KEYBOARD_REPORT_SIZE, -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - hid_ep_rx_buf, - HID_KEYBOARD_OUTPUT_REPORT_SIZE -#else - NULL, 0 -#endif - ); - - /* - * Reload endpoint on reset, to make sure we report accurate - * state to host (this is especially important for tablet mode - * switch). - */ - write_keyboard_report(); - return; - } - - if (evt == USB_EVENT_DEVICE_RESUME && queue_count(&key_queue) > 0) - hook_call_deferred(&keyboard_process_queue_data, 0); -} - -USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_keyboard_tx, -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - hid_keyboard_rx, -#else - hid_keyboard_tx, -#endif - hid_keyboard_event); - -struct action_key_config { - uint32_t mask; /* bit position of usb_hid_keyboard_report.top_row */ - uint32_t usage; /*usage ID */ -}; - -static const struct action_key_config action_key[] = { - [TK_BACK] = { .mask = BIT(0), .usage = 0x000C0224 }, - [TK_FORWARD] = { .mask = BIT(1), .usage = 0x000C0225 }, - [TK_REFRESH] = { .mask = BIT(2), .usage = 0x000C0227 }, - [TK_FULLSCREEN] = { .mask = BIT(3), .usage = 0x000C0232 }, - [TK_OVERVIEW] = { .mask = BIT(4), .usage = 0x000C029F }, - [TK_BRIGHTNESS_DOWN] = { .mask = BIT(5), .usage = 0x000C0070 }, - [TK_BRIGHTNESS_UP] = { .mask = BIT(6), .usage = 0x000C006F }, - [TK_VOL_MUTE] = { .mask = BIT(7), .usage = 0x000C00E2 }, - [TK_VOL_DOWN] = { .mask = BIT(8), .usage = 0x000C00EA }, - [TK_VOL_UP] = { .mask = BIT(9), .usage = 0x000C00E9 }, - [TK_SNAPSHOT] = { .mask = BIT(10), .usage = 0x00070046 }, - [TK_PRIVACY_SCRN_TOGGLE] = { .mask = BIT(11), .usage = 0x000C02D0 }, - [TK_KBD_BKLIGHT_DOWN] = { .mask = BIT(12), .usage = 0x000C007A }, - [TK_KBD_BKLIGHT_UP] = { .mask = BIT(13), .usage = 0x000C0079 }, - [TK_PLAY_PAUSE] = { .mask = BIT(14), .usage = 0x000C00CD }, - [TK_NEXT_TRACK] = { .mask = BIT(15), .usage = 0x000C00B5 }, - [TK_PREV_TRACK] = { .mask = BIT(16), .usage = 0x000C00B6 }, - [TK_KBD_BKLIGHT_TOGGLE] = { .mask = BIT(17), .usage = 0x000C007C }, - [TK_MICMUTE] = { .mask = BIT(18), .usage = 0x000B002F }, -}; - -/* TK_* is 1-indexed, so the next bit is at ARRAY_SIZE(action_key) - 1 */ -static const int SLEEP_KEY_MASK = BIT(ARRAY_SIZE(action_key) - 1); - -#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI -static uint32_t feature_report[CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS]; - -static void hid_keyboard_feature_init(void) -{ - const struct ec_response_keybd_config *config = - board_vivaldi_keybd_config(); - - for (int i = 0; i < CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS; i++) { - int key = config->action_keys[i]; - - if (IN_RANGE(key, 0, ARRAY_SIZE(action_key))) - feature_report[i] = action_key[key].usage; - } -} -DECLARE_HOOK(HOOK_INIT, hid_keyboard_feature_init, HOOK_PRIO_DEFAULT - 1); -#endif - -static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type, - const uint8_t **buffer_ptr, int *buffer_size) -{ - if (report_type == REPORT_TYPE_INPUT) { - *buffer_ptr = (uint8_t *)&report; - *buffer_size = sizeof(report); - return 0; - } - -#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - if (report_type == REPORT_TYPE_FEATURE) { - *buffer_ptr = (uint8_t *)feature_report; - *buffer_size = (sizeof(uint32_t) * - CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS); - return 0; - } -#endif - - return -1; -} - -static struct usb_hid_config_t hid_config_kb = { - .report_desc = report_desc, - .report_size = sizeof(report_desc), - .hid_desc = &hid_desc_kb, - .get_report = &hid_keyboard_get_report, -}; - -static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) -{ - int ret; - - ret = hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_kb); - if (ret >= 0) - return ret; - - if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) { - uint16_t value = ep0_buf_rx[1]; - - if (value >= HID_PROTOCOL_COUNT) - return -1; - - protocol = value; - - /* Reload endpoint with appropriate tx_count. */ - btable_ep[USB_EP_HID_KEYBOARD].tx_count = - (protocol == HID_BOOT_PROTOCOL) ? - HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE; - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); - - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - return 0; - } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) { - uint8_t value = protocol; - - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &value, sizeof(value)); - btable_ep[0].tx_count = 1; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - return 0; - } - - return -1; -} -USB_DECLARE_IFACE(USB_IFACE_HID_KEYBOARD, hid_keyboard_iface_request) - -void keyboard_clear_buffer(void) -{ - mutex_lock(&key_queue_mutex); - queue_init(&key_queue); - mutex_unlock(&key_queue_mutex); - - memset(&report, 0, sizeof(report)); -#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH - if (tablet_get_mode()) - report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH - - HID_KEYBOARD_EXTRA_LOW); -#endif - write_keyboard_report(); -} - -/* - * Convert a function key to the bit mask of corresponding action key. - * - * Return 0 if no need to map (not a function key or vivaldi not enabled) - */ -static uint32_t maybe_convert_function_key(int keycode) -{ - const struct ec_response_keybd_config *config = - board_vivaldi_keybd_config(); - /* zero-based function key index (e.g. F1 -> 0) */ - int index; - - if (!IS_ENABLED(CONFIG_USB_HID_KEYBOARD_VIVALDI) || !config) - return 0; - - if (IN_RANGE(keycode, HID_F1, HID_F12 + 1)) - index = keycode - HID_F1; - else if (IN_RANGE(keycode, HID_F13, HID_F15 + 1)) - index = keycode - HID_F13 + 12; - else - return 0; /* not a function key */ - - /* convert F13 to Sleep */ - if (index == 12 && (config->capabilities & KEYBD_CAP_SCRNLOCK_KEY)) - return SLEEP_KEY_MASK; - - if (index >= config->num_top_row_keys || - config->action_keys[index] == TK_ABSENT) - return 0; /* not mapped */ - return action_key[config->action_keys[index]].mask; -} - -static void keyboard_process_queue(void) -{ - int i; - uint8_t mask; - struct key_event ev; - int valid = 0; - int trimming = 0; - uint32_t now = __hw_clock_source_read(); - uint32_t first_key_time; - - if (keyboard_debug) - CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue), - usb_is_suspended(), hid_ep_data_ready, - (STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) - == EP_TX_VALID); - mutex_lock(&key_queue_mutex); - - if (queue_count(&key_queue) == 0) { - mutex_unlock(&key_queue_mutex); - return; - } - - if (usb_is_suspended() || hid_ep_data_ready) { - usb_wake(); - - if (!queue_is_full(&key_queue)) { - /* Queue still has space, let's keep gathering keys. */ - mutex_unlock(&key_queue_mutex); - return; - } - - /* - * Queue is full, so we continue, as the code below is - * guaranteed to pop at least one key from the queue, but we do - * not write the report at the end. - */ - CPRINTF("Trimming queue (%d %d %d)\n", queue_count(&key_queue), - usb_is_suspended(), hid_ep_data_ready); - - trimming = 1; - } - - /* There is at least one element in the queue. */ - queue_peek_units(&key_queue, &ev, 0, 1); - first_key_time = ev.time; - - /* - * Pick key events from the queue, coalescing events older than events - * within EP interval time to make sure the queue cannot grow, and - * dropping keys that are too old. - */ - while (queue_count(&key_queue) > 0) { - uint32_t action_key_mask; - - queue_peek_units(&key_queue, &ev, 0, 1); - if (keyboard_debug) - CPRINTF(" =%02x/%d %d %d\n", ev.keycode, ev.keycode, - ev.pressed, ev.time - now); - - if ((now - ev.time) <= KEY_DISCARD_MAX_TIME && - (ev.time - first_key_time) >= COALESCE_INTERVAL) - break; - - queue_advance_head(&key_queue, 1); - - action_key_mask = maybe_convert_function_key(ev.keycode); - if (action_key_mask) { -#ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - if (ev.pressed) - report.top_row |= action_key_mask; - else - report.top_row &= ~action_key_mask; - valid = 1; -#endif - } else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW && - ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) { -#ifdef HID_KEYBOARD_EXTRA_FIELD - mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW); - if (ev.pressed) - report.extra |= mask; - else - report.extra &= ~mask; - valid = 1; -#endif - } else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW && - ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) { - mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW); - if (ev.pressed) - report.modifiers |= mask; - else - report.modifiers &= ~mask; - valid = 1; - } else if (ev.pressed) { - /* - * Add keycode to the list of keys (does nothing if the - * array is already full). - */ - for (i = 0; i < ARRAY_SIZE(report.keys); i++) { - /* Is key already pressed? */ - if (report.keys[i] == ev.keycode) - break; - if (report.keys[i] == 0) { - report.keys[i] = ev.keycode; - valid = 1; - break; - } - } - } else { - /* - * Remove keycode from the list of keys (does nothing - * if the key is not in the array). - */ - for (i = 0; i < ARRAY_SIZE(report.keys); i++) { - if (report.keys[i] == ev.keycode) { - report.keys[i] = 0; - valid = 1; - break; - } - } - } - } - - mutex_unlock(&key_queue_mutex); - - if (valid && !trimming) - write_keyboard_report(); -} - -static void queue_keycode_event(uint8_t keycode, int is_pressed) -{ - struct key_event ev = { - .time = __hw_clock_source_read(), - .keycode = keycode, - .pressed = is_pressed, - }; - - mutex_lock(&key_queue_mutex); - queue_add_unit(&key_queue, &ev); - mutex_unlock(&key_queue_mutex); - - keyboard_process_queue(); -} - -#ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH -#include "console.h" - -static void tablet_mode_change(void) -{ - queue_keycode_event(HID_KEYBOARD_TABLET_MODE_SWITCH, tablet_get_mode()); -} -DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT); -/* Run after tablet_mode_init. */ -DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1); -#endif - -void keyboard_state_changed(int row, int col, int is_pressed) -{ - uint8_t keycode = keycodes[col][row]; - - if (!keycode) { - CPRINTF("Unknown key at %d/%d\n", row, col); - return; - } - - queue_keycode_event(keycode, is_pressed); -} - -void clear_typematic_key(void) -{ } - -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT -void usb_hid_keyboard_init(void) -{ - if (board_has_keyboard_backlight()) { - hid_config_kb.report_desc = report_desc_with_backlight; - hid_config_kb.report_size = sizeof(report_desc_with_backlight); - - set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT, - &hid_desc_kb.desc[0].wDescriptorLength, - sizeof(report_desc_with_backlight)); - } -} -/* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */ -DECLARE_HOOK(HOOK_INIT, usb_hid_keyboard_init, HOOK_PRIO_DEFAULT - 1); -#endif diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c deleted file mode 100644 index 0ead660432..0000000000 --- a/chip/stm32/usb_hid_touchpad.c +++ /dev/null @@ -1,424 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "clock.h" -#include "common.h" -#include "config.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "link_defs.h" -#include "queue.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_api.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_hid.h" -#include "usb_hid_hw.h" -#include "usb_hid_touchpad.h" - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) - -static const int touchpad_debug; - -static struct queue const report_queue = QUEUE_NULL(8, - struct usb_hid_touchpad_report); -static struct mutex report_queue_mutex; - -#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report) - -/* - * Touchpad EP interval: Make sure this value is smaller than the typical - * interrupt interval from the trackpad. - */ -#define HID_TOUCHPAD_EP_INTERVAL_MS 2 /* ms */ - -/* Discard TP events older than this time */ -#define EVENT_DISCARD_MAX_TIME (1 * SECOND) - -/* HID descriptors */ -const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID_TOUCHPAD) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_HID_TOUCHPAD, - .bAlternateSetting = 0, - .bNumEndpoints = 1, - .bInterfaceClass = USB_CLASS_HID, - .bInterfaceSubClass = 0, - .bInterfaceProtocol = 0, - .iInterface = 0, -}; -const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_HID_TOUCHPAD, - .bmAttributes = 0x03 /* Interrupt endpoint */, - .wMaxPacketSize = HID_TOUCHPAD_REPORT_SIZE, - .bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */ -}; - -#define FINGER_USAGE \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - 0x09, 0x22, /* Usage (Finger) */ \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x09, 0x47, /* Usage (Confidence) */ \ - 0x09, 0x42, /* Usage (Tip Switch) */ \ - 0x09, 0x32, /* Usage (In Range) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x03, /* Report Count (3) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x51, /* Usage (0x51) Contact identifier */ \ - 0x75, 0x04, /* Report Size (4) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x25, 0x0F, /* Logical Maximum (15) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - /* Logical Maximum of Pressure */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \ - 0x75, 0x09, /* Report Size (9) */ \ - 0x09, 0x30, /* Usage (Tip pressure) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, 0xFF, 0x0F, /* Logical Maximum (4095) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x09, 0x48, /* Usage (WIDTH) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x49, /* Usage (HEIGHT) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x55, 0x0E, /* Unit Exponent (-2) */ \ - 0x65, 0x11, /* Unit (System: SI Linear, Length: cm) */ \ - 0x09, 0x30, /* Usage (X) */ \ - 0x35, 0x00, /* Physical Minimum (0) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x09, 0x31, /* Usage (Y) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0xC0 /* End Collection */ - -/* - * HID: Report Descriptor - * TODO(b/35582031): There are ways to reduce flash usage, as the - * Finger Usage is repeated 5 times. - */ -static const uint8_t report_desc[] = { - /* Touchpad Collection */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x05, /* Usage (Touch Pad) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_TOUCHPAD, /* Report ID (1, Touch) */ - /* Finger 0 */ - FINGER_USAGE, - /* Finger 1 */ - FINGER_USAGE, - /* Finger 2 */ - FINGER_USAGE, - /* Finger 3 */ - FINGER_USAGE, - /* Finger 4 */ - FINGER_USAGE, - /* Contact count */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x54, /* Usage (Contact count) */ - 0x25, MAX_FINGERS, /* Logical Maximum (MAX_FINGERS) */ - 0x75, 0x07, /* Report Size (7) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - /* Button */ - 0x05, 0x01, /* Usage Page(Generic Desktop Ctrls) */ - 0x05, 0x09, /* Usage (Button) */ - 0x19, 0x01, /* Usage Minimum (0x01) */ - 0x29, 0x01, /* Usage Maximum (0x01) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - /* Timestamp */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x55, 0x0C, /* Unit Exponent (-4) */ - 0x66, 0x01, 0x10, /* Unit (Seconds) */ - 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ - 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ - 0x75, 0x10, /* Report Size (16) */ - 0x95, 0x01, /* Report Count (1) */ - 0x09, 0x56, /* Usage (0x56, Relative Scan Time) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - - 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ - 0x09, 0x55, /* Usage (Contact Count Maximum) */ - 0x09, 0x59, /* Usage (Pad Type) */ - 0x25, 0x0F, /* Logical Maximum (15) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x02, /* Report Count (2) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - - /* Page 0xFF, usage 0xC5 is device certificate. */ - 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ - 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ - 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ - 0x75, 0x08, /* Report Size (8) */ - 0x96, 0x00, 0x01, /* Report Count (256) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - - 0xC0, /* End Collection */ -}; - -/* A 256-byte default blob for the 'device certification status' feature report. - * - * TODO(b/113248108): do we need a real certification? - */ -static const uint8_t device_cert_response[] = { - REPORT_ID_DEVICE_CERT, - - 0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, - 0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88, - 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6, - 0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, - 0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43, - 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC, - 0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, - 0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71, - 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5, - 0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, - 0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9, - 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C, - 0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, - 0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B, - 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A, - 0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, - 0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1, - 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7, - 0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, - 0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35, - 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC, - 0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, - 0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF, - 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60, - 0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, - 0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13, - 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7, - 0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, - 0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89, - 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4, - 0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, - 0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2, -}; - -/* Device capabilities feature report. */ -static const uint8_t device_caps_response[] = { - REPORT_ID_DEVICE_CAPS, - - MAX_FINGERS, /* Contact Count Maximum */ - 0x00, /* Pad Type: Depressible click-pad */ -}; - -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, - hid, hid_desc_tp) = { - .bLength = 9, - .bDescriptorType = USB_HID_DT_HID, - .bcdHID = 0x0100, - .bCountryCode = 0x00, /* Hardware target country */ - .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} -}; - -static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram; - -/* - * Write a report to EP, must be called with queue mutex held, and caller - * must first check that EP is not busy. - */ -static void write_touchpad_report(struct usb_hid_touchpad_report *report) -{ - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf), - report, sizeof(*report)); - /* enable TX */ - STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0); - - /* - * Wake the host. This is required to prevent a race between EP getting - * reloaded and host suspending the device, as, ideally, we never want - * to have EP loaded during suspend, to avoid reporting stale data. - */ - usb_wake(); -} - -static void hid_touchpad_process_queue(void); -DECLARE_DEFERRED(hid_touchpad_process_queue); - -static void hid_touchpad_process_queue(void) -{ - struct usb_hid_touchpad_report report; - uint16_t now; - int trimming = 0; - - mutex_lock(&report_queue_mutex); - - /* EP is busy, or nothing in queue: do nothing. */ - if (queue_count(&report_queue) == 0) - goto unlock; - - now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT; - - if (usb_is_suspended() || - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) - == EP_TX_VALID) { - usb_wake(); - - /* Let's trim old events from the queue, if any. */ - trimming = 1; - } else { - hook_call_deferred(&hid_touchpad_process_queue_data, -1); - } - - if (touchpad_debug) - CPRINTS("TPQ t=%d (%d)", trimming, queue_count(&report_queue)); - - while (queue_count(&report_queue) > 0) { - int delta; - - queue_peek_units(&report_queue, &report, 0, 1); - - delta = (int)((uint16_t)(now - report.timestamp)) - * USB_HID_TOUCHPAD_TIMESTAMP_UNIT; - - if (touchpad_debug) - CPRINTS("evt t=%d d=%d", report.timestamp, delta); - - /* Drop old events */ - if (delta > EVENT_DISCARD_MAX_TIME) { - queue_advance_head(&report_queue, 1); - continue; - } - - if (trimming) { - /* - * If we stil fail to resume, this will discard the - * event after the timeout expires. - */ - hook_call_deferred(&hid_touchpad_process_queue_data, - EVENT_DISCARD_MAX_TIME - delta); - } else { - queue_advance_head(&report_queue, 1); - write_touchpad_report(&report); - } - break; - } - -unlock: - mutex_unlock(&report_queue_mutex); -} - -void set_touchpad_report(struct usb_hid_touchpad_report *report) -{ - static int print_full = 1; - - mutex_lock(&report_queue_mutex); - - /* USB/EP ready and nothing in queue, just write the report. */ - if (!usb_is_suspended() && - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID - && queue_count(&report_queue) == 0) { - write_touchpad_report(report); - mutex_unlock(&report_queue_mutex); - return; - } - - /* Else add to queue, dropping oldest event if needed. */ - if (touchpad_debug) - CPRINTS("sTP t=%d", report->timestamp); - if (queue_is_full(&report_queue)) { - if (print_full) - CPRINTF("TP queue full\n"); - print_full = 0; - - queue_advance_head(&report_queue, 1); - } else { - print_full = 1; - } - queue_add_unit(&report_queue, report); - - mutex_unlock(&report_queue_mutex); - - hid_touchpad_process_queue(); -} - -static void hid_touchpad_tx(void) -{ - hid_tx(USB_EP_HID_TOUCHPAD); - - if (queue_count(&report_queue) > 0) - hook_call_deferred(&hid_touchpad_process_queue_data, 0); -} - -static void hid_touchpad_event(enum usb_ep_event evt) -{ - if (evt == USB_EVENT_RESET) - hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf, - HID_TOUCHPAD_REPORT_SIZE, NULL, 0); - else if (evt == USB_EVENT_DEVICE_RESUME && - queue_count(&report_queue) > 0) - hook_call_deferred(&hid_touchpad_process_queue_data, 0); -} - -USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx, - hid_touchpad_event); - -static int get_report(uint8_t report_id, uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size) -{ - switch (report_id) { - case REPORT_ID_DEVICE_CAPS: - *buffer_ptr = device_caps_response; - *buffer_size = MIN(sizeof(device_caps_response), *buffer_size); - return 0; - case REPORT_ID_DEVICE_CERT: - *buffer_ptr = device_cert_response; - *buffer_size = MIN(sizeof(device_cert_response), *buffer_size); - return 0; - } - return -1; -} - -static const struct usb_hid_config_t hid_config_tp = { - .report_desc = report_desc, - .report_size = sizeof(report_desc), - .hid_desc = &hid_desc_tp, - .get_report = get_report, -}; - -static int hid_touchpad_iface_request(usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) -{ - return hid_iface_request(ep0_buf_rx, ep0_buf_tx, &hid_config_tp); -} -USB_DECLARE_IFACE(USB_IFACE_HID_TOUCHPAD, hid_touchpad_iface_request) diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h deleted file mode 100644 index 0c75322a7d..0000000000 --- a/chip/stm32/usb_hw.h +++ /dev/null @@ -1,142 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_HW_H -#define __CROS_EC_USB_HW_H - -#include <stddef.h> -#include <stdint.h> - -/* Event types for the endpoint event handler. */ -enum usb_ep_event { - USB_EVENT_RESET, - USB_EVENT_DEVICE_RESUME, /* Device-initiated wake completed. */ -}; - -#if defined(CHIP_FAMILY_STM32F4) -#include "usb_dwc_hw.h" -#else - - -/* - * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads & - * writes are 16-bits wide). The endpoint tables and the data buffers live in - * this RAM. -*/ - -/* Primitive to access the words in USB RAM */ -typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint; -/* Linker symbol for start of USB RAM */ -extern usb_uint __usb_ram_start[]; - -/* Attribute to define a buffer variable in USB RAM */ -#define __usb_ram __attribute__((section(".usb_ram.99_data"))) - -/* Mask for the rx_count to identify the number of bytes in the buffer. */ -#define RX_COUNT_MASK (0x3ff) - -struct stm32_endpoint { - volatile usb_uint tx_addr; - volatile usb_uint tx_count; - volatile usb_uint rx_addr; - volatile usb_uint rx_count; -}; - -extern struct stm32_endpoint btable_ep[]; - -/* Attribute to put the endpoint table in USB RAM */ -#define __usb_btable __attribute__((section(".usb_ram.00_btable"))) - -/* Read from USB RAM into a usb_setup_packet struct */ -struct usb_setup_packet; -void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet); - -/* - * Copy data to and from the USB dedicated RAM and take care of the weird - * addressing. These functions correctly handle unaligned accesses to the USB - * memory. They have the same prototype as memcpy, allowing them to be used - * in places that expect memcpy. The void pointer used to represent a location - * in the USB dedicated RAM should be the offset in that address space, not the - * AHB address space. - * - * The USB packet RAM is attached to the processor via the AHB2APB bridge. This - * bridge performs manipulations of read and write accesses as per the note in - * section 2.1 of RM0091. The upshot is that custom memcpy-like routines need - * to be employed. - */ -void *memcpy_to_usbram(void *dest, const void *src, size_t n); -void *memcpy_from_usbram(void *dest, const void *src, size_t n); - -/* - * Descriptor patching support, useful to change a few values in the descriptor - * (typically, length or bitfields) without having to move descriptors to RAM. - */ - -enum usb_desc_patch_type { -#ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - USB_DESC_KEYBOARD_BACKLIGHT, -#endif - USB_DESC_PATCH_COUNT, -}; - -/* - * Set patch in table: replace uint16_t at address (STM32 flash) with data. - * - * The patches need to be setup before _before_ usb_init is executed (or, at - * least, before the first call to memcpy_to_usbram_ep0_patch). - */ -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data); - -/* Copy to USB ram, applying patches to src as required. */ -void *memcpy_to_usbram_ep0_patch(const void *src, size_t n); - -/* Compute the address inside dedicate SRAM for the USB controller */ -#define usb_sram_addr(x) ((x - __usb_ram_start) * sizeof(uint16_t)) - -/* Helpers for endpoint declaration */ -#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix) -#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx) -#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx) -#define _EP_EVENT_HANDLER(num) _EP_HANDLER2(num, _evt) -/* Used to check function types are correct (attribute alias does not do it) */ -#define _EP_TX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _tx_typecheck) -#define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) -#define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) - -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler - -/* arrays with all endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); -/* array with interface-specific control request callbacks */ -extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); - -/* - * Interface handler returns -1 on error, 0 if it wrote the last chunk of data, - * or 1 if more data needs to be transferred on the next control request. - */ -#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx, \ - usb_uint *epo_buf_tx) \ - __attribute__ ((alias(STRINGIFY(handler)))); - -#endif -#endif /* __CROS_EC_USB_HW_H */ diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c deleted file mode 100644 index 792507aa75..0000000000 --- a/chip/stm32/usb_isochronous.c +++ /dev/null @@ -1,163 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "stddef.h" -#include "common.h" -#include "config.h" -#include "link_defs.h" -#include "registers.h" -#include "util.h" -#include "usb_api.h" -#include "usb_hw.h" -#include "usb_isochronous.h" - - -/* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) - -/* - * Currently, we only support TX direction for USB isochronous transfer. - * - * According to RM0091, isochronous transfer is always double buffered. - * Addresses of buffers are pointed by `btable_ep[<endpoint>].tx_addr` and - * `btable_ep[<endpoint>].rx_addr`. - * - * DTOG | USB Buffer | App Buffer - * -----+------------+----------- - * 0 | tx_addr | rx_addr - * 1 | rx_addr | tx_addr - * - * That is, when DTOG bit is 0 (see `get_tx_dtog()`), USB hardware will read - * from `tx_addr`, and our application can write new data to `rx_addr` at the - * same time. - * - * Number of bytes in each buffer shall be tracked by `tx_count` and `rx_count` - * respectively. - * - * `get_app_addr()`, `set_app_count()` help you to to select the correct - * variable to use by given DTOG value, which is available by `get_tx_dtog()`. - */ - -/* - * Gets current DTOG value of given `config`. - */ -static int get_tx_dtog(struct usb_isochronous_config const *config) -{ - return !!(STM32_USB_EP(config->endpoint) & EP_TX_DTOG); -} - -/* - * Gets buffer address that can be used by software (application). - * - * The mapping between application buffer address and current TX DTOG value is - * shown in table above. - */ -static usb_uint *get_app_addr(struct usb_isochronous_config const *config, - int dtog_value) -{ - return config->tx_ram[dtog_value]; -} - -/* - * Sets number of bytes written to application buffer. - */ -static void set_app_count(struct usb_isochronous_config const *config, - int dtog_value, - usb_uint count) -{ - if (dtog_value) - btable_ep[config->endpoint].tx_count = count; - else - btable_ep[config->endpoint].rx_count = count; -} - -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit) -{ - int dtog_value = get_tx_dtog(config); - usb_uint *buffer = get_app_addr(config, dtog_value); - uintptr_t ptr = usb_sram_addr(buffer); - - if (*buffer_id == -1) - *buffer_id = dtog_value; - else if (dtog_value != *buffer_id) - return -EC_ERROR_TIMEOUT; - - if (dst_offset > config->tx_size) - return -EC_ERROR_INVAL; - - n = MIN(n, config->tx_size - dst_offset); - memcpy_to_usbram((void *)(ptr + dst_offset), src, n); - - if (commit) - set_app_count(config, dtog_value, dst_offset + n); - - return n; -} - -void usb_isochronous_init(struct usb_isochronous_config const *config) -{ - int ep = config->endpoint; - - btable_ep[ep].tx_addr = usb_sram_addr(get_app_addr(config, 1)); - btable_ep[ep].rx_addr = usb_sram_addr(get_app_addr(config, 0)); - set_app_count(config, 0, 0); - set_app_count(config, 1, 0); - - STM32_USB_EP(ep) = ((ep << 0) | /* Endpoint Addr */ - EP_TX_VALID | /* start transmit */ - (2 << 9) | /* ISO EP */ - EP_RX_DISAB); -} - -void usb_isochronous_event(struct usb_isochronous_config const *config, - enum usb_ep_event evt) -{ - if (evt == USB_EVENT_RESET) - usb_isochronous_init(config); -} - -void usb_isochronous_tx(struct usb_isochronous_config const *config) -{ - /* - * Clear CTR_TX, note that EP_TX_VALID will *NOT* be cleared by - * hardware, so we don't need to toggle it. - */ - STM32_TOGGLE_EP(config->endpoint, 0, 0, 0); - /* - * Clear buffer count for buffer we just transmitted, so we do not - * transmit the data twice. - */ - set_app_count(config, get_tx_dtog(config), 0); - - config->tx_callback(config); -} - -int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) -{ - int ret = -1; - - if (ep0_buf_rx[0] == (USB_DIR_OUT | - USB_TYPE_STANDARD | - USB_RECIP_INTERFACE | - USB_REQ_SET_INTERFACE << 8)) { - ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]); - - if (ret == 0) { - /* ACK */ - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); - } - } - return ret; -} diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h deleted file mode 100644 index efa4d94ab4..0000000000 --- a/chip/stm32/usb_isochronous.h +++ /dev/null @@ -1,197 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_ISOCHRONOUS_H -#define __CROS_EC_USB_ISOCHRONOUS_H - -#include "common.h" -#include "compile_time_macros.h" -#include "hooks.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -struct usb_isochronous_config; - -/* - * Currently, we only support TX direction for USB isochronous transfer. - */ - -/* - * Copy `n` bytes from `src` to USB buffer. - * - * We are using double buffering, therefore, we need to write to the buffer that - * hardware is not currently using. This function will handle this for you. - * - * Sample usage: - * - * int buffer_id = -1; // initialize to unknown - * int ret; - * size_t dst_offset = 0, src_offset = 0; - * const uint8_t* buf; - * size_t buf_size; - * - * while (1) { - * buf = ...; - * buf_size = ...; - * if (no more data) { - * buf = NULL; - * break; - * } else { - * ret = usb_isochronous_write_buffer( - * config, buf, buf_size, dst_offset, - * &buffer_id, - * 0); - * if (ret < 0) - * goto FAILED; - * dst_offset += ret; - * if (ret != buf_size) { - * // no more space in TX buffer - * src_offset = ret; - * break; - * } - * } - * } - * // commit - * ret = usb_isochronous_write_buffer( - * config, NULL, 0, dst_offset, - * &buffer_id, 1); - * if (ret < 0) - * goto FAILED; - * if (buf) - * // buf[src_offset ... buf_size] haven't been sent yet, send them - * // later. - * - * On the first invocation, on success, `ret` will be number of bytes that have - * been written, and `buffer_id` will be 0 or 1, depending on which buffer we - * are writing. And commit=0 means there are pending data, so buffer count - * won't be set yet. - * - * On the second invocation, since buffer_id is not -1, we will return an error - * if hardware has switched to this buffer (it means we spent too much time - * filling buffer). And commit=1 means we are done, and buffer count will be - * set to `dst_offset + num_bytes_written` on success. - * - * @return -EC_ERROR_CODE on failure, or number of bytes written on success. - */ -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit); - -struct usb_isochronous_config { - int endpoint; - - /* - * On TX complete, this function will be called in **interrupt - * context**. - * - * @param config the usb_isochronous_config of the USB interface. - */ - void (*tx_callback)(struct usb_isochronous_config const *config); - - /* - * Received SET_INTERFACE request. - * - * @param alternate_setting new bAlternateSetting value. - * @param interface interface number. - * @return int 0 for success, -1 for unknown setting. - */ - int (*set_interface)(usb_uint alternate_setting, usb_uint interface); - - /* USB packet RAM buffer size. */ - size_t tx_size; - /* USB packet RAM buffers. */ - usb_uint *tx_ram[2]; -}; - -/* Define an USB isochronous interface */ -#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - TX_SIZE, \ - TX_CALLBACK, \ - SET_INTERFACE, \ - NUM_EXTRA_ENDPOINTS) \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - /* Declare buffer */ \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \ - struct usb_isochronous_config const NAME = { \ - .endpoint = ENDPOINT, \ - .tx_callback = TX_CALLBACK, \ - .set_interface = SET_INTERFACE, \ - .tx_size = TX_SIZE, \ - .tx_ram = { \ - CONCAT2(NAME, _ep_tx_buffer_0), \ - CONCAT2(NAME, _ep_tx_buffer_1), \ - }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 0, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_interface_descriptor \ - USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 1, \ - .bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x01 /* Isochronous IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 1, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_isochronous_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_isochronous_event(&NAME, evt); \ - } \ - static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx) \ - { \ - return usb_isochronous_iface_handler(&NAME, rx, tx); \ - } \ - USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler)); \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_event)); \ - -void usb_isochronous_tx(struct usb_isochronous_config const *config); -void usb_isochronous_event(struct usb_isochronous_config const *config, - enum usb_ep_event event); -int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx); -#endif /* __CROS_EC_USB_ISOCHRONOUS_H */ diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c deleted file mode 100644 index 90506d8975..0000000000 --- a/chip/stm32/usb_pd_phy.c +++ /dev/null @@ -1,680 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "adc.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "crc.h" -#include "dma.h" -#include "gpio.h" -#include "hwtimer.h" -#include "hooks.h" -#include "registers.h" -#include "system.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "usb_pd.h" -#include "usb_pd_config.h" - -#ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#else -#define CPRINTF(format, args...) -#define CPRINTS(format, args...) -#endif - -#define PD_DATARATE 300000 /* Hz */ - -/* - * Maximum size of a Power Delivery packet (in bits on the wire) : - * 16-bit header + 0..7 32-bit data objects (+ 4b5b encoding) - * 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b) - * = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5 - */ -#define PD_BIT_LEN 429 - -#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2) - -/* maximum number of consecutive similar bits with Biphase Mark Coding */ -#define MAX_BITS 2 - -/* alternating bit sequence used for packet preamble : 00 10 11 01 00 .. */ -#define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */ - -#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE))) - -/* threshold for 1 300-khz period */ -#define PERIOD 4 -#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD) -#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2) - -static struct pd_physical { - /* samples for the PD messages */ - uint32_t raw_samples[DIV_ROUND_UP(PD_MAX_RAW_SIZE, sizeof(uint32_t))]; - - /* state of the bit decoder */ - int d_toggle; - int d_lastlen; - uint32_t d_last; - int b_toggle; - - /* DMA structures for each PD port */ - struct dma_option dma_tx_option; - struct dma_option dma_tim_option; - - /* Pointers to timer register for each port */ - timer_ctlr_t *tim_tx; - timer_ctlr_t *tim_rx; -} pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT]; - -/* keep track of RX edge timing in order to trigger receive */ -static timestamp_t - rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT]; -static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT]; - -/* keep track of transmit polarity for DMA interrupt */ -static int tx_dma_polarities[CONFIG_USB_PD_PORT_MAX_COUNT]; - -void pd_init_dequeue(int port) -{ - /* preamble ends with 1 */ - pd_phy[port].d_toggle = 0; - pd_phy[port].d_last = 0; - pd_phy[port].d_lastlen = 0; -} - -static int wait_bits(int port, int nb) -{ - int avail; - stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port)); - - avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE); - if (avail < nb) { /* no received yet ... */ - while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) - && !(pd_phy[port].tim_rx->sr & 4)) - ; /* optimized for latency, not CPU usage ... */ - if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) { - CPRINTS("PD TMOUT RX %d/%d", - dma_bytes_done(rx, PD_MAX_RAW_SIZE), nb); - return -1; - } - } - return nb; -} - -int pd_dequeue_bits(int port, int off, int len, uint32_t *val) -{ - int w; - uint8_t cnt = 0xff; - uint8_t *samples = (uint8_t *)pd_phy[port].raw_samples; - - while ((pd_phy[port].d_lastlen < len) && (off < PD_MAX_RAW_SIZE - 1)) { - w = wait_bits(port, off + 2); - if (w < 0) - goto stream_err; - cnt = samples[off] - samples[off-1]; - if (!cnt || (cnt > 3*PERIOD)) - goto stream_err; - off++; - if (cnt <= PERIOD_THRESHOLD) { - /* - w = wait_bits(port, off + 1); - if (w < 0) - goto stream_err; - */ - cnt = samples[off] - samples[off-1]; - if (cnt > PERIOD_THRESHOLD) - goto stream_err; - off++; - } - - /* enqueue the bit of the last period */ - pd_phy[port].d_last = (pd_phy[port].d_last >> 1) - | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0); - pd_phy[port].d_lastlen++; - } - if (off < PD_MAX_RAW_SIZE) { - *val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len)) - >> (32 - len); - pd_phy[port].d_lastlen -= len; - return off; - } else { - return -1; - } -stream_err: - /* CPRINTS("PD Invalid %d @%d", cnt, off); */ - return -1; -} - -int pd_find_preamble(int port) -{ - int bit; - uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples; - - /* - * Detect preamble - * Alternate 1-period 1-period & 2-period. - */ - uint32_t all = 0; - stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX(port)); - - for (bit = 1; bit < PD_MAX_RAW_SIZE - 1; bit++) { - uint8_t cnt; - /* wait if the bit is not received yet ... */ - if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) { - while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) && - !(pd_phy[port].tim_rx->sr & 4)) - ; - if (pd_phy[port].tim_rx->sr & 4) { - CPRINTS("PD TMOUT RX %d/%d", - PD_MAX_RAW_SIZE - rx->cndtr, bit); - return -1; - } - } - cnt = vals[bit] - vals[bit-1]; - all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0); - if (all == 0x36db6db6) - return bit - 1; /* should be SYNC-1 */ - if (all == 0xF33F3F3F) - return PD_RX_ERR_HARD_RESET; /* got HARD-RESET */ - if (all == 0x3c7fe0ff) - return PD_RX_ERR_CABLE_RESET; /* got CABLE-RESET */ - } - return -1; -} - -int pd_write_preamble(int port) -{ - uint32_t *msg = pd_phy[port].raw_samples; - - /* 64-bit x2 preamble */ - msg[0] = PD_PREAMBLE; - msg[1] = PD_PREAMBLE; - msg[2] = PD_PREAMBLE; - msg[3] = PD_PREAMBLE; - pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */ - return 2*64; -} - -int pd_write_sym(int port, int bit_off, uint32_t val10) -{ - uint32_t *msg = pd_phy[port].raw_samples; - int word_idx = bit_off / 32; - int bit_idx = bit_off % 32; - uint32_t val = pd_phy[port].b_toggle ^ val10; - pd_phy[port].b_toggle = val & 0x200 ? 0x3FF : 0; - if (bit_idx <= 22) { - if (bit_idx == 0) - msg[word_idx] = 0; - msg[word_idx] |= val << bit_idx; - } else { - msg[word_idx] |= val << bit_idx; - msg[word_idx+1] = val >> (32 - bit_idx); - /* side effect: clear the new word when starting it */ - } - return bit_off + 5*2; -} - -int pd_write_last_edge(int port, int bit_off) -{ - uint32_t *msg = pd_phy[port].raw_samples; - int word_idx = bit_off / 32; - int bit_idx = bit_off % 32; - - if (bit_idx == 0) - msg[word_idx] = 0; - - if (!pd_phy[port].b_toggle /* last bit was 0 */) { - /* transition to 1, another 1, then 0 */ - if (bit_idx == 31) { - msg[word_idx++] |= 1 << bit_idx; - msg[word_idx] = 1; - } else { - msg[word_idx] |= 3 << bit_idx; - } - } - /* ensure that the trailer is 0 */ - msg[word_idx+1] = 0; - - return bit_off + 3; -} - -#ifdef CONFIG_COMMON_RUNTIME -void pd_dump_packet(int port, const char *msg) -{ - uint8_t *vals = (uint8_t *)pd_phy[port].raw_samples; - int bit; - - CPRINTF("ERR %s:\n000:- ", msg); - /* Packet debug output */ - for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) { - int cnt = NB_PERIOD(vals[bit-1], vals[bit]); - if ((bit & 31) == 0) - CPRINTF("\n%03d:", bit); - CPRINTF("%1d ", cnt); - } - CPRINTF("><\n"); - cflush(); - for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) { - if ((bit & 31) == 0) - CPRINTF("\n%03d:", bit); - CPRINTF("%02x ", vals[bit]); - } - CPRINTF("||\n"); - cflush(); -} -#endif /* CONFIG_COMMON_RUNTIME */ - -/* --- SPI TX operation --- */ - -void pd_tx_spi_init(int port) -{ - stm32_spi_regs_t *spi = SPI_REGS(port); - - /* Enable Tx DMA for our first transaction */ - spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8); - - /* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */ - spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST - | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE - | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA; -} - -static void tx_dma_done(void *data) -{ - int port = (int)data; - int polarity = tx_dma_polarities[port]; - stm32_spi_regs_t *spi = SPI_REGS(port); - - while (spi->sr & STM32_SPI_SR_FTLVL) - ; /* wait for TX FIFO empty */ - while (spi->sr & STM32_SPI_SR_BSY) - ; /* wait for BSY == 0 */ - - /* Stop counting */ - pd_phy[port].tim_tx->cr1 &= ~1; - - /* put TX pins and reference in Hi-Z */ - pd_tx_disable(port, polarity); - -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - task_set_event(PD_PORT_TO_TASK_ID(port), TASK_EVENT_DMA_TC); -#endif -} - -int pd_start_tx(int port, int polarity, int bit_len) -{ - stm32_dma_chan_t *tx = dma_get_channel(DMAC_SPI_TX(port)); - -#ifndef CONFIG_USB_PD_TX_PHY_ONLY - /* disable RX detection interrupt */ - pd_rx_disable_monitoring(port); - - /* Check that we are not receiving a frame to avoid collisions */ - if (pd_rx_started(port)) - return -5; -#endif /* !CONFIG_USB_PD_TX_PHY_ONLY */ - - /* Initialize spi peripheral to prepare for transmission. */ - pd_tx_spi_init(port); - - /* - * Set timer to one tick before reset so that the first tick causes - * a rising edge on the output. - */ - pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1; - - /* update DMA configuration */ - dma_prepare_tx(&(pd_phy[port].dma_tx_option), - DIV_ROUND_UP(bit_len, 8), - pd_phy[port].raw_samples); - /* Flush data in write buffer so that DMA can get the latest data */ - asm volatile("dmb;"); - - /* Kick off the DMA to send the data */ - dma_clear_isr(DMAC_SPI_TX(port)); -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - tx_dma_polarities[port] = polarity; - if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) { - /* Only enable interrupt if not in circular mode */ - dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port), - &tx_dma_done, - (void *)port); - } -#endif - dma_go(tx); - - /* - * Drive the CC line from the TX block : - * - put SPI function on TX pin. - * - set the low level reference. - * Call this last before enabling timer in order to meet spec on - * timing between enabling TX and clocking out bits. - */ - pd_tx_enable(port, polarity); - - /* Start counting at 300Khz*/ - pd_phy[port].tim_tx->cr1 |= 1; - - return bit_len; -} - -void pd_tx_done(int port, int polarity) -{ -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - /* wait for DMA, DMA interrupt will stop the SPI clock */ - task_wait_event_mask(TASK_EVENT_DMA_TC, DMA_TRANSFER_TIMEOUT_US); - dma_disable_tc_interrupt(DMAC_SPI_TX(port)); -#else - tx_dma_polarities[port] = polarity; - tx_dma_done((void *)port); -#endif - - /* Reset SPI to clear remaining data in buffer */ - pd_tx_spi_reset(port); -} - -void pd_tx_set_circular_mode(int port) -{ - pd_phy[port].dma_tx_option.flags |= STM32_DMA_CCR_CIRC; -} - -void pd_tx_clear_circular_mode(int port) -{ - /* clear the circular mode bit in flag variable */ - pd_phy[port].dma_tx_option.flags &= ~STM32_DMA_CCR_CIRC; - /* disable dma transaction underway */ - dma_disable(DMAC_SPI_TX(port)); -#if defined(CONFIG_COMMON_RUNTIME) && defined(CONFIG_DMA_DEFAULT_HANDLERS) - tx_dma_done((void *)port); -#endif -} - -/* --- RX operation using comparator linked to timer --- */ - -void pd_rx_start(int port) -{ - /* start sampling the edges on the CC line using the RX timer */ - dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE, - pd_phy[port].raw_samples); - /* enable TIM2 DMA requests */ - pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */; - pd_phy[port].tim_rx->sr = 0; /* clear overflows */ - pd_phy[port].tim_rx->cr1 |= 1; -} - -void pd_rx_complete(int port) -{ - /* stop stampling TIM2 */ - pd_phy[port].tim_rx->cr1 &= ~1; - /* stop DMA */ - dma_disable(DMAC_TIM_RX(port)); -} - -int pd_rx_started(int port) -{ - /* is the sampling timer running ? */ - return pd_phy[port].tim_rx->cr1 & 1; -} - -void pd_rx_enable_monitoring(int port) -{ - /* clear comparator external interrupt */ - STM32_EXTI_PR = EXTI_COMP_MASK(port); - /* enable comparator external interrupt */ - STM32_EXTI_IMR |= EXTI_COMP_MASK(port); -} - -void pd_rx_disable_monitoring(int port) -{ - /* disable comparator external interrupt */ - STM32_EXTI_IMR &= ~EXTI_COMP_MASK(port); - /* clear comparator external interrupt */ - STM32_EXTI_PR = EXTI_COMP_MASK(port); -} - -uint64_t get_time_since_last_edge(int port) -{ - int prev_idx = (rx_edge_ts_idx[port] == 0) ? - PD_RX_TRANSITION_COUNT - 1 : - rx_edge_ts_idx[port] - 1; - return get_time().val - rx_edge_ts[port][prev_idx].val; -} - -/* detect an edge on the PD RX pin */ -void pd_rx_handler(void) -{ - int pending, i; - int next_idx; - pending = STM32_EXTI_PR; - -#ifdef CONFIG_USB_CTVPD - /* Charge-Through Side detach event */ - if (pending & EXTI_COMP2_MASK) { - task_wake(PD_PORT_TO_TASK_ID(0)); - /* Clear interrupt */ - STM32_EXTI_PR = EXTI_COMP2_MASK; - pending &= ~EXTI_COMP2_MASK; - } -#endif - - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (pending & EXTI_COMP_MASK(i)) { - rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val; - next_idx = (rx_edge_ts_idx[i] == - PD_RX_TRANSITION_COUNT - 1) ? - 0 : rx_edge_ts_idx[i] + 1; - -#if defined(CONFIG_LOW_POWER_IDLE) && \ -defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) - /* - * Do not deep sleep while waiting for more edges. For - * most boards, sleep is already disabled due to being - * in PD connected state, but boards which define - * CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED can - * sleep while connected. - */ - disable_sleep(SLEEP_MASK_USB_PD); -#endif - - /* - * If we have seen enough edges in a certain amount of - * time, then trigger RX start. - */ - if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val - - rx_edge_ts[i][next_idx].val) - < PD_RX_TRANSITION_WINDOW) { - /* start sampling */ - pd_rx_start(i); - /* - * ignore the comparator IRQ until we are done - * with current message - */ - pd_rx_disable_monitoring(i); - /* trigger the analysis in the task */ - pd_rx_event(i); - } else { - /* do not trigger RX start, just clear int */ - STM32_EXTI_PR = EXTI_COMP_MASK(i); - } - rx_edge_ts_idx[i] = next_idx; - } - } -} -#ifdef CONFIG_USB_PD_RX_COMP_IRQ -DECLARE_IRQ(STM32_IRQ_COMP, pd_rx_handler, 1); -#endif - -/* --- release hardware --- */ -void pd_hw_release(int port) -{ - __hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 0); - __hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 0); - dma_disable(DMAC_SPI_TX(port)); -} - -/* --- Startup initialization --- */ - -void pd_hw_init_rx(int port) -{ - struct pd_physical *phy = &pd_phy[port]; - - /* configure registers used for timers */ - phy->tim_rx = (void *)TIM_REG_RX(port); - - /* configure RX DMA */ - phy->dma_tim_option.channel = DMAC_TIM_RX(port); - phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port)); - phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_16_BIT; - - /* --- set counter for RX timing : 2.4Mhz rate, free-running --- */ - __hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1); - /* Timer configuration */ - phy->tim_rx->cr1 = 0x0000; - phy->tim_rx->cr2 = 0x0000; - phy->tim_rx->dier = 0x0000; - /* Auto-reload value : 16-bit free running counter */ - phy->tim_rx->arr = 0xFFFF; - - /* Timeout for message receive */ - phy->tim_rx->ccr[2] = (2400000 / 1000) * USB_PD_RX_TMOUT_US / 1000; - /* Timer ICx input configuration */ - if (TIM_RX_CCR_IDX(port) == 1) - phy->tim_rx->ccmr1 |= TIM_CCR_CS << 0; - else if (TIM_RX_CCR_IDX(port) == 2) - phy->tim_rx->ccmr1 |= TIM_CCR_CS << 8; - else if (TIM_RX_CCR_IDX(port) == 4) - phy->tim_rx->ccmr2 |= TIM_CCR_CS << 8; - else - /* Unsupported RX timer capture input */ - ASSERT(0); - - phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4); - /* configure DMA request on CCRx update */ - phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */; - /* set prescaler to /26 (F=1.2Mhz, T=0.8us) */ - phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1; - /* Reload the pre-scaler and reset the counter (clear CCRx) */ - phy->tim_rx->egr = 0x0001 | (1 << TIM_RX_CCR_IDX(port)); - /* clear update event from reloading */ - phy->tim_rx->sr = 0; - - /* --- DAC configuration for comparator at 850mV --- */ -#ifdef CONFIG_PD_USE_DAC_AS_REF - /* Enable DAC interface clock. */ - STM32_RCC_APB1ENR |= BIT(29); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - /* set voltage Vout=0.850V (Vref = 3.0V) */ - STM32_DAC_DHR12RD = 850 * 4096 / 3000; - /* Start DAC channel 1 */ - STM32_DAC_CR = STM32_DAC_CR_EN1; -#endif - - /* --- COMP2 as comparator for RX vs Vmid = 850mV --- */ -#ifdef CONFIG_USB_PD_INTERNAL_COMP -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) - /* turn on COMP/SYSCFG */ - STM32_RCC_APB2ENR |= BIT(0); - /* Delay 1 APB clock cycle after the clock is enabled */ - clock_wait_bus_cycles(BUS_APB, 1); - /* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */ - STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED | - STM32_COMP_CMP1INSEL_INM6 | - CMP1OUTSEL | - STM32_COMP_CMP1HYST_HI | - STM32_COMP_CMP2MODE_LSPEED | - STM32_COMP_CMP2INSEL_INM6 | - CMP2OUTSEL | - STM32_COMP_CMP2HYST_HI; -#elif defined(CHIP_FAMILY_STM32L) - STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */ - - STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1 - | STM32_COMP_SPEED_FAST; - /* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */ - STM32_RI_ASCR2 |= BIT(4); -#else -#error Unsupported chip family -#endif -#endif /* CONFIG_USB_PD_INTERNAL_COMP */ - - /* comparator interrupt setup */ - EXTI_XTSR |= EXTI_COMP_MASK(port); - STM32_EXTI_IMR |= EXTI_COMP_MASK(port); - task_enable_irq(IRQ_COMP); -} - -void pd_hw_init(int port, enum pd_power_role role) -{ - struct pd_physical *phy = &pd_phy[port]; - uint32_t val; - - /* Initialize all PD pins to default state based on desired role */ - pd_config_init(port, role); - - /* set 40 MHz pin speed on communication pins */ - pd_set_pins_speed(port); - - /* --- SPI init --- */ - - /* Enable clocks to SPI module */ - spi_enable_clock(port); - - /* Initialize SPI peripheral registers */ - pd_tx_spi_init(port); - - /* configure TX DMA */ - phy->dma_tx_option.channel = DMAC_SPI_TX(port); - phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr; - phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT; - dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE, - phy->raw_samples); - - /* configure registers used for timers */ - phy->tim_tx = (void *)TIM_REG_TX(port); - - /* --- set the TX timer with updates at 600KHz (BMC frequency) --- */ - __hw_timer_enable_clock(TIM_CLOCK_PD_TX(port), 1); - /* Timer configuration */ - phy->tim_tx->cr1 = 0x0000; - phy->tim_tx->cr2 = 0x0000; - phy->tim_tx->dier = 0x0000; - /* Auto-reload value : 600000 Khz overflow */ - phy->tim_tx->arr = TX_CLOCK_DIV; - /* 50% duty cycle on the output */ - phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2; - /* Timer channel output configuration */ - val = (6 << 4) | BIT(3); - if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */ - val <<= 8; - if (TIM_TX_CCR_IDX(port) <= 2) - phy->tim_tx->ccmr1 = val; - else - phy->tim_tx->ccmr2 = val; - - phy->tim_tx->ccer = 1 << ((TIM_TX_CCR_IDX(port) - 1) * 4); - phy->tim_tx->bdtr = 0x8000; - /* set prescaler to /1 */ - phy->tim_tx->psc = 0; - /* Reload the pre-scaler and reset the counter */ - phy->tim_tx->egr = 0x0001; -#ifndef CONFIG_USB_PD_TX_PHY_ONLY - /* Configure the reception side : comparators + edge timer + DMA */ - pd_hw_init_rx(port); -#endif /* CONFIG_USB_PD_TX_PHY_ONLY */ - - CPRINTS("USB PD initialized"); -} - -void pd_set_clock(int port, int freq) -{ - pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq); -} diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c deleted file mode 100644 index 24dbff06cd..0000000000 --- a/chip/stm32/usb_power.c +++ /dev/null @@ -1,733 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "dma.h" -#include "hooks.h" -#include "i2c.h" -#include "link_defs.h" -#include "registers.h" -#include "timer.h" -#include "usb_descriptor.h" -#include "usb_power.h" -#include "util.h" - -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) - -static int usb_power_init_inas(struct usb_power_config const *config); -static int usb_power_read(struct usb_power_config const *config); -static int usb_power_write_line(struct usb_power_config const *config); - -void usb_power_deferred_rx(struct usb_power_config const *config) -{ - int rx_count = rx_ep_pending(config->endpoint); - - /* Handle an incoming command if available */ - if (rx_count) - usb_power_read(config); -} - -void usb_power_deferred_tx(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - - if (!tx_ep_is_ready(config->endpoint)) - return; - - /* We've replied, set up the next read. */ - if (!rx_ep_is_active(config->endpoint)) { - /* Remove any active dma region from output buffer */ - state->reports_xmit_active = state->reports_tail; - - /* Wait for the next command */ - usb_read_ep(config->endpoint, - config->ep->out_databuffer_max, - config->ep->out_databuffer); - return; - } -} - -/* Reset stream */ -void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt) -{ - if (evt != USB_EVENT_RESET) - return; - - config->ep->out_databuffer = config->state->rx_buf; - config->ep->out_databuffer_max = sizeof(config->state->rx_buf); - config->ep->in_databuffer = config->state->tx_buf; - config->ep->in_databuffer_max = sizeof(config->state->tx_buf); - - epN_reset(config->endpoint); - - /* Flush any queued data */ - hook_call_deferred(config->ep->rx_deferred, 0); - hook_call_deferred(config->ep->tx_deferred, 0); -} - - -/* Write one or more power records to USB */ -static int usb_power_write_line(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_tail)); - /* status + size + timestamps + power list */ - size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count); - - /* Check if queue has active data. */ - if (config->state->reports_head != config->state->reports_tail) { - int recordcount = 1; - - /* We'll concatenate all the upcoming recrds. */ - if (config->state->reports_tail < config->state->reports_head) - recordcount = config->state->reports_head - - config->state->reports_tail; - else - recordcount = state->max_cached - - config->state->reports_tail; - - state->reports_xmit_active = state->reports_tail; - state->reports_tail = (state->reports_tail + recordcount) % - state->max_cached; - - usb_write_ep(config->endpoint, bytes * recordcount, r); - return bytes; - } - - return 0; -} - - -static int usb_power_state_reset(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - - state->state = USB_POWER_STATE_OFF; - state->reports_head = 0; - state->reports_tail = 0; - state->reports_xmit_active = 0; - - CPRINTS("[RESET] STATE -> OFF"); - return USB_POWER_SUCCESS; -} - - -static int usb_power_state_stop(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - - /* Only a valid transition from CAPTURING */ - if (state->state != USB_POWER_STATE_CAPTURING) { - CPRINTS("[STOP] Error not capturing."); - return USB_POWER_ERROR_NOT_CAPTURING; - } - - state->state = USB_POWER_STATE_OFF; - state->reports_head = 0; - state->reports_tail = 0; - state->reports_xmit_active = 0; - state->stride_bytes = 0; - CPRINTS("[STOP] STATE: CAPTURING -> OFF"); - return USB_POWER_SUCCESS; -} - - - -static int usb_power_state_start(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) -{ - struct usb_power_state *state = config->state; - int integration_us = cmd->start.integration_us; - int ret; - - if (state->state != USB_POWER_STATE_SETUP) { - CPRINTS("[START] Error not setup."); - return USB_POWER_ERROR_NOT_SETUP; - } - - if (count != sizeof(struct usb_power_command_start)) { - CPRINTS("[START] Error count %d is not %d", (int)count, - sizeof(struct usb_power_command_start)); - return USB_POWER_ERROR_READ_SIZE; - } - - if (integration_us == 0) { - CPRINTS("[START] integration_us cannot be 0"); - return USB_POWER_ERROR_UNKNOWN; - } - - /* Calculate the reports array */ - state->stride_bytes = USB_POWER_RECORD_SIZE(state->ina_count); - state->max_cached = USB_POWER_MAX_CACHED(state->ina_count); - - state->integration_us = integration_us; - ret = usb_power_init_inas(config); - - if (ret) - return USB_POWER_ERROR_INVAL; - - state->state = USB_POWER_STATE_CAPTURING; - CPRINTS("[START] STATE: SETUP -> CAPTURING %dus", integration_us); - - /* Find our starting time. */ - config->state->base_time = get_time().val; - - hook_call_deferred(config->deferred_cap, state->integration_us); - return USB_POWER_SUCCESS; -} - - -static int usb_power_state_settime(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) -{ - if (count != sizeof(struct usb_power_command_settime)) { - CPRINTS("[SETTIME] Error: count %d is not %d", - (int)count, sizeof(struct usb_power_command_settime)); - return USB_POWER_ERROR_READ_SIZE; - } - - /* Find the offset between microcontroller clock and host clock. */ - if (cmd->settime.time) - config->state->wall_offset = cmd->settime.time - get_time().val; - else - config->state->wall_offset = 0; - - return USB_POWER_SUCCESS; -} - - -static int usb_power_state_addina(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) -{ - struct usb_power_state *state = config->state; - struct usb_power_ina_cfg *ina; - int i; - - /* Only valid from OFF or SETUP */ - if ((state->state != USB_POWER_STATE_OFF) && - (state->state != USB_POWER_STATE_SETUP)) { - CPRINTS("[ADDINA] Error incorrect state."); - return USB_POWER_ERROR_NOT_SETUP; - } - - if (count != sizeof(struct usb_power_command_addina)) { - CPRINTS("[ADDINA] Error count %d is not %d", - (int)count, sizeof(struct usb_power_command_addina)); - return USB_POWER_ERROR_READ_SIZE; - } - - if (state->ina_count >= USB_POWER_MAX_READ_COUNT) { - CPRINTS("[ADDINA] Error INA list full"); - return USB_POWER_ERROR_FULL; - } - - /* Transition to SETUP state if necessary and clear INA data */ - if (state->state == USB_POWER_STATE_OFF) { - state->state = USB_POWER_STATE_SETUP; - state->ina_count = 0; - } - - if ((cmd->addina.type < USBP_INA231_POWER) || - (cmd->addina.type > USBP_INA231_SHUNTV)) { - CPRINTS("[ADDINA] Error INA type 0x%x invalid", - (int)(cmd->addina.type)); - return USB_POWER_ERROR_INVAL; - } - - if (cmd->addina.rs == 0) { - CPRINTS("[ADDINA] Error INA resistance cannot be zero!"); - return USB_POWER_ERROR_INVAL; - } - - /* Select INA to configure */ - ina = state->ina_cfg + state->ina_count; - - ina->port = cmd->addina.port; - ina->addr_flags = cmd->addina.addr_flags; - ina->rs = cmd->addina.rs; - ina->type = cmd->addina.type; - - /* - * INAs can be shared, in that they will have various values - * (and therefore registers) read from them each cycle, including - * power, voltage, current. If only a single value is read, - * we an use i2c_readagain for faster transactions as we don't - * have to respecify the address. - */ - ina->shared = 0; -#ifdef USB_POWER_VERBOSE - ina->shared = 1; -#endif - - /* Check if shared with previously configured INAs. */ - for (i = 0; i < state->ina_count; i++) { - struct usb_power_ina_cfg *tmp = state->ina_cfg + i; - - if ((tmp->port == ina->port) && - (tmp->addr_flags == ina->addr_flags)) { - ina->shared = 1; - tmp->shared = 1; - } - } - - state->ina_count += 1; - return USB_POWER_SUCCESS; -} - -static int usb_power_read(struct usb_power_config const *config) -{ - /* - * If there is a USB packet waiting we process it and generate a - * response. - */ - uint8_t count = rx_ep_pending(config->endpoint); - uint8_t result = USB_POWER_SUCCESS; - union usb_power_command_data *cmd = - (union usb_power_command_data *)config->ep->out_databuffer; - - struct usb_power_state *state = config->state; - struct dwc_usb_ep *ep = config->ep; - - /* Bytes to return */ - int in_msgsize = 1; - - if (count < 2) - return EC_ERROR_INVAL; - - /* State machine. */ - switch (cmd->command) { - case USB_POWER_CMD_RESET: - result = usb_power_state_reset(config); - break; - - case USB_POWER_CMD_STOP: - result = usb_power_state_stop(config); - break; - - case USB_POWER_CMD_START: - result = usb_power_state_start(config, cmd, count); - if (result == USB_POWER_SUCCESS) { - /* Send back actual integration time. */ - ep->in_databuffer[1] = - (state->integration_us >> 0) & 0xff; - ep->in_databuffer[2] = - (state->integration_us >> 8) & 0xff; - ep->in_databuffer[3] = - (state->integration_us >> 16) & 0xff; - ep->in_databuffer[4] = - (state->integration_us >> 24) & 0xff; - in_msgsize += 4; - } - break; - - case USB_POWER_CMD_ADDINA: - result = usb_power_state_addina(config, cmd, count); - break; - - case USB_POWER_CMD_SETTIME: - result = usb_power_state_settime(config, cmd, count); - break; - - case USB_POWER_CMD_NEXT: - if (state->state == USB_POWER_STATE_CAPTURING) { - int ret; - - ret = usb_power_write_line(config); - if (ret) - return EC_SUCCESS; - - result = USB_POWER_ERROR_BUSY; - } else { - CPRINTS("[STOP] Error not capturing."); - result = USB_POWER_ERROR_NOT_CAPTURING; - } - break; - - default: - CPRINTS("[ERROR] Unknown command 0x%04x", (int)cmd->command); - result = USB_POWER_ERROR_UNKNOWN; - break; - } - - /* Return result code if applicable. */ - ep->in_databuffer[0] = result; - - usb_write_ep(config->endpoint, in_msgsize, ep->in_databuffer); - - return EC_SUCCESS; -} - - - -/****************************************************************************** - * INA231 interface. - * List the registers and fields here. - * TODO(nsanders): combine with the currently incompatible common INA drivers. - */ - -#define INA231_REG_CONF 0 -#define INA231_REG_RSHV 1 -#define INA231_REG_BUSV 2 -#define INA231_REG_PWR 3 -#define INA231_REG_CURR 4 -#define INA231_REG_CAL 5 -#define INA231_REG_EN 6 - - -#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9) -#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6) -#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3) -#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0) -#define INA231_MODE_OFF 0x0 -#define INA231_MODE_SHUNT 0x5 -#define INA231_MODE_BUS 0x6 -#define INA231_MODE_BOTH 0x7 - -int reg_type_mapping(enum usb_power_ina_type ina_type) -{ - switch (ina_type) { - case USBP_INA231_POWER: - return INA231_REG_PWR; - case USBP_INA231_BUSV: - return INA231_REG_BUSV; - case USBP_INA231_CURRENT: - return INA231_REG_CURR; - case USBP_INA231_SHUNTV: - return INA231_REG_RSHV; - - default: - return INA231_REG_CONF; - } -} - -uint16_t ina2xx_readagain(uint8_t port, uint16_t slave_addr_flags) -{ - int res; - uint16_t val; - - res = i2c_xfer(port, slave_addr_flags, - NULL, 0, (uint8_t *)&val, sizeof(uint16_t)); - - if (res) { - CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", - (int)port, (int)I2C_STRIP_FLAGS(slave_addr_flags)); - return 0x0bad; - } - return (val >> 8) | ((val & 0xff) << 8); -} - - -uint16_t ina2xx_read(uint8_t port, uint16_t slave_addr_flags, - uint8_t reg) -{ - int res; - int val; - - res = i2c_read16(port, slave_addr_flags, reg, &val); - if (res) { - CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", - (int)port, (int)I2C_STRIP_FLAGS(slave_addr_flags), - (int)reg); - return 0x0bad; - } - return (val >> 8) | ((val & 0xff) << 8); -} - -int ina2xx_write(uint8_t port, uint16_t slave_addr_flags, - uint8_t reg, uint16_t val) -{ - int res; - uint16_t be_val = (val >> 8) | ((val & 0xff) << 8); - - res = i2c_write16(port, slave_addr_flags, reg, be_val); - if (res) - CPRINTS("INA2XX I2C write failed"); - return res; -} - - - -/****************************************************************************** - * Background tasks - * - * Here we setup the INAs and read them at the specified interval. - * INA samples are stored in a ringbuffer that can be fetched using the - * USB commands. - */ - -/* INA231 integration and averaging time presets, indexed by register value */ -#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) -static const int average_settings[] = { - 1, 4, 16, 64, 128, 256, 512, 1024}; -static const int conversion_time_us[] = { - 140, 204, 332, 588, 1100, 2116, 4156, 8244}; - -static int usb_power_init_inas(struct usb_power_config const *config) -{ - struct usb_power_state *state = config->state; - int i; - int shunt_time = 0; - int avg = 0; - int target_us = state->integration_us; - - if (state->state != USB_POWER_STATE_SETUP) { - CPRINTS("[ERROR] usb_power_init_inas while not SETUP"); - return -1; - } - - /* Find an INA preset integration time less than specified */ - while (shunt_time < (NELEMS(conversion_time_us) - 1)) { - if (conversion_time_us[shunt_time + 1] > target_us) - break; - shunt_time++; - } - - /* Find an averaging setting from the INA presets that fits. */ - while (avg < (NELEMS(average_settings) - 1)) { - if ((conversion_time_us[shunt_time] * - average_settings[avg + 1]) - > target_us) - break; - avg++; - } - - state->integration_us = - conversion_time_us[shunt_time] * average_settings[avg]; - - for (i = 0; i < state->ina_count; i++) { - int value; - int ret; - struct usb_power_ina_cfg *ina = state->ina_cfg + i; - -#ifdef USB_POWER_VERBOSE - { - int conf, cal; - - conf = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - cal = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - conf, cal); - } -#endif - /* - * Calculate INA231 Calibration register - * CurrentLSB = uA per div = 80mV / (Rsh * 2^15) - * CurrentLSB 100x uA = 100x 80000000nV / (Rsh mOhm * 0x8000) - */ - /* TODO: allow voltage readings if no sense resistor. */ - if (ina->rs == 0) - return -1; - - ina->scale = (100 * (80000000 / 0x8000)) / ina->rs; - - /* - * CAL = .00512 / (CurrentLSB * Rsh) - * CAL = 5120000 / (uA * mOhm) - */ - if (ina->scale == 0) - return -1; - value = (5120000 * 100) / (ina->scale * ina->rs); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CAL, value); - if (ret != EC_SUCCESS) { - CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret); - return ret; - } -#ifdef USB_POWER_VERBOSE - { - int actual; - - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x", - ina->scale / 100, ina->scale*25/100, value, actual); - } -#endif - /* Conversion time, shunt + bus, set average. */ - value = INA231_CONF_MODE(INA231_MODE_BOTH) | - INA231_CONF_SHUNT_TIME(shunt_time) | - INA231_CONF_BUS_TIME(shunt_time) | - INA231_CONF_AVG(avg); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CONF, value); - if (ret != EC_SUCCESS) { - CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret); - return ret; - } -#ifdef USB_POWER_VERBOSE - { - int actual; - - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - value, actual); - } -#endif -#ifdef USB_POWER_VERBOSE - { - int busv_mv = - (ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV) - * 125) / 100; - - CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - busv_mv); - } -#endif - /* Initialize read from power register. This register address - * will be cached and all ina2xx_readagain() calls will read - * from the same address. - */ - ina2xx_read(ina->port, ina->addr_flags, - reg_type_mapping(ina->type)); -#ifdef USB_POWER_VERBOSE - CPRINTS("[CAP] %d (%d,0x%02x): type:%d", (int)(ina->type)); -#endif - } - - return EC_SUCCESS; -} - - -/* - * Read each INA's power integration measurement. - * - * INAs recall the most recent address, so no register access write is - * necessary, simply read 16 bits from each INA and fill the result into - * the power record. - * - * If the power record ringbuffer is full, fail with USB_POWER_ERROR_OVERFLOW. - */ -static int usb_power_get_samples(struct usb_power_config const *config) -{ - uint64_t time = get_time().val; - struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_head)); - struct usb_power_ina_cfg *inas = state->ina_cfg; - int i; - - /* TODO(nsanders): Would we prefer to evict oldest? */ - if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count)) - == state->reports_xmit_active) { - CPRINTS("Overflow! h:%d a:%d t:%d (%d)", - state->reports_head, state->reports_xmit_active, - state->reports_tail, - USB_POWER_MAX_CACHED(state->ina_count)); - return USB_POWER_ERROR_OVERFLOW; - } - - r->status = USB_POWER_SUCCESS; - r->size = state->ina_count; - if (config->state->wall_offset) - time = time + config->state->wall_offset; - else - time -= config->state->base_time; - r->timestamp = time; - - for (i = 0; i < state->ina_count; i++) { - int regval; - struct usb_power_ina_cfg *ina = inas + i; - - /* Read INA231. - * ina2xx_read(ina->port, ina->addr, INA231_REG_PWR); - * Readagain cached this address so we'll save an I2C - * transaction. - */ - if (ina->shared) - regval = ina2xx_read(ina->port, ina->addr_flags, - reg_type_mapping(ina->type)); - else - regval = ina2xx_readagain(ina->port, - ina->addr_flags); - r->power[i] = regval; -#ifdef USB_POWER_VERBOSE - { - int current; - int power; - int voltage; - int bvoltage; - - voltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_RSHV); - bvoltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV); - current = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CURR); - power = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_PWR); - { - int uV = ((int)voltage * 25) / 10; - int mV = ((int)bvoltage * 125) / 100; - int uA = (uV * 1000) / ina->rs; - int CuA = (((int)current * ina->scale) / 100); - int uW = (((int)power * ina->scale*25)/100); - - CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - uV/1000, ina->rs, uA/1000); - CPRINTS("[CAP] %duV %dmV %duA %dCuA " - "%duW v:%04x, b:%04x, p:%04x", - uV, mV, uA, CuA, uW, voltage, bvoltage, power); - } - } -#endif - } - - /* Mark this slot as used. */ - state->reports_head = (state->reports_head + 1) % - USB_POWER_MAX_CACHED(state->ina_count); - - return EC_SUCCESS; -} - -/* - * This function is called every [interval] uS, and reads the accumulated - * values of the INAs, and reschedules itself for the next interval. - * - * It will stop collecting frames if a ringbuffer overflow is - * detected, or a stop request is seen.. - */ -void usb_power_deferred_cap(struct usb_power_config const *config) -{ - int ret; - uint64_t timeout = get_time().val + config->state->integration_us; - uint64_t timein; - - /* Exit if we have stopped capturing in the meantime. */ - if (config->state->state != USB_POWER_STATE_CAPTURING) - return; - - /* Get samples for this timeslice */ - ret = usb_power_get_samples(config); - if (ret == USB_POWER_ERROR_OVERFLOW) { - CPRINTS("[CAP] usb_power_deferred_cap: OVERFLOW"); - return; - } - - /* Calculate time remaining until next slice. */ - timein = get_time().val; - if (timeout > timein) - timeout = timeout - timein; - else - timeout = 0; - - /* Double check if we are still capturing. */ - if (config->state->state == USB_POWER_STATE_CAPTURING) - hook_call_deferred(config->deferred_cap, timeout); -} - diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h deleted file mode 100644 index 68b7f75ca2..0000000000 --- a/chip/stm32/usb_power.h +++ /dev/null @@ -1,383 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_USB_POWER_H -#define __CROS_EC_USB_POWER_H - -/* Power monitoring USB interface for Chrome EC */ - -#include "compile_time_macros.h" -#include "hooks.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* - * Command: - * - * Commands are a 16 bit value, with optional command dependent data. - * +--------------+-----------------------------------+ - * | command : 2B | | - * +--------------+-----------------------------------+ - * - * Responses are an 8 bit status value, with optional data. - * +----------+-----------------------------------+ - * | res : 1B | | - * +----------+-----------------------------------+ - * - * reset: 0x0000 - * +--------+ - * | 0x0000 | - * +--------+ - * - * stop: 0x0001 - * +--------+ - * | 0x0001 | - * +--------+ - * - * addina: 0x0002 - * +--------+--------------------------+-------------+--------------+-----------+--------+ - * | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs | - * +--------+--------------------------+-------------+--------------+-----------+--------+ - * - * start: 0x0003 - * +--------+----------------------+ - * | 0x0003 | 4B: integration time | - * +--------+----------------------+ - * - * start response: - * +-------------+-----------------------------+ - * | status : 1B | Actual integration time: 4B | - * +-------------+-----------------------------+ - * - * next: 0x0004 - * +--------+ - * | 0x0004 | - * +--------+ - * - * next response: - * +-------------+----------+----------------+----------------------------+ - * | status : 1B | size: 1B | timestamp : 8B | payload : may span packets | - * +-------------+----------+----------------+----------------------------+ - * - * settime: 0x0005 - * +--------+---------------------+ - * | 0x0005 | 8B: Wall clock time | - * +--------+---------------------+ - * - * - * Status: 1 byte status - * - * 0x00: Success - * 0x01: I2C Error - * 0x02: Overflow - * This can happen if data acquisition is faster than USB reads. - * 0x03: No configuration set. - * 0x04: No active capture. - * 0x05: Timeout. - * 0x06: Busy, outgoing queue is empty. - * 0x07: Size, command length is incorrect for command type.. - * 0x08: More INAs specified than board limit. - * 0x09: Invalid input, eg. invalid INA type. - * 0x80: Unknown error - * - * size: 1 byte incoming INA reads count - * - * timestamp: 4 byte timestamp associated with these samples - * - */ - -/* 8b status field. */ -enum usb_power_error { - USB_POWER_SUCCESS = 0x00, - USB_POWER_ERROR_I2C = 0x01, - USB_POWER_ERROR_OVERFLOW = 0x02, - USB_POWER_ERROR_NOT_SETUP = 0x03, - USB_POWER_ERROR_NOT_CAPTURING = 0x04, - USB_POWER_ERROR_TIMEOUT = 0x05, - USB_POWER_ERROR_BUSY = 0x06, - USB_POWER_ERROR_READ_SIZE = 0x07, - USB_POWER_ERROR_FULL = 0x08, - USB_POWER_ERROR_INVAL = 0x09, - USB_POWER_ERROR_UNKNOWN = 0x80, -}; - -/* 16b command field. */ -enum usb_power_command { - USB_POWER_CMD_RESET = 0x0000, - USB_POWER_CMD_STOP = 0x0001, - USB_POWER_CMD_ADDINA = 0x0002, - USB_POWER_CMD_START = 0x0003, - USB_POWER_CMD_NEXT = 0x0004, - USB_POWER_CMD_SETTIME = 0x0005, -}; - -/* Addina "INA Type" field. */ -enum usb_power_ina_type { - USBP_INA231_POWER = 0x01, - USBP_INA231_BUSV = 0x02, - USBP_INA231_CURRENT = 0x03, - USBP_INA231_SHUNTV = 0x04, -}; - -/* Internal state machine values */ -enum usb_power_states { - USB_POWER_STATE_OFF = 0, - USB_POWER_STATE_SETUP, - USB_POWER_STATE_CAPTURING, -}; - -#define USB_POWER_MAX_READ_COUNT 64 -#define USB_POWER_MIN_CACHED 10 - -struct usb_power_ina_cfg { - /* - * Relevant config for INA usage. - */ - /* i2c bus. TODO(nsanders): specify what kind of index. */ - int port; - /* 7-bit i2c addr */ - uint16_t addr_flags; - - /* Base voltage. mV */ - int mv; - - /* Shunt resistor. mOhm */ - int rs; - /* uA per div as reported from INA */ - int scale; - - /* Is this power, shunt voltage, bus voltage, or current? */ - int type; - /* Is this INA returning the one value only and can use readagain? */ - int shared; -}; - - -struct __attribute__ ((__packed__)) usb_power_report { - uint8_t status; - uint8_t size; - uint64_t timestamp; - uint16_t power[USB_POWER_MAX_READ_COUNT]; -}; - -/* Must be 4 byte aligned */ -#define USB_POWER_RECORD_SIZE(ina_count) \ - ((((sizeof(struct usb_power_report) \ - - (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) \ - + (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4) - -#define USB_POWER_DATA_SIZE \ - (sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1)) -#define USB_POWER_MAX_CACHED(ina_count) \ - (USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count)) - - -struct usb_power_state { - /* - * The power data acquisition must be setup, then started, in order to - * return data. - * States are OFF, SETUP, and CAPTURING. - */ - int state; - - struct usb_power_ina_cfg ina_cfg[USB_POWER_MAX_READ_COUNT]; - int ina_count; - int integration_us; - /* Start of sampling. */ - uint64_t base_time; - /* Offset between microcontroller timestamp and host wall clock. */ - uint64_t wall_offset; - - /* Cached power reports for sending on USB. */ - /* Actual backing data for variable sized record queue. */ - uint8_t reports_data_area[USB_POWER_DATA_SIZE]; - /* Size of power report struct for this config. */ - int stride_bytes; - /* Max power records storeable in this config */ - int max_cached; - struct usb_power_report *reports; - - /* Head and tail pointers for output ringbuffer */ - /* Head adds newly probed power data. */ - int reports_head; - /* Tail contains oldest records not yet sent to USB */ - int reports_tail; - /* Xmit_active -> tail is active usb DMA */ - int reports_xmit_active; - - /* Pointers to RAM. */ - uint8_t rx_buf[USB_MAX_PACKET_SIZE]; - uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4]; -}; - - -/* - * Compile time Per-USB gpio configuration stored in flash. Instances of this - * structure are provided by the user of the USB gpio. This structure binds - * together all information required to operate a USB gpio. - */ -struct usb_power_config { - /* In RAM state of the USB power interface. */ - struct usb_power_state *state; - - /* USB endpoint state.*/ - struct dwc_usb_ep *ep; - - /* Interface and endpoint indicies. */ - int interface; - int endpoint; - - /* Deferred function to call to handle power request. */ - const struct deferred_data *deferred; - const struct deferred_data *deferred_cap; -}; - -struct __attribute__ ((__packed__)) usb_power_command_start { - uint16_t command; - uint32_t integration_us; -}; - -struct __attribute__ ((__packed__)) usb_power_command_addina { - uint16_t command; - uint8_t port; - uint8_t type; - uint8_t addr_flags; - uint8_t extra; - uint32_t rs; -}; - -struct __attribute__ ((__packed__)) usb_power_command_settime { - uint16_t command; - uint64_t time; -}; - -union usb_power_command_data { - uint16_t command; - struct usb_power_command_start start; - struct usb_power_command_addina addina; - struct usb_power_command_settime settime; -}; - - -/* - * Convenience macro for defining a USB INA Power driver. - * - * NAME is used to construct the names of the trampoline functions and the - * usb_power_config struct, the latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * driver. - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - */ -#define USB_POWER_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT) \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ - static void CONCAT2(NAME, _deferred_cap_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_)); \ - struct usb_power_state CONCAT2(NAME, _state_) = { \ - .state = USB_POWER_STATE_OFF, \ - .ina_count = 0, \ - .integration_us = 0, \ - .reports_head = 0, \ - .reports_tail = 0, \ - .wall_offset = 0, \ - }; \ - static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_data = 0, \ - .out_databuffer = 0, \ - .out_databuffer_max = 0, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = 0, \ - .in_databuffer_max = 0, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - struct usb_power_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .ep = &CONCAT2(NAME, _ep_ctl), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred_cap = &CONCAT2(NAME, _deferred_cap__data), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 1, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_epN_tx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_epN_rx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_power_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { usb_power_deferred_tx(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { usb_power_deferred_rx(&NAME); } \ - static void CONCAT2(NAME, _deferred_cap_)(void) \ - { usb_power_deferred_cap(&NAME); } - - -/* - * Handle power request in a deferred callback. - */ -void usb_power_deferred_rx(struct usb_power_config const *config); -void usb_power_deferred_tx(struct usb_power_config const *config); -void usb_power_deferred_cap(struct usb_power_config const *config); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB GPIO driver. - */ -void usb_power_tx(struct usb_power_config const *config); -void usb_power_rx(struct usb_power_config const *config); -void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt); - - - - -#endif /* __CROS_EC_USB_DWC_POWER_H */ - diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c deleted file mode 100644 index 54caae015e..0000000000 --- a/chip/stm32/usb_spi.c +++ /dev/null @@ -1,627 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "common.h" -#include "link_defs.h" -#include "registers.h" -#include "spi.h" -#include "usb_descriptor.h" -#include "usb_hw.h" -#include "usb_spi.h" -#include "util.h" - -/* Forward declare platform specific functions. */ -static bool usb_spi_received_packet(struct usb_spi_config const *config); -static bool usb_spi_transmitted_packet(struct usb_spi_config const *config); -static void usb_spi_read_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet); -static void usb_spi_write_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet); - -/* - * Map EC error codes to USB_SPI error codes. - * - * @param error EC error code - * - * @returns USB SPI error code based on the mapping. - */ -static int16_t usb_spi_map_error(int error) -{ - switch (error) { - case EC_SUCCESS: return USB_SPI_SUCCESS; - case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT; - case EC_ERROR_BUSY: return USB_SPI_BUSY; - default: return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff); - } -} - -/* - * Read data into the receive buffer. - * - * @param dst Destination receive context we are writing data to. - * @param src Source packet context we are reading data from. - * - * @returns USB_SPI_RX_DATA_OVERFLOW if the source packet is too large - */ -static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, - const struct usb_spi_packet_ctx *src) -{ - size_t max_read_length = dst->transfer_size - dst->transfer_index; - size_t bytes_in_buffer = src->packet_size - src->header_size; - const uint8_t *packet_buffer = src->bytes + src->header_size; - - if (bytes_in_buffer > max_read_length) { - /* - * An error occurred, we should not receive more data than - * the buffer can support. - */ - return USB_SPI_RX_DATA_OVERFLOW; - } - memcpy(dst->buffer + dst->transfer_index, packet_buffer, - bytes_in_buffer); - - dst->transfer_index += bytes_in_buffer; - return USB_SPI_SUCCESS; -} - -/* - * Fill the USB packet with data from the transmit buffer. - * - * @param dst Destination packet context we are writing data to. - * @param src Source transmit context we are reading data from. - */ -static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst, - struct usb_spi_transfer_ctx *src) -{ - size_t transfer_size = src->transfer_size - src->transfer_index; - size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size; - uint8_t *packet_buffer = dst->bytes + dst->header_size; - - if (transfer_size > max_buffer_size) - transfer_size = max_buffer_size; - - memcpy(packet_buffer, src->buffer + src->transfer_index, transfer_size); - - dst->packet_size = dst->header_size + transfer_size; - src->transfer_index += transfer_size; -} - -/* - * Setup the USB SPI state to start a new SPI transfer. - * - * @param config USB SPI config - * @param write_count Number of bytes to write in the SPI transfer - * @param read_count Number of bytes to read in the SPI transfer - */ -static void usb_spi_setup_transfer(struct usb_spi_config const *config, - size_t write_count, size_t read_count) -{ - /* Reset any status code. */ - config->state->status_code = USB_SPI_SUCCESS; - - /* Reset the write and read counts. */ - config->state->spi_write_ctx.transfer_size = write_count; - config->state->spi_write_ctx.transfer_index = 0; - config->state->spi_read_ctx.transfer_size = read_count; - config->state->spi_read_ctx.transfer_index = 0; -} - -/* - * Handle USB events that will reset the USB SPI state. - * - * @param config USB SPI config - */ -static void usb_spi_reset_interface(struct usb_spi_config const *config) -{ - /* Setup a 0 byte transfer to clear the contexts. */ - usb_spi_setup_transfer(config, 0, 0); -} - -/* - * Returns if the response transfer is in progress. - * - * @param config USB SPI config - * - * @returns True if a response transfer is in progress. - */ -static bool usb_spi_response_in_progress(struct usb_spi_config const *config) -{ - if ((config->state->mode == USB_SPI_MODE_START_RESPONSE) || - (config->state->mode == USB_SPI_MODE_CONTINUE_RESPONSE)) { - return true; - } - return false; -} - -/* - * Prep the state to construct a new response. This sets the transfer - * contexts, the mode, and status code. If a non-zero status code is - * returned, then no payload will be transmitted. - * - * @param config USB SPI config - * @param status_code status code to set for the response. - */ -static void setup_transfer_response(struct usb_spi_config const *config, - uint16_t status_code) -{ - config->state->status_code = status_code; - config->state->spi_read_ctx.transfer_index = 0; - config->state->mode = USB_SPI_MODE_START_RESPONSE; - - /* If an error occurred, transmit an empty start packet. */ - if (status_code != USB_SPI_SUCCESS) - config->state->spi_read_ctx.transfer_size = 0; -} - -/* - * Constructs the response packet containing the SPI configuration. - * - * @param config USB SPI config - * @param packet Packet buffer we will be transmitting. - */ -static void create_spi_config_response(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) -{ - /* Construct the response packet. */ - packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG; - packet->rsp_config.max_write_count = USB_SPI_MAX_WRITE_COUNT; - packet->rsp_config.max_read_count = USB_SPI_MAX_READ_COUNT; - /* Set the feature flags. */ - packet->rsp_config.feature_bitmap = 0; -#ifndef CONFIG_SPI_HALFDUPLEX - packet->rsp_config.feature_bitmap |= - USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED; -#endif - packet->packet_size = - sizeof(struct usb_spi_response_configuration_v2); -} - -/* - * If we have a transfer response in progress, this will construct the - * next entry. If no transfer is in progress or if we are unable to - * create the next packet, it will not modify tx_packet. - * - * @param config USB SPI config - * @param packet Packet buffer we will be transmitting. - */ -static void usb_spi_create_spi_transfer_response( - struct usb_spi_config const *config, - struct usb_spi_packet_ctx *transmit_packet) -{ - - if (!usb_spi_response_in_progress(config)) - return; - - if (config->state->spi_read_ctx.transfer_index == 0) { - - /* Transmit the first packet with the status code. */ - transmit_packet->header_size = - offsetof(struct usb_spi_response_v2, data); - transmit_packet->rsp_start.packet_id = - USB_SPI_PKT_ID_RSP_TRANSFER_START; - transmit_packet->rsp_start.status_code = - config->state->status_code; - - usb_spi_fill_usb_packet(transmit_packet, - &config->state->spi_read_ctx); - } else if (config->state->spi_read_ctx.transfer_index < - config->state->spi_read_ctx.transfer_size) { - - /* Transmit the continue packets. */ - transmit_packet->header_size = - offsetof(struct usb_spi_continue_v2, data); - transmit_packet->rsp_continue.packet_id = - USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE; - transmit_packet->rsp_continue.data_index = - config->state->spi_read_ctx.transfer_index; - - usb_spi_fill_usb_packet(transmit_packet, - &config->state->spi_read_ctx); - } - if (config->state->spi_read_ctx.transfer_index < - config->state->spi_read_ctx.transfer_size) { - config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE; - } else { - config->state->mode = USB_SPI_MODE_IDLE; - } -} - -/* - * Process the rx packet. - * - * @param config USB SPI config - * @param packet Received packet to process. - */ -static void usb_spi_process_rx_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) -{ - if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) { - /* No valid packet exists smaller than the packet id. */ - setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET); - return; - } - /* Reset the mode until we've processed the packet. */ - config->state->mode = USB_SPI_MODE_IDLE; - - switch (packet->packet_id) { - case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: - { - /* The host requires the SPI configuration. */ - config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION; - break; - } - case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: - { - /* - * The host has requested the device restart the last response. - * This is used to recover from lost USB packets without - * duplicating SPI transfers. - */ - setup_transfer_response(config, config->state->status_code); - break; - } - case USB_SPI_PKT_ID_CMD_TRANSFER_START: - { - /* The host started a new USB SPI transfer */ - size_t write_count = packet->cmd_start.write_count; - size_t read_count = packet->cmd_start.read_count; - - if (!config->state->enabled) { - setup_transfer_response(config, USB_SPI_DISABLED); - } else if (write_count > USB_SPI_MAX_WRITE_COUNT) { - setup_transfer_response(config, - USB_SPI_WRITE_COUNT_INVALID); - } else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) { -#ifndef CONFIG_SPI_HALFDUPLEX - /* Full duplex mode is not supported on this device. */ - setup_transfer_response(config, - USB_SPI_UNSUPPORTED_FULL_DUPLEX); -#endif - } else if (read_count > USB_SPI_MAX_READ_COUNT && - read_count != USB_SPI_FULL_DUPLEX_ENABLED) { - setup_transfer_response(config, - USB_SPI_READ_COUNT_INVALID); - } else { - usb_spi_setup_transfer(config, write_count, read_count); - packet->header_size = - offsetof(struct usb_spi_command_v2, data); - config->state->status_code = usb_spi_read_usb_packet( - &config->state->spi_write_ctx, packet); - } - - /* Send responses if we encountered an error. */ - if (config->state->status_code != USB_SPI_SUCCESS) { - setup_transfer_response(config, - config->state->status_code); - break; - } - - /* Start the SPI transfer when we've read all data. */ - if (config->state->spi_write_ctx.transfer_index == - config->state->spi_write_ctx.transfer_size) { - config->state->mode = USB_SPI_MODE_START_SPI; - } - - break; - } - case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: - { - /* - * The host has sent a continue packet for the SPI transfer - * which contains additional data payload. - */ - packet->header_size = - offsetof(struct usb_spi_continue_v2, data); - if (config->state->status_code == USB_SPI_SUCCESS) { - config->state->status_code = usb_spi_read_usb_packet( - &config->state->spi_write_ctx, packet); - } - - /* Send responses if we encountered an error. */ - if (config->state->status_code != USB_SPI_SUCCESS) { - setup_transfer_response(config, - config->state->status_code); - break; - } - - /* Start the SPI transfer when we've read all data. */ - if (config->state->spi_write_ctx.transfer_index == - config->state->spi_write_ctx.transfer_size) { - config->state->mode = USB_SPI_MODE_START_SPI; - } - - break; - } - default: - { - /* An unknown USB packet was delivered. */ - setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET); - break; - } - } -} - -/* Deferred function to handle state changes, process USB SPI packets, - * and construct responses. - * - * @param config USB SPI config - */ -void usb_spi_deferred(struct usb_spi_config const *config) -{ - int enabled; - struct usb_spi_packet_ctx *receive_packet = - &config->state->receive_packet; - struct usb_spi_packet_ctx *transmit_packet = - &config->state->transmit_packet; - transmit_packet->packet_size = 0; - - if (config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE) - enabled = config->state->enabled_device; - else - enabled = config->state->enabled_device && - config->state->enabled_host; - - /* - * If our overall enabled state has changed we call the board specific - * enable or disable routines and save our new state. - */ - if (enabled != config->state->enabled) { - if (enabled) usb_spi_board_enable(config); - else usb_spi_board_disable(config); - - config->state->enabled = enabled; - } - - /* Read any packets from the endpoint. */ - - usb_spi_read_packet(config, receive_packet); - if (receive_packet->packet_size) { - usb_spi_process_rx_packet(config, receive_packet); - } - - /* Need to send the USB SPI configuration */ - if (config->state->mode == USB_SPI_MODE_SEND_CONFIGURATION) { - create_spi_config_response(config, transmit_packet); - usb_spi_write_packet(config, transmit_packet); - config->state->mode = USB_SPI_MODE_IDLE; - return; - } - - /* Start a new SPI transfer. */ - if (config->state->mode == USB_SPI_MODE_START_SPI) { - uint16_t status_code; - int read_count = config->state->spi_read_ctx.transfer_size; -#ifndef CONFIG_SPI_HALFDUPLEX - /* - * Handle the full duplex mode on supported platforms. - * The read count is equal to the write count. - */ - if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) { - config->state->spi_read_ctx.transfer_size = - config->state->spi_write_ctx.transfer_size; - read_count = SPI_READBACK_ALL; - } -#endif - status_code = spi_transaction(SPI_FLASH_DEVICE, - config->state->spi_write_ctx.buffer, - config->state->spi_write_ctx.transfer_size, - config->state->spi_read_ctx.buffer, - read_count); - - /* Cast the EC status code to USB SPI and start the response. */ - status_code = usb_spi_map_error(status_code); - setup_transfer_response(config, status_code); - } - - if (usb_spi_response_in_progress(config) && - usb_spi_transmitted_packet(config)) { - usb_spi_create_spi_transfer_response(config, transmit_packet); - usb_spi_write_packet(config, transmit_packet); - } -} - -/* - * Sets which SPI modes will be enabled - * - * @param config USB SPI config - * @param enabled usb_spi_request indicating which SPI mode is enabled. - */ -void usb_spi_enable(struct usb_spi_config const *config, int enabled) -{ - config->state->enabled_device = enabled; - - hook_call_deferred(config->deferred, 0); -} - -/* - * STM32 Platform: Receive the data from the endpoint into the packet and - * mark the endpoint as ready to accept more data. - * - * @param config USB SPI config - * @param packet Destination packet used to store the endpoint data. - */ -static void usb_spi_read_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) -{ - size_t packet_size; - - if (!usb_spi_received_packet(config)) { - /* No data is present on the endpoint. */ - packet->packet_size = 0; - return; - } - - /* Copy bytes from endpoint memory. */ - packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK; - memcpy_from_usbram(packet->bytes, - (void *)usb_sram_addr(config->ep_rx_ram), packet_size); - packet->packet_size = packet_size; - /* Set endpoint as valid for accepting new packet. */ - STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); -} - -/* - * STM32 Platform: Transmit data from the packet to the endpoint buffer. - * If a packet is written, the endpoint will be marked valid for transmitting. - * - * @param config USB SPI config - * @param packet Source packet we will write to the endpoint data. - */ -static void usb_spi_write_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) -{ - if (packet->packet_size == 0) - return; - - /* Copy bytes to endpoint memory. */ - memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram), - packet->bytes, packet->packet_size); - btable_ep[config->endpoint].tx_count = packet->packet_size; - - /* Mark the packet as having no data. */ - packet->packet_size = 0; - - /* Set endpoint as valid for transmitting new packet. */ - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_VALID, 0); -} - -/* - * STM32 Platform: Returns the RX endpoint status - * - * @param config USB SPI config - * - * @returns Returns true when the RX endpoint has a packet. - */ -static bool usb_spi_received_packet(struct usb_spi_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_RX_MASK) != EP_RX_VALID; -} - -/* STM32 Platform: Returns the TX endpoint status - * - * @param config USB SPI config - * - * @returns Returns true when the TX endpoint transmitted - * the packet written. - */ -static bool usb_spi_transmitted_packet(struct usb_spi_config const *config) -{ - return (STM32_USB_EP(config->endpoint) & EP_TX_MASK) != EP_TX_VALID; -} - -/* STM32 Platform: Handle interrupt for USB data received. - * - * @param config USB SPI config - */ -void usb_spi_rx(struct usb_spi_config const *config) -{ - /* - * We need to set both the TX and RX endpoints to NAK to prevent - * transfers. The protocol requires responses to follow a command, but - * the USB host will request the next packet from the TX endpoint - * before the USB SPI has updated the memory in the buffer. By setting - * it to NAK in the ISR, it will not perform a transfer until the - * next packet is ready. - * - * This has a side effect of disabling the endpoint interrupts until - * they are set to valid or a USB reset events occurs. - */ - STM32_TOGGLE_EP(config->endpoint, EP_TX_RX_MASK, EP_TX_RX_NAK, 0); - - hook_call_deferred(config->deferred, 0); -} - -/* - * STM32 Platform: Handle interrupt for USB data transmitted. - * - * @param config USB SPI config - */ -void usb_spi_tx(struct usb_spi_config const *config) -{ - STM32_TOGGLE_EP(config->endpoint, EP_TX_MASK, EP_TX_NAK, 0); - - hook_call_deferred(config->deferred, 0); -} - -/* - * STM32 Platform: Handle interrupt for USB events - * - * @param config USB SPI config - * @param evt USB event - */ -void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt) -{ - int endpoint; - - if (evt != USB_EVENT_RESET) - return; - - endpoint = config->endpoint; - - usb_spi_reset_interface(config); - - btable_ep[endpoint].tx_addr = usb_sram_addr(config->ep_tx_ram); - btable_ep[endpoint].tx_count = 0; - - btable_ep[endpoint].rx_addr = usb_sram_addr(config->ep_rx_ram); - btable_ep[endpoint].rx_count = - 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - - STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (3 << 12)); /* RX Valid */ -} - -/* - * STM32 Platform: Handle control transfers. - * - * @param config USB SPI config - * @param rx_buf Contains setup packet - * @param tx_buf unused - */ -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, - usb_uint *tx_buf) -{ - struct usb_setup_packet setup; - - usb_read_setup_packet(rx_buf, &setup); - - if (setup.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) - return 1; - - if (setup.wValue != 0 || - setup.wIndex != config->interface || - setup.wLength != 0) - return 1; - - switch (setup.bRequest) { - case USB_SPI_REQ_ENABLE: - config->state->enabled_host = 1; - break; - - case USB_SPI_REQ_DISABLE: - config->state->enabled_host = 0; - break; - - default: return 1; - } - - /* - * Our state has changed, call the deferred function to handle the - * state change. - */ - if (!(config->flags & USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE)) - hook_call_deferred(config->deferred, 0); - - usb_spi_reset_interface(config); - - btable_ep[0].tx_count = 0; - STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, EP_STATUS_OUT); - return 0; -} diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h deleted file mode 100644 index 591975234d..0000000000 --- a/chip/stm32/usb_spi.h +++ /dev/null @@ -1,594 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_USB_SPI_H -#define __CROS_EC_USB_SPI_H - -/* STM32 USB SPI driver for Chrome EC */ - -#include "compile_time_macros.h" -#include "hooks.h" -#include "usb_descriptor.h" -#include "usb_hw.h" - -/* - * This SPI flash programming interface is designed to talk to a Chromium OS - * device over a Raiden USB connection. - * - * USB SPI Version 2: - * - * USB SPI version 2 adds support for larger SPI transfers and reduces the - * number of USB packets transferred. This improves performance when - * writing or reading large chunks of memory from a device. A packet ID - * field is used to distinguish the different packet types. Additional - * packets have been included to query the device for its configuration - * allowing the interface to be used on platforms with different SPI - * limitations. It includes validation and a packet to recover from the - * situations where USB packets are lost. - * - * The USB SPI hosts which support packet version 2 are backwards compatible - * and use the bInterfaceProtocol field to identify which type of target - * they are connected to. - * - * - * Example: USB SPI request with 128 byte write and 0 byte read. - * - * Packet #1 Host to Device: - * packet id = USB_SPI_PKT_ID_CMD_TRANSFER_START - * write count = 128 - * read count = 0 - * payload = First 58 bytes from the write buffer, - * starting at byte 0 in the buffer - * packet size = 64 bytes - * - * Packet #2 Host to Device: - * packet id = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE - * data index = 58 - * payload = Next 60 bytes from the write buffer, - * starting at byte 58 in the buffer - * packet size = 64 bytes - * - * Packet #3 Host to Device: - * packet id = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE - * data index = 118 - * payload = Next 10 bytes from the write buffer, - * starting at byte 118 in the buffer - * packet size = 14 bytes - * - * Packet #4 Device to Host: - * packet id = USB_SPI_PKT_ID_RSP_TRANSFER_START - * status code = status code from device - * payload = 0 bytes - * packet size = 4 bytes - * - * Example: USB SPI request with 2 byte write and 100 byte read. - * - * Packet #1 Host to Device: - * packet id = USB_SPI_PKT_ID_CMD_TRANSFER_START - * write count = 2 - * read count = 100 - * payload = The 2 byte write buffer - * packet size = 8 bytes - * - * Packet #2 Device to Host: - * packet id = USB_SPI_PKT_ID_RSP_TRANSFER_START - * status code = status code from device - * payload = First 60 bytes from the read buffer, - * starting at byte 0 in the buffer - * packet size = 64 bytes - * - * Packet #3 Device to Host: - * packet id = USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE - * data index = 60 - * payload = Next 40 bytes from the read buffer, - * starting at byte 60 in the buffer - * packet size = 44 bytes - * - * - * Message Packets: - * - * Command Start Packet (Host to Device): - * - * Start of the USB SPI command, contains the number of bytes to write - * and read on SPI and up to the first 58 bytes of write payload. - * Longer writes will use the continue packets with packet id - * USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE to transmit the remaining data. - * - * +----------------+------------------+-----------------+---------------+ - * | packet id : 2B | write count : 2B | read count : 2B | w.p. : <= 58B | - * +----------------+------------------+-----------------+---------------+ - * - * packet id: 2 byte enum defined by packet_id_type - * Valid values packet id = USB_SPI_PKT_ID_CMD_TRANSFER_START - * - * write count: 2 byte, zero based count of bytes to write - * - * read count: 2 byte, zero based count of bytes to read - * UINT16_MAX indicates full duplex mode with a read count - * equal to the write count. - * - * write payload: Up to 58 bytes of data to write to SPI, the total - * length of all TX packets must match write count. - * Due to data alignment constraints, this must be an - * even number of bytes unless this is the final packet. - * - * - * Response Start Packet (Device to Host): - * - * Start of the USB SPI response, contains the status code and up to - * the first 60 bytes of read payload. Longer reads will use the - * continue packets with packet id USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE - * to transmit the remaining data. - * - * +----------------+------------------+-----------------------+ - * | packet id : 2B | status code : 2B | read payload : <= 60B | - * +----------------+------------------+-----------------------+ - * - * packet id: 2 byte enum defined by packet_id_type - * Valid values packet id = USB_SPI_PKT_ID_RSP_TRANSFER_START - * - * status code: 2 byte status code - * 0x0000: Success - * 0x0001: SPI timeout - * 0x0002: Busy, try again - * This can happen if someone else has acquired the shared memory - * buffer that the SPI driver uses as /dev/null - * 0x0003: Write count invalid. The byte limit is platform specific - * and is set during the configure USB SPI response. - * 0x0004: Read count invalid. The byte limit is platform specific - * and is set during the configure USB SPI response. - * 0x0005: The SPI bridge is disabled. - * 0x0006: The RX continue packet's data index is invalid. This - * can indicate a USB transfer failure to the device. - * 0x0007: The RX endpoint has received more data than write count. - * This can indicate a USB transfer failure to the device. - * 0x0008: An unexpected packet arrived that the device could not - * process. - * 0x0009: The device does not support full duplex mode. - * 0x8000: Unknown error mask - * The bottom 15 bits will contain the bottom 15 bits from the EC - * error code. - * - * read payload: Up to 60 bytes of data read from SPI, the total - * length of all RX packets must match read count - * unless an error status was returned. Due to data - * alignment constraints, this must be a even number - * of bytes unless this is the final packet. - * - * - * Continue Packet (Bidirectional): - * - * Continuation packet for the writes and read buffers. Both packets - * follow the same format, a data index counts the number of bytes - * previously transferred in the USB SPI transfer and a payload of bytes. - * - * +----------------+-----------------+-------------------------------+ - * | packet id : 2B | data index : 2B | write / read payload : <= 60B | - * +----------------+-----------------+-------------------------------+ - * - * packet id: 2 byte enum defined by packet_id_type - * The packet id has 2 values depending on direction: - * packet id = USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE - * indicates the packet is being transmitted from the host - * to the device and contains SPI write payload. - * packet id = USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE - * indicates the packet is being transmitted from the device - * to the host and contains SPI read payload. - * - * data index: The data index indicates the number of bytes in the - * read or write buffers that have already been transmitted. - * It is used to validate that no packets have been dropped - * and that the prior packets have been correctly decoded. - * This value corresponds to the offset bytes in the buffer - * to start copying the payload into. - * - * read and write payload: - * Contains up to 60 bytes of payload data to transfer to - * the SPI write buffer or from the SPI read buffer. - * - * - * Command Get Configuration Packet (Host to Device): - * - * Query the device to request it's USB SPI configuration indicating - * the number of bytes it can write and read. - * - * +----------------+ - * | packet id : 2B | - * +----------------+ - * - * packet id: 2 byte enum USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG - * - * Response Configuration Packet (Device to Host): - * - * Response packet form the device to report the maximum write and - * read size supported by the device. - * - * +----------------+----------------+---------------+----------------+ - * | packet id : 2B | max write : 2B | max read : 2B | feature bitmap | - * +----------------+----------------+---------------+----------------+ - * - * packet id: 2 byte enum USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG - * - * max write count: 2 byte count of the maximum number of bytes - * the device can write to SPI in one transaction. - * - * max read count: 2 byte count of the maximum number of bytes - * the device can read from SPI in one transaction. - * - * feature bitmap: Bitmap of supported features. - * BIT(0): Full duplex SPI mode is supported - * BIT(1:15): Reserved for future use - * - * Command Restart Response Packet (Host to Device): - * - * Command to restart the response transfer from the device. This enables - * the host to recover from a lost packet when reading the response - * without restarting the SPI transfer. - * - * +----------------+ - * | packet id : 2B | - * +----------------+ - * - * packet id: 2 byte enum USB_SPI_PKT_ID_CMD_RESTART_RESPONSE - * - * USB Error Codes: - * - * send_command return codes have the following format: - * - * 0x00000: Status code success. - * 0x00001-0x0FFFF: Error code returned by the USB SPI device. - * 0x10001-0x1FFFF: USB SPI Host error codes - * 0x20001-0x20063 Lower bits store the positive value representation - * of the libusb_error enum. See the libusb documentation: - * http://libusb.sourceforge.net/api-1.0/group__misc.html - */ - -#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX) - -#define USB_SPI_PAYLOAD_SIZE_V2_START (58) - -#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60) - -#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60) - -#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60) - -#define USB_SPI_MIN_PACKET_SIZE (2) - -enum packet_id_type { - /* Request USB SPI configuration data from device. */ - USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0, - /* USB SPI configuration data from device. */ - USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1, - /* - * Start a USB SPI transfer specifying number of bytes to write, - * read and deliver first packet of data to write. - */ - USB_SPI_PKT_ID_CMD_TRANSFER_START = 2, - /* Additional packets containing write payload. */ - USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3, - /* - * Request the device restart the response enabling us to recover - * from packet loss without another SPI transfer. - */ - USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4, - /* - * First packet of USB SPI response with the status code - * and read payload if it was successful. - */ - USB_SPI_PKT_ID_RSP_TRANSFER_START = 5, - /* Additional packets containing read payload. */ - USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6, -}; - -enum feature_bitmap { - /* Indicates the platform supports full duplex mode. */ - USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED = BIT(0) -}; - -struct usb_spi_response_configuration_v2 { - uint16_t packet_id; - uint16_t max_write_count; - uint16_t max_read_count; - uint16_t feature_bitmap; -} __packed; - -struct usb_spi_command_v2 { - uint16_t packet_id; - uint16_t write_count; - /* UINT16_MAX Indicates readback all on halfduplex compliant devices. */ - uint16_t read_count; - uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_START]; -} __packed; - -struct usb_spi_response_v2 { - uint16_t packet_id; - uint16_t status_code; - uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_RESPONSE]; -} __packed; - -struct usb_spi_continue_v2 { - uint16_t packet_id; - uint16_t data_index; - uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_CONTINUE]; -} __packed; - -struct usb_spi_packet_ctx { - union { - uint8_t bytes[USB_MAX_PACKET_SIZE]; - uint16_t packet_id; - struct usb_spi_command_v2 cmd_start; - struct usb_spi_continue_v2 cmd_continue; - struct usb_spi_response_configuration_v2 rsp_config; - struct usb_spi_response_v2 rsp_start; - struct usb_spi_continue_v2 rsp_continue; - } __packed; - /* - * By storing the number of bytes in the header and knowing that the - * USB data packets are all 64B long, we are able to use the header - * size to store the offset of the buffer and it's size without - * duplicating variables that can go out of sync. - */ - size_t header_size; - /* Number of bytes in the packet. */ - size_t packet_size; -}; - -enum usb_spi_error { - USB_SPI_SUCCESS = 0x0000, - USB_SPI_TIMEOUT = 0x0001, - USB_SPI_BUSY = 0x0002, - USB_SPI_WRITE_COUNT_INVALID = 0x0003, - USB_SPI_READ_COUNT_INVALID = 0x0004, - USB_SPI_DISABLED = 0x0005, - /* The RX continue packet's data index is invalid. */ - USB_SPI_RX_BAD_DATA_INDEX = 0x0006, - /* The RX endpoint has received more data than write count. */ - USB_SPI_RX_DATA_OVERFLOW = 0x0007, - /* An unexpected packet arrived on the device. */ - USB_SPI_RX_UNEXPECTED_PACKET = 0x0008, - /* The device does not support full duplex mode. */ - USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009, - USB_SPI_UNKNOWN_ERROR = 0x8000, -}; - -enum usb_spi_request { - USB_SPI_REQ_ENABLE = 0x0000, - USB_SPI_REQ_DISABLE = 0x0001, -}; - -/* - * To optimize for speed, we want to fill whole packets for each transfer - * This is done by setting the read and write counts to the payload sizes - * of the smaller start packet + N * continue packets. - * - * If a platform has a small maximum SPI transfer size, it can be optimized - * by setting these limits to the maximum transfer size. - */ -#define USB_SPI_BUFFER_SIZE (USB_SPI_PAYLOAD_SIZE_V2_START + \ - (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE)) -#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE -#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE - -struct usb_spi_transfer_ctx { - /* Address of transfer buffer. */ - uint8_t *buffer; - /* Number of bytes in the transfer. */ - size_t transfer_size; - /* Number of bytes transferred. */ - size_t transfer_index; -}; - -enum usb_spi_mode { - /* No tasks are required. */ - USB_SPI_MODE_IDLE = 0, - /* Indicates the device needs to send it's USB SPI configuration.*/ - USB_SPI_MODE_SEND_CONFIGURATION, - /* Indicates we device needs start the SPI transfer. */ - USB_SPI_MODE_START_SPI, - /* Indicates we should start a transfer response. */ - USB_SPI_MODE_START_RESPONSE, - /* Indicates we need to continue a transfer response. */ - USB_SPI_MODE_CONTINUE_RESPONSE, -}; - -struct usb_spi_state { - /* - * The SPI bridge must be enabled both locally and by the host to allow - * access to the SPI device. The enabled_host flag is set and cleared - * by sending USB_SPI_REQ_ENABLE and USB_SPI_REQ_DISABLE to the device - * control endpoint. The enabled_device flag is set by calling - * usb_spi_enable. - */ - int enabled_host; - int enabled_device; - - /* - * The current enabled state. This is only updated in the deferred - * callback. Whenever either of the host or device specific enable - * flags is changed the deferred callback is queued, and it will check - * their combined state against this flag. If the combined state is - * different, then one of usb_spi_board_enable or usb_spi_board_disable - * is called and this flag is updated. This ensures that the board - * specific state update routines are only called from the deferred - * callback. - */ - int enabled; - - /* Mark the current operating mode. */ - enum usb_spi_mode mode; - - /* - * Stores the status code response for the transfer, delivered in the - * header for the first response packet. Error code is cleared during - * first RX packet and set if a failure occurs. - */ - uint16_t status_code; - - /* Stores the content from the USB packets */ - struct usb_spi_packet_ctx receive_packet; - struct usb_spi_packet_ctx transmit_packet; - - /* - * Context structures representing the progress receiving the SPI - * write data and transmitting the SPI read data. - */ - struct usb_spi_transfer_ctx spi_write_ctx; - struct usb_spi_transfer_ctx spi_read_ctx; -}; - -/* - * Compile time Per-USB gpio configuration stored in flash. Instances of this - * structure are provided by the user of the USB gpio. This structure binds - * together all information required to operate a USB gpio. - */ -struct usb_spi_config { - /* In RAM state of the USB SPI bridge. */ - struct usb_spi_state *state; - - /* Interface and endpoint indices. */ - int interface; - int endpoint; - - /* Deferred function to call to handle SPI request. */ - const struct deferred_data *deferred; - - /* Pointers to USB endpoint buffers. */ - usb_uint *ep_rx_ram; - usb_uint *ep_tx_ram; - - /* Flags. See USB_SPI_CONFIG_FLAGS_* for definitions */ - uint32_t flags; -}; - -/* - * Use when you want the SPI subsystem to be enabled even when the USB SPI - * endpoint is not enabled by the host. This means that when this firmware - * enables SPI, then the HW SPI module is enabled (i.e. SPE bit is set) until - * this firmware disables the SPI module; it ignores the host's enables state. - */ -#define USB_SPI_CONFIG_FLAGS_IGNORE_HOST_SIDE_ENABLE BIT(0) - -/* - * Convenience macro for defining a USB SPI bridge driver. - * - * NAME is used to construct the names of the trampoline functions and the - * usb_spi_config struct, the latter is just called NAME. - * - * INTERFACE is the index of the USB interface to associate with this - * SPI driver. - * - * ENDPOINT is the index of the USB bulk endpoint used for receiving and - * transmitting bytes. - * - * FLAGS encodes different run-time control parameters. See - * USB_SPI_CONFIG_FLAGS_* for definitions. - */ -#define USB_SPI_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT, \ - FLAGS) \ - static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\ - static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - struct usb_spi_state CONCAT2(NAME, _state_) = { \ - .enabled_host = 0, \ - .enabled_device = 0, \ - .enabled = 0, \ - .spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ - .spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ - }; \ - struct usb_spi_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred = &CONCAT2(NAME, _deferred__data), \ - .ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \ - .ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \ - .flags = FLAGS, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_spi_tx (&NAME); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_spi_rx (&NAME); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_spi_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_spi_interface(&NAME, rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_spi_deferred(&NAME); } - -/* - * Handle SPI request in a deferred callback. - */ -void usb_spi_deferred(struct usb_spi_config const *config); - -/* - * Set the enable state for the USB-SPI bridge. - * - * The bridge must be enabled from both the host and device side - * before the SPI bus is usable. This allows the bridge to be - * available for host tools to use without forcing the device to - * disconnect or disable whatever else might be using the SPI bus. - */ -void usb_spi_enable(struct usb_spi_config const *config, int enabled); - -/* - * These functions are used by the trampoline functions defined above to - * connect USB endpoint events with the generic USB GPIO driver. - */ -void usb_spi_tx(struct usb_spi_config const *config); -void usb_spi_rx(struct usb_spi_config const *config); -void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt); -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, - usb_uint *tx_buf); - -/* - * These functions should be implemented by the board to provide any board - * specific operations required to enable or disable access to the SPI device. - */ -void usb_spi_board_enable(struct usb_spi_config const *config); -void usb_spi_board_disable(struct usb_spi_config const *config); - -#endif /* __CROS_EC_USB_SPI_H */ diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c deleted file mode 100644 index 40dfc72059..0000000000 --- a/chip/stm32/watchdog.c +++ /dev/null @@ -1,119 +0,0 @@ -/* Copyright 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Watchdog driver */ - -#include "common.h" -#include "gpio.h" -#include "hooks.h" -#include "hwtimer.h" -#include "registers.h" -#include "task.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * LSI oscillator frequency is typically 38 kHz, but it may be between 28-56 - * kHz and we don't calibrate it to know. Use 56 kHz so that we pick a counter - * value large enough that we reload before the worst-case watchdog delay - * (fastest LSI clock). - */ -#ifdef CHIP_FAMILY_STM32L4 -#define LSI_CLOCK 34000 -#else -#define LSI_CLOCK 56000 -#endif - -/* The timeout value is multiplied by 1000 to be converted into ms */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_CLOCK) - -/* - * Use largest prescaler divider = /256. This gives a worst-case watchdog - * clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) = - * 18.7 sec. - * - * For STM32L4, Max LSI is 34000. Watchdog clock is 34000 / 256 = 132Hz, - * Max timeout = 4095 / 132 = 31 sec. - */ -#define IWDG_PRESCALER 6 -#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER) - -void watchdog_reload(void) -{ - /* Reload the watchdog */ - STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; - -#ifdef CONFIG_WATCHDOG_HELP - hwtimer_reset_watchdog(); -#endif -} -DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); - -int watchdog_init(void) -{ -#ifdef CHIP_FAMILY_STM32L4 - timestamp_t tickstart, ticknow; - - /* Enable watchdog registers */ - STM32_IWDG_KR = STM32_IWDG_KR_START; -#endif - /* Unlock watchdog registers */ - STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK; - - /* Set the prescaler between the LSI clock and the watchdog counter */ - STM32_IWDG_PR = IWDG_PRESCALER & 7; - - /* Set the reload value of the watchdog counter */ - STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS * - (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); -#ifdef CHIP_FAMILY_STM32L4 - tickstart = get_time(); - /* Wait for SR */ - while (STM32_IWDG_SR != 0x00u) { - ticknow = get_time(); - if ((ticknow.val - tickstart.val) > - HAL_IWDG_DEFAULT_TIMEOUT * 1000) { - return EC_ERROR_TIMEOUT; - } - } - - /* Reload the watchdog */ - STM32_IWDG_KR = STM32_IWDG_KR_RELOAD; -#else - /* Start the watchdog (and re-lock registers) */ - STM32_IWDG_KR = STM32_IWDG_KR_START; - - /* - * We should really wait for IWDG_PR and IWDG_RLR value to be updated - * but updating those registers can take about 48ms (found - * empirically, it's 6 LSI cycles at 32kHz). Such a big delay is not - * desired during system init. - * - * However documentation allows us to continue code execution, but - * we should wait for RVU bit to be clear before updating IWDG_RLR - * once again (hard reboot for STM32H7 and STM32F4). - * - * RM0433 Rev 7 - * Section 45.4.4 Page 1920 - * https://www.st.com/resource/en/reference_manual/dm00314099.pdf - * If several reload, prescaler, or window values are used by the - * application, it is mandatory to wait until RVU bit is reset before - * changing the reload value, to wait until PVU bit is reset before - * changing the prescaler value, and to wait until WVU bit is reset - * before changing the window value. However, after updating the - * prescaler and/or the reload/window value it is not necessary to wait - * until RVU or PVU or WVU is reset before continuing code execution - * except in case of low-power mode entry. - */ - -#endif -#ifdef CONFIG_WATCHDOG_HELP - /* Use a harder timer to warn about an impending watchdog reset */ - hwtimer_setup_watchdog(); -#endif - - return EC_SUCCESS; -} |