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| author | Matthew Blecker <matthewb@chromium.org> | 2018-07-26 20:55:35 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-08-09 22:04:40 -0700 |
| commit | b3f08549e2b42a3ac4d9070c559fb91e0b94ef4f (patch) | |
| tree | 1c66d9d99039285101a72a91c20d537d7dc81c44 /chip/stm32 | |
| parent | 740427a24398b3fd66904e913b742f751371d09c (diff) | |
| download | chrome-ec-b3f08549e2b42a3ac4d9070c559fb91e0b94ef4f.tar.gz | |
servo_micro: Add enable_ite_dfu and get_ite_chipid console commands.
enable_ite_dfu: Enable direct firmware update (DFU) over I2C mode on
ITE IT8320 EC chip by sending special non-I2C waveforms over the
I2C bus wires.
get_ite_chipid: Verify that DFU mode is enabled by querying the EC over I2C
for its CHIPID1 and CHIPID2 registers. It will only respond over I2C when
in DFU mode.
BRANCH=none
BUG=b:79684405
TEST=get_ite_chipid succeeds after enable_ite_dfu
Change-Id: Ief2c12ebd902285ea3d285767deb8d35c0017592
Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1152565
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/registers.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index e0425b9271..6e976d5b86 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -544,14 +544,29 @@ REG32(STM32_TIM_BASE(n) + (offset)) #define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) +#define STM32_TIM_CR1_CEN (1 << 0) #define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) #define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) #define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) #define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) #define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) +#define STM32_TIM_EGR_UG (1 << 0) #define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) +#define STM32_TIM_CCMR1_OC1PE (1 << 2) +/* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ +#define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) +#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) +#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) +#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) +#define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2) +#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) +#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) +#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) +#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) +#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) #define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) #define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) +#define STM32_TIM_CCER_CC1E (1 << 0) #define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) #define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) #define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) @@ -561,6 +576,7 @@ #define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) #define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) #define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) +#define STM32_TIM_BDTR_MOE (1 << 15) #define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) #define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) #define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) @@ -1159,6 +1175,8 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) #define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) #define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_APB2ENR_TIM16EN (1 << 17) +#define STM32_RCC_APB2ENR_TIM17EN (1 << 18) #define STM32_RCC_DBGMCUEN (1 << 22) #define STM32_RCC_SYSCFGEN (1 << 0) |