diff options
| author | Bossen WU <bossen.wu@stmicro.corp-partner.google.com> | 2021-07-01 11:48:21 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-02 05:05:12 +0000 |
| commit | fc864d7e8e8f40cba9bc9ee062eaf93c863290d6 (patch) | |
| tree | f46262d36735879cab2ec9b7518f85d587a13e9a /chip/stm32 | |
| parent | a9e3d03396e664288e9bfe781e15648167e6d862 (diff) | |
| download | chrome-ec-fc864d7e8e8f40cba9bc9ee062eaf93c863290d6.tar.gz | |
stm32: clock: avoid division by zero worries.
In chip_config.h, PLLM / PLLN / PLLR was predefined as 0. It raise
concern that frequency calculation would have division by zero issue.
Redefine PLLM / PLLN / PLLR as 1 to remove such worry.
BRANCH=main
BUG=b:188117811
TEST=make buildall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: If57aa40af29e0176762a981bd5b2dac9528b1144
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999412
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/config_chip.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 8b34f2fc44..53f31215ea 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -166,9 +166,9 @@ #define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) -/* Prescaler values for PLL. Currently used only by STM32L476. */ -#define STM32_PLLM 0 -#define STM32_PLLN 0 -#define STM32_PLLR 0 +/* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */ +#define STM32_PLLM 1 +#define STM32_PLLN 1 +#define STM32_PLLR 1 #endif /* __CROS_EC_CONFIG_CHIP_H */ |