stm32g4: ucpd: Move hbit clock config macros to .h file

Honeybuns needs to preset Rd on both CC lines while in RO. But, it
does not have a full usbc/pd stack. The ucpd driver file is not
included either. However, ucpd needs some basic initialization so that
Rd can be applied correctly. This CL moves the macros which are
required to configure the ucpd clocks to the .h file.

BUG=b:172493899
BRANCH=None
TEST=make BOARD=quiche

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I07614a941a05fa133ab4504d9241249066f41e29
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2772738
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Sam Hurst <shurst@google.com>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

2 files changed, 29 insertions, 26 deletions

diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
index 47045229fc..5c9bfbcef3 100644
--- a/chip/stm32/ucpd-stm32gx.c
+++ b/chip/stm32/ucpd-stm32gx.c
@@ -24,32 +24,6 @@
 #define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
 
 #define USB_VID_STM32 0x0483
-/*
- * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
- * a prescaler who's output feeds the 'half-bit' divider which is used
- * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
- * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
- * range is 9 <--> 18 MHz.
- *
- *          ------- @ 16 MHz ---------   @ ~600 kHz   -------------
- * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt |
- *          -------          ---------    |           -------------
- *                                        |           -------------
- *                                        |---------->| ifrgap_cnt|
- *                                                    -------------
- * Requirements:
- *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
- *   2. tTransitionWindow - 12 to 20 uSec
- *   3. tInterframGap - uSec
- *
- * hbit_clk = HSI_clk / 26 = 615,385 kHz = 1.625 uSec period
- * tTransitionWindow = 1.625 uS * 8 = 13 uS
- * tInterFrameGap = 1.625 uS * 17 = 27.625 uS
- */
-#define UCPD_PSC_DIV 1
-#define UCPD_HBIT_DIV 27
-#define UCPD_TRANSWIN_CNT 8
-#define UCPD_IFRGAP_CNT 17
 
 /*
  * USB PD message buffer length. Absent extended messages, the longest PD
diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h
index 06408ab8dc..59b2b7f9bc 100644
--- a/chip/stm32/ucpd-stm32gx.h
+++ b/chip/stm32/ucpd-stm32gx.h
@@ -10,6 +10,35 @@
 #include "usb_pd_tcpm.h"
 
 /*
+ * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
+ * a prescaler who's output feeds the 'half-bit' divider which is used
+ * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
+ * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
+ * range is 9 <--> 18 MHz.
+ *
+ *          ------- @ 16 MHz ---------   @ ~600 kHz   -------------
+ * HSI ---->| /psc |-------->| /hbit |--------------->| trans_cnt |
+ *          -------          ---------    |           -------------
+ *                                        |           -------------
+ *                                        |---------->| ifrgap_cnt|
+ *                                                    -------------
+ * Requirements:
+ *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
+ *   2. tTransitionWindow - 12 to 20 uSec
+ *   3. tInterframGap - uSec
+ *
+ * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
+ * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
+ * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
+ */
+
+#define UCPD_PSC_DIV 1
+#define UCPD_HBIT_DIV 27
+#define UCPD_TRANSWIN_CNT 8
+#define UCPD_IFRGAP_CNT 17
+
+
+/*
  * K-codes and ordered set defines. These codes and sets are used to encode
  * which type of USB-PD message is being sent. This information can be found in
  * the USB-PD spec section 5.4 - 5.6. This info is also included in the STM32G4