diff options
| author | Craig Hesling <hesling@chromium.org> | 2019-12-11 13:28:17 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-21 23:44:00 +0000 |
| commit | cefb6232a83f5122ef4397ba81572183f723ce3f (patch) | |
| tree | 2522a0c62dec7f10fefe53ed0d5a78b975e30519 /chip/stm32 | |
| parent | 62df6c8c83814e3ade12afd346afb11d7a6150c8 (diff) | |
| download | chrome-ec-cefb6232a83f5122ef4397ba81572183f723ce3f.tar.gz | |
chip/stm32: Stop timers and watchdogs on STM32F4 when debugging
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Attach SWD to dragonclaw v0.2
Change-Id: I7bd5741c4862bb2f134ae3067715d2301a18ea78
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962974
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/registers-stm32f4.h | 2 | ||||
| -rw-r--r-- | chip/stm32/system.c | 9 |
2 files changed, 10 insertions, 1 deletions
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h index fbc76d9c3c..e645337242 100644 --- a/chip/stm32/registers-stm32f4.h +++ b/chip/stm32/registers-stm32f4.h @@ -569,6 +569,8 @@ #define STM32_RCC_CSR_LSION BIT(0) #define STM32_RCC_CSR_LSIRDY BIT(1) +#define STM32_RCC_PB2_TIM1 BIT(0) +#define STM32_RCC_PB2_TIM8 BIT(1) #define STM32_RCC_PB2_TIM9 BIT(16) #define STM32_RCC_PB2_TIM10 BIT(17) #define STM32_RCC_PB2_TIM11 BIT(18) diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 37e5d66b78..31434bd49c 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -155,7 +155,14 @@ void chip_pre_init(void) apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; #elif defined(CHIP_FAMILY_STM32F4) - /* TODO(nsanders): Implement this if someone needs jtag. */ + apb1fz_reg = + STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | + STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14| + STM32_RCC_PB1_RTC | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = + STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | STM32_RCC_PB2_TIM9 | + STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32L4) apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | |