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authorShawn Nematbakhsh <shawnn@chromium.org>2017-06-20 17:45:09 -0700
committerchrome-bot <chrome-bot@chromium.org>2017-06-21 01:03:00 -0700
commit0cf4ec5baebcba3c699794b9e034200768ceb5f9 (patch)
tree1571d94c5fb2f6beac1927afe2115e77489082c8 /chip
parent7eae5a320f019a2d8a0b40c060a802c0e7e03c93 (diff)
downloadchrome-ec-0cf4ec5baebcba3c699794b9e034200768ceb5f9.tar.gz
rwsig: Fix mapped read location for rwsig / pubkey
Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not CONFIG_R*_MEM_OFF. The previous implementation happened to work for internal mapped storage (eg. stm32) but failed for external mapped storage which is copied to SRAM before execution (eg. npcx). BUG=b:62841029 TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump and sig verification continues to work on fizz and stm32. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7 Reviewed-on: https://chromium-review.googlesource.com/541861 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/npcx/config_flash_layout.h13
1 files changed, 8 insertions, 5 deletions
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 5ba56610a8..602bdbdc5e 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -47,17 +47,20 @@
#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
-/* RO firmware offset in flash */
+/* RO firmware in program memory - use all of program memory */
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE
-/* RW firmware offset in flash */
-#define CONFIG_RW_MEM_OFF CONFIG_EC_WRITABLE_STORAGE_OFF + \
- CONFIG_RW_STORAGE_OFF
+/*
+ * RW firmware in program memory - Identical to RO, only one image loaded at
+ * a time.
+ */
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
#define CONFIG_RW_SIZE CONFIG_RO_SIZE
-/* The storage offset of ec.R*.flat which is used for firmware_image.lds */
+/* RO image resides at start of protected region, right after header */
#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
+/* RW image resides at start of writable region */
#define CONFIG_RW_STORAGE_OFF 0
#endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */