npcx: system: fix the incorrect checking of invalid BBRAM(IBBR) bit.

This CL adds:
1. Fixed the incorrect address of BKUP_STS register.
2. Cleared the IBBR bit of BKUP_STS register at initial because
its default value is 1(means the content of BBRAM is invalid) whenever
VBAT is powered up.
3. Add debug msg when IBBR bit is set to indicate the BBRAM's
corruption.
4. Modified the valid BBRAM offset from 1 to 0 and size from 63 to 64.

BRANCH=none
BUG=b:38187362
TEST=No build error for make buildall; Check IBBR is cleared at initial.
Check IBBR is set by changing the VBAT voltage below VBAT MIN.
Test console command "reboot ap-off" on poppy.

Change-Id: I69d98b50d4e0aec17b55a4a9b5e8f1a412a3fe45
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505861
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

4 files changed, 49 insertions, 16 deletions

diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index 1b32297013..83c09f130e 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -356,10 +356,13 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal)
 void gpio_pre_init(void)
 {
 	const struct gpio_info *g = gpio_list;
-	int is_warm = system_is_reboot_warm();
+	int is_warm;
 	int flags;
 	int i, j;
 
+	system_check_bbram_on_reset();
+	is_warm = system_is_reboot_warm();
+
 #ifdef CHIP_FAMILY_NPCX7
 	/*
 	 * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 7914caa5b7..e07870cfc2 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -1124,12 +1124,12 @@ enum PM_CHANNEL_T {
 
 /******************************************************************************/
 /* Battery-Backed RAM (BBRAM) Registers */
-#define NPCX_BKUP_STS                REG8(NPCX_BBRAM_BASE_ADDR + 0x000)
-#define NPCX_BBRAM(offset)           REG8(NPCX_BBRAM_BASE_ADDR + 0x001 + offset)
+#define NPCX_BKUP_STS                REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
+#define NPCX_BBRAM(offset)           REG8(NPCX_BBRAM_BASE_ADDR + offset)
 
 /* BBRAM register fields */
 #define NPCX_BKUP_STS_IBBR               7
-#define NPCX_BBRAM_SIZE                  63  /* Size of BBRAM */
+#define NPCX_BBRAM_SIZE                  64  /* Size of BBRAM */
 
 /******************************************************************************/
 /* Timer Watch Dog (TWD) Registers */
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index bce7b17e09..5a6327fe04 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -34,6 +34,7 @@
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
 
 /*****************************************************************************/
 /* Internal functions */
@@ -83,6 +84,42 @@ static int bbram_is_byte_access(enum bbram_data_index index)
 	;
 }
 
+/* Check and clear BBRAM status on power-on reset */
+void system_check_bbram_on_reset(void)
+{
+	/* Check if power on reset */
+	if ((!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) &&
+	    (!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))) {
+		/*
+		 * Clear IBBR bit because it's default value is 1
+		 * on reset whenever the VBAT supply is powered up.
+		 */
+		SET_BIT(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR);
+	} else {
+		/*
+		 * When the reset cause is other than power on reset,
+		 * it is illegal if IBBR is set.
+		 */
+		if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR))
+			CPRINTF("VBAT drop!\n");
+	}
+}
+
+/* Check index is within valid BBRAM range and IBBR is not set */
+static int bbram_valid(enum bbram_data_index index, int bytes)
+{
+	/* Check index */
+	if (index < 0 || index + bytes > NPCX_BBRAM_SIZE)
+		return 0;
+
+	/* Check BBRAM is valid */
+	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
+		CPRINTF("IBBR set: BBRAM corrupted!\n");
+		return 0;
+	}
+	return 1;
+}
+
 /**
  * Read battery-backed ram (BBRAM) at specified index.
  *
@@ -93,12 +130,7 @@ static uint32_t bbram_data_read(enum bbram_data_index index)
 	uint32_t value = 0;
 	int bytes = bbram_is_byte_access(index) ? 1 : 4;
 
-	/* Check index */
-	if (index < 0 || index + bytes >= NPCX_BBRAM_SIZE)
-		return 0;
-
-	/* BBRAM is valid */
-	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR))
+	if (!bbram_valid(index, bytes))
 		return 0;
 
 	/* Read BBRAM */
@@ -124,12 +156,7 @@ static int bbram_data_write(enum bbram_data_index index, uint32_t value)
 {
 	int bytes = bbram_is_byte_access(index) ? 1 : 4;
 
-	/* Check index */
-	if (index < 0 || index >= NPCX_BBRAM_SIZE)
-		return EC_ERROR_INVAL;
-
-	/* BBRAM is valid */
-	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR))
+	if (!bbram_valid(index, bytes))
 		return EC_ERROR_INVAL;
 
 	/* Write BBRAM */
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
index edec22e284..750eb7a662 100644
--- a/chip/npcx/system_chip.h
+++ b/chip/npcx/system_chip.h
@@ -35,6 +35,9 @@ void system_mpu_config(void);
 /* Hibernate function for different Nuvoton chip series. */
 void __hibernate_npcx_series(void);
 
+/* Check and clear BBRAM status on power-on reset */
+void system_check_bbram_on_reset(void);
+
 /* The utilities and variables depend on npcx chip family */
 #if defined(CHIP_FAMILY_NPCX5)
 /* Bypass for GMDA issue of ROM api utilities only on npcx5 series */