npcx: modify the npcxspiflash little firmware to support UUT

The original ec_npcxspiflash lfw is used by the openocd to program SPI
flash via Servo JTAG. In order to support UUT mode to program SPI flash,
this CL modified the lfw with the following changes:
1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming.
2. The npcx_monitor will read the first 4 bytes from the area of monitor
header. If the monitor identifies the first 4 bytes is a UUT tag, it
will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of
monitor header. Otherwise, it will read parameter from the general
register r0/r1 which will be restored by openocd script in advance.
3. Add monitor_hdr.c to generate the monitor header binary files
(monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled.

The memory layout to restore the reuqired binaries are listed below:
ec firmware(RO/RW) - the start address of Code RAM area.
monitor header - 0x200C3000
npcx_monitor - 0x200C3020

BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=Follow instructions in CL:826763; make sure the ec firmware is
updated and ec can boot up.
CQ-DEPEND=CL:828341

Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826909
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>

6 files changed, 161 insertions, 116 deletions

diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index f228a13de1..ff65c95d1e 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -35,10 +35,17 @@ chip-$(CONFIG_SPI)+=spi.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
 
-# spi flash program fw for openocd
-npcx-flash-fw=chip/npcx/spiflashfw/ec_npcxflash
-npcx-flash-fw-bin=${out}/$(npcx-flash-fw).bin
-PROJECT_EXTRA+=${npcx-flash-fw-bin}
+# spi monitor program fw for openocd and UUT(UART Update Tool)
+npcx-monitor-fw=chip/npcx/spiflashfw/npcx_monitor
+npcx-monitor-fw-bin=${out}/$(npcx-monitor-fw).bin
+PROJECT_EXTRA+=${npcx-monitor-fw-bin}
+# Monitor header is only used for UUT which is not supported on npcx5.
+ifneq "$(CHIP_FAMILY)" "npcx5"
+npcx-monitor-hdr=chip/npcx/spiflashfw/monitor_hdr
+npcx-monitor-hdr-ro-bin=${out}/$(npcx-monitor-hdr)_ro.bin
+npcx-monitor-hdr-rw-bin=${out}/$(npcx-monitor-hdr)_rw.bin
+PROJECT_EXTRA+=${npcx-monitor-hdr-ro-bin} ${npcx-monitor-hdr-rw-bin}
+endif
 
 # ECST tool is for filling the header used by booter of npcx EC
 show_esct_cmd=$(if $(V),,echo '  ECST   ' $(subst $(out)/,,$@) ; )
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.ld b/chip/npcx/spiflashfw/ec_npcxflash.ld
deleted file mode 100644
index 3ab642b074..0000000000
--- a/chip/npcx/spiflashfw/ec_npcxflash.ld
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * NPCX5M5G SoC spi flash update tool
- */
-
-/* Memory Spaces Definitions */
-MEMORY
-{
-    CODERAM (rx) : ORIGIN = 0x200C0000, LENGTH = 16K
-    RAM    (xrw) : ORIGIN = 0x200C4000, LENGTH = 16K
-}
-
-/*
- * The entry point is informative, for debuggers and simulators,
- * since the Cortex-M vector points to it anyway.
- */
-ENTRY(sspi_flash_upload)
-
-
-/* Sections Definitions */
-
-SECTIONS
-{
-    .startup_text :
-    {
-        . = ALIGN(4);
-        *(.startup_text )	/* Startup code */
-        . = ALIGN(4);
-    } >CODERAM
-
-    /*
-     * The program code is stored in the .text section,
-     * which goes to CODERAM.
-     */
-    .text :
-    {
-        . = ALIGN(4);
-        *(.text .text.*)			/* all remaining code */
-        *(.rodata .rodata.*)		/* read-only data (constants) */
-    } >CODERAM
-
-    . = ALIGN(4);
-    _etext = .;
-
-    /*
-     * This address is used by the startup code to
-     * initialise the .data section.
-     */
-    _sidata = _etext;
-
-    /*
-     * Used for validation only, do not allocate anything here!
-     *
-     * This is just to check that there is enough RAM left for the Main
-     * stack. It should generate an error if it's full.
-     */
-    .up_flag :
-    {
-        . = ALIGN(4);
-        *(.up_flag )	/* Startup code */
-        . = ALIGN(4);
-    } >RAM
-
-    /*
-     * The initialised data section.
-     */
-    .data  : AT ( _sidata )
-    {
-	    . = ALIGN(4);
-
-        /* This is used by the startup code to initialise the .data section */
-        __data_start__ = . ;
-        *(.data_begin .data_begin.*)
-
-        *(.data .data.*)
-
-        *(.data_end .data_end.*)
-        . = ALIGN(4);
-
-        /* This is used by the startup code to initialise the .data section */
-        __data_end__ = . ;
-
-    } >RAM
-
-    /*
-     * The uninitialised data section. NOLOAD is used to avoid
-     * the "section `.bss' type changed to PROGBITS" warning
-     */
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;	/* standard newlib definition */
-        *(.bss_begin .bss_begin.*)
-
-        *(.bss .bss.*)
-        *(COMMON)
-
-        *(.bss_end .bss_end.*)
-        . = ALIGN(4);
-        __bss_end__ = .;        /* standard newlib definition */
-    } >RAM
-}
diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c
new file mode 100644
index 0000000000..b875eb4e86
--- /dev/null
+++ b/chip/npcx/spiflashfw/monitor_hdr.c
@@ -0,0 +1,37 @@
+/* Copyright (c) 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NPCX SoC spi flash update tool -  monitor firmware header
+ */
+
+#include "config.h"
+#include "npcx_monitor.h"
+
+const struct monitor_header_tag monitor_hdr = {
+	/* 0x00: TAG = 0xA5075001 */
+	NPCX_MONITOR_UUT_TAG,
+	/* 0x04: Size·of·the·EC image·be·programmed.
+	 * Default = code RAM size
+	 */
+	NPCX_PROGRAM_MEMORY_SIZE,
+	/*
+	 * 0x08: The start of RAM address to store the EC image, which will be
+	 * programed into the SPI flash.
+	 */
+	CONFIG_PROGRAM_MEMORY_BASE,
+	/* 0x0C:The Flash start address to be programmed*/
+#ifdef SECTION_IS_RO
+	/* Default: RO image is programed from the start of SPI flash */
+	CONFIG_EC_PROTECTED_STORAGE_OFF,
+#else
+	/* Default: RW image is programed from the half of SPI flash */
+	CONFIG_EC_WRITABLE_STORAGE_OFF,
+#endif
+	/* 0x10: Maximum allowable flash clock frequency */
+	0,
+	/* 0x11: SPI Flash read mode */
+	0,
+	/* 0x12: Reserved */
+	0,
+};
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.c b/chip/npcx/spiflashfw/npcx_monitor.c
index 6f46a4374a..49069c7626 100644
--- a/chip/npcx/spiflashfw/ec_npcxflash.c
+++ b/chip/npcx/spiflashfw/npcx_monitor.c
@@ -2,12 +2,12 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * NPCX5M5G SoC spi flash update tool
+ * NPCX SoC spi flash update tool - monitor firmware
  */
 
 #include <stdint.h>
-
 #include "config.h"
+#include "npcx_monitor.h"
 #include "registers.h"
 #include "util.h"
 
@@ -258,17 +258,33 @@ int sspi_flash_get_image_used(const char *fw_base)
 
 }
 
-volatile __attribute__((section(".up_flag"))) uint32_t flag_upload;
 
 /* Entry function of spi upload function */
-void __attribute__ ((section(".startup_text"), noreturn))
+uint32_t  __attribute__ ((section(".startup_text")))
 sspi_flash_upload(int spi_offset, int spi_size)
 {
 	/*
 	 * Flash image has been uploaded to Code RAM
 	 */
-	const char *image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
-	uint32_t sz_image = spi_size;
+	uint32_t sz_image;
+	uint32_t uut_tag;
+	const char *image_base;
+	uint32_t *flag_upload = (uint32_t *)SPI_PROGRAMMING_FLAG;
+	struct monitor_header_tag *monitor_header =
+		(struct monitor_header_tag *)NPCX_MONITOR_HEADER_ADDR;
+
+	*flag_upload = 0;
+
+	uut_tag = monitor_header->tag;
+	/* If it is UUT tag, read required parameters from header */
+	if (uut_tag == NPCX_MONITOR_UUT_TAG) {
+		sz_image = monitor_header->size;
+		spi_offset = monitor_header->dest_addr;
+		image_base = (const char *)(monitor_header->src_addr);
+	} else {
+		sz_image = spi_size;
+		image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
+	}
 
 	/* Unlock & stop watchdog */
 	NPCX_WDSDM = 0x87;
@@ -295,14 +311,18 @@ sspi_flash_upload(int spi_offset, int spi_size)
 
 		/* Verify data */
 		if (sspi_flash_verify(spi_offset, sz_image, image_base))
-			flag_upload |= 0x02;
+			*flag_upload |= 0x02;
 
 		/* Disable pinmux */
 		sspi_flash_pinmux(0);
 	}
 
 	/* Mark we have finished upload work */
-	flag_upload |= 0x01;
+	*flag_upload |= 0x01;
+
+	/* Return the status back to ROM code is required for UUT */
+	if (uut_tag == NPCX_MONITOR_UUT_TAG)
+		return *flag_upload;
 
 	/* Infinite loop */
 	for (;;)
diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h
new file mode 100644
index 0000000000..f4f30454d2
--- /dev/null
+++ b/chip/npcx/spiflashfw/npcx_monitor.h
@@ -0,0 +1,33 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#ifndef __CROS_EC_NPCX_MONITOR_H
+#define __CROS_EC_NPCX_MONITOR_H
+
+#include <stdint.h>
+
+#define NPCX_MONITOR_UUT_TAG      0xA5075001
+#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
+
+/* Flag to record the progress of programming SPI flash */
+#define SPI_PROGRAMMING_FLAG     0x200C4000
+
+struct monitor_header_tag {
+	/* offset 0x00: TAG NPCX_MONITOR_TAG */
+	uint32_t tag;
+	/* offset 0x04: Size of the binary being programmed (in bytes) */
+	uint32_t size;
+	/* offset 0x08: The RAM address of the binary to program into the SPI */
+	uint32_t src_addr;
+	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
+	uint32_t dest_addr;
+	/* offset 0x10: Maximum allowable flash clock frequency */
+	uint8_t  max_clock;
+	/* offset 0x11: SPI Flash read mode */
+	uint8_t  read_mode;
+	/* offset 0x12: Reserved */
+	uint16_t reserved;
+} __packed;
+
+#endif /* __CROS_EC_NPCX_MONITOR_H */
diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld
new file mode 100644
index 0000000000..d674791728
--- /dev/null
+++ b/chip/npcx/spiflashfw/npcx_monitor.ld
@@ -0,0 +1,52 @@
+/* Copyright (c) 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NPCX SoC spi flash update tool
+ */
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+    CODERAM (rx) : ORIGIN = 0x200C3020, LENGTH = 0xFE0
+}
+
+/*
+ * The entry point is informative, for debuggers and simulators,
+ * since the Cortex-M vector points to it anyway.
+ */
+ENTRY(sspi_flash_upload)
+
+
+/* Sections Definitions */
+
+SECTIONS
+{
+    .startup_text :
+    {
+        . = ALIGN(4);
+        *(.startup_text )	/* Startup code */
+        . = ALIGN(4);
+    } >CODERAM
+
+    /*
+     * The program code is stored in the .text section,
+     * which goes to CODERAM.
+     */
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text .text.*)			/* all remaining code */
+        *(.rodata .rodata.*)		/* read-only data (constants) */
+    } >CODERAM
+
+    . = ALIGN(4);
+    _etext = .;
+
+    /*
+     * This address is used by the startup code to
+     * initialise the .data section.
+     */
+    _sidata = _etext;
+
+}