diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2018-09-25 18:15:56 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-11-05 22:09:19 -0800 |
| commit | 7ba4e5f6cb3d96eb93b6aad45bb28cb2e9f06d1d (patch) | |
| tree | 6885ee87f3a7e993353655903a7b998013a092de /chip | |
| parent | c6f536334535887c6ef95ae1432b79b816ea86b9 (diff) | |
| download | chrome-ec-7ba4e5f6cb3d96eb93b6aad45bb28cb2e9f06d1d.tar.gz | |
cr50: enable ITE CCD programming
This patch enables support of ITE EC programming by Cr50. ITE EC sync
sequence generator implementation is being added to the image, I2C RX
and TX queue sizes are increased to be able to accommodate messages
sent during programming session.
Board level callback function is provided to request ITE SYNC sequence
generation on the next boot, and to reset the H1 with a 10 ms delay,
necessary for CCD host USB communications to quiesce.
Board startup code is modified to when requested invoke function
generating ITE SYNC sequence early in the boot before jitter
configuration is locked.
BRANCH=cr50, cr50-mp
BUG=b:75976718
TEST=with the rest of the patches applied verified that it is possible
to disable and re-enable clock jitter at run time.
Change-Id: I88367b200ceb5b62613f96061d565faa56f4d75a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1263898
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/g/build.mk | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/g/build.mk b/chip/g/build.mk index 77f8ea4a00..402bbdf537 100644 --- a/chip/g/build.mk +++ b/chip/g/build.mk @@ -67,6 +67,8 @@ chip-y+= jitter.o chip-y+= pmu.o chip-y+= trng.o chip-y+= runlevel.o +chip-$(CONFIG_CCD_ITE_PROGRAMMING)+= ite_flash.o +chip-$(CONFIG_CCD_ITE_PROGRAMMING)+= ite_sync.o chip-$(CONFIG_ENABLE_H1_ALERTS)+= alerts.o chip-$(CONFIG_USB_FW_UPDATE)+= usb_upgrade.o chip-$(CONFIG_NON_HC_FW_UPDATE)+= upgrade_fw.o post_reset.o upgrade.o |