diff options
author | Vadim Bendebury <vbendeb@chromium.org> | 2017-10-31 18:51:51 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-07 17:52:15 -0800 |
commit | 3919001a390f593ba8e022f223bf1e43b7dbc0a2 (patch) | |
tree | 5a5534aca31394c15d4cc6f09197348b66f786ef /chip | |
parent | 0354ad02cba910c90fd0c0e622c3b0b698802a1c (diff) | |
download | chrome-ec-3919001a390f593ba8e022f223bf1e43b7dbc0a2.tar.gz |
tpm: provide means of shutting down comms layer while in reset
Currently the Cr50 code resets TPM communications layer at a certain
point during TPM reset process.
It turns out that this is not sufficient - the comms layer keeps
receiving and trying to invoke TPM layer, which does not mesh well
with TPM reset.
Let's provide two callbacks for each comms layer - to shut it down and
to bring it back up. We shut down the comms when starting TPM reset
and bring them back up when reset is completed.
BRANCH=cr50
BUG=b:68012381
TEST=ran AP firmware test suite on both SPI and I2C based devices.
Change-Id: I7caf4a09b9a5c6e5fc6bfe60eae1c0d64ab24904
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/754502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/i2cs.c | 4 | ||||
-rw-r--r-- | chip/g/sps.c | 3 | ||||
-rw-r--r-- | chip/g/sps_tpm.c | 16 |
3 files changed, 18 insertions, 5 deletions
diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c index 8c00c4ddea..0cd5abf13f 100644 --- a/chip/g/i2cs.c +++ b/chip/g/i2cs.c @@ -351,6 +351,10 @@ void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len) int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler) { task_disable_irq(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT); + + if (!wc_handler) + return 0; + i2cs_init(); write_complete_handler_ = wc_handler; task_enable_irq(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT); diff --git a/chip/g/sps.c b/chip/g/sps.c index 6a5fed0ee3..fc7a0d8458 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -215,6 +215,9 @@ int sps_register_rx_handler(enum sps_mode mode, rx_handler_f rx_handler, task_disable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR); task_disable_irq(GC_IRQNUM_SPS0_CS_DEASSERT_INTR); + if (!rx_handler) + return 0; + if (!rx_fifo_threshold) rx_fifo_threshold = 8; /* This is a sensible default. */ sps_rx_handler = rx_handler; diff --git a/chip/g/sps_tpm.c b/chip/g/sps_tpm.c index 1d7706e432..5d5073bb6f 100644 --- a/chip/g/sps_tpm.c +++ b/chip/g/sps_tpm.c @@ -265,14 +265,20 @@ static void tpm_rx_handler(uint8_t *data, size_t data_size, int cs_disabled) init_new_cycle(); } -static void sps_tpm_enable(void) +static void sps_if_stop(void) +{ + /* Let's shut down the interface while TPM is being reset. */ + sps_register_rx_handler(0, NULL, 0); +} + +static void sps_if_start(void) { /* - * Let's make sure we get an interrupt as soon as the header is - * received. + * Threshold of 3 makes sure we get an interrupt as soon as the header + * is received. */ - sps_register_rx_handler(SPS_GENERIC_MODE, tpm_rx_handler, 3); init_new_cycle(); + sps_register_rx_handler(SPS_GENERIC_MODE, tpm_rx_handler, 3); } @@ -281,6 +287,6 @@ static void sps_if_register(void) if (!board_tpm_uses_spi()) return; - tpm_register_interface(sps_tpm_enable); + tpm_register_interface(sps_if_start, sps_if_stop); } DECLARE_HOOK(HOOK_INIT, sps_if_register, HOOK_PRIO_LAST); |