Add IRQ constants, and task functions to enable/disable/trigger IRQs.

The constants don't work with the DECLARE_IRQ() macro yet, because it
relies on stringizing the IRQ number.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=none
TEST=none

Change-Id: Ie6ddecd79e28c319b095089131579ba994a17da3
(cherry picked from commit e24904644a977f2618f51629cc066b93a3d53595)

6 files changed, 57 insertions, 17 deletions

diff --git a/chip/lm4/init.S b/chip/lm4/init.S
index 4d58cae563..df55b13226 100644
--- a/chip/lm4/init.S
+++ b/chip/lm4/init.S
@@ -202,8 +202,8 @@ data_loop:
 
     /**
      * Set stack pointer
-     * already done my Cortex-M hardware but this allows software to jump directly
-     * to reset function or to run on other ARM
+     * already done my Cortex-M hardware but this allows software to
+     * jump directly to reset function or to run on other ARM
      */
     ldr r0, =stack_end
     mov sp, r0
diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h
index 91fc2f90be..8038ac9b4b 100644
--- a/chip/lm4/registers.h
+++ b/chip/lm4/registers.h
@@ -177,6 +177,20 @@ static inline int lm4_lpc_addr(int ch, int offset)
 #define LM4_NVIC_PRI(x)        LM4REG(0xe000e400 + 4 * (x))
 #define LM4_NVIC_APINT         LM4REG(0xe000ed0c)
 #define LM4_NVIC_SWTRIG        LM4REG(0xe000ef00)
+/* IRQ numbers */
+#define LM4_IRQ_GPIOD            3
+#define LM4_IRQ_UART0            5
+#define LM4_IRQ_UART1            6
+#define LM4_IRQ_I2C0             8
+#define LM4_IRQ_WATCHDOG        18
+#define LM4_IRQ_I2C1            37
+#define LM4_IRQ_I2C2            68
+#define LM4_IRQ_I2C3            69
+#define LM4_IRQ_TIMERW0A        94
+#define LM4_IRQ_TIMERW1A        96
+#define LM4_IRQ_LPC            108
+#define LM4_IRQ_I2C4           109
+#define LM4_IRQ_I2C5           110
 
 #define LM4_SCB_SYSCTRL        LM4REG(0xe000ed10)
 
diff --git a/chip/lm4/task.c b/chip/lm4/task.c
index 5c4ee8780c..85976e07ab 100644
--- a/chip/lm4/task.c
+++ b/chip/lm4/task.c
@@ -244,11 +244,31 @@ uint32_t task_send_msg(task_id_t tskid, task_id_t from, int wait)
 	return 0;
 }
 
+
 uint32_t task_wait_msg(int timeout_us)
 {
 	return __wait_msg(timeout_us, TASK_ID_IDLE);
 }
 
+
+void task_enable_irq(int irq)
+{
+	LM4_NVIC_EN(irq / 32) = 1 << (irq % 32);
+}
+
+
+void task_disable_irq(int irq)
+{
+	LM4_NVIC_DIS(irq / 32) = 1 << (irq % 32);
+}
+
+
+void task_trigger_irq(int irq)
+{
+	LM4_NVIC_SWTRIG = irq;
+}
+
+
 /**
  * Enable all used IRQ in the NVIC and set their priorities
  * as defined by the DECLARE_IRQ statements
@@ -269,7 +289,10 @@ static void __nvic_init_irqs(void)
 				(LM4_NVIC_PRI(irq / 4) &
 				 ~(0x7 << prio_shift)) |
 				(prio << prio_shift);
-		LM4_NVIC_EN(irq / 32) |= 1<<(irq % 32);
+
+		/* TODO: enabling all interrupts here causes a race condition
+		   between an interrupt and setting up the handler for it. */
+		task_enable_irq(irq);
 	}
 }
 
diff --git a/chip/lm4/timer.c b/chip/lm4/timer.c
index 597c61da95..5d83edba4b 100644
--- a/chip/lm4/timer.c
+++ b/chip/lm4/timer.c
@@ -170,7 +170,7 @@ int timer_arm(timestamp_t tstamp, task_id_t tskid)
 	/* modify the next event if needed */
 	if ((tstamp.le.hi < clksrc_high) ||
 	    ((tstamp.le.hi == clksrc_high) && (tstamp.le.lo <= next_deadline)))
-		LM4_NVIC_SWTRIG = 94;
+		task_trigger_irq(LM4_IRQ_TIMERW0A);
 
 	return EC_SUCCESS;
 }
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
index f7f785301d..430c3ecde0 100644
--- a/chip/lm4/uart.c
+++ b/chip/lm4/uart.c
@@ -128,6 +128,8 @@ static void uart_0_interrupt(void)
 	if (tx_buf_tail == tx_buf_head)
 		LM4_UART_IM(0) &= ~0x20;
 }
+/* TODO: can't use LM4_IRQ_UART0 constant because it messes with the
+ * DECLARE_IRQ() macro. */
 DECLARE_IRQ(5, uart_0_interrupt, 1);
 
 
@@ -248,7 +250,7 @@ int uart_puts(const char *outstr)
 		 * UART where the FIFO only triggers the interrupt when its
 		 * threshold is _crossed_, not just met. */
 		LM4_UART_IM(0) |= 0x20;
-		LM4_NVIC_SWTRIG = 5;
+		task_trigger_irq(LM4_IRQ_UART0);
 	}
 
 	/* Successful if we consumed all output */
@@ -388,7 +390,7 @@ int uart_printf(const char *format, ...)
 		 * UART where the FIFO only triggers the interrupt when its
 		 * threshold is _crossed_, not just met. */
 		LM4_UART_IM(0) |= 0x20;
-		LM4_NVIC_SWTRIG = 5;
+		task_trigger_irq(LM4_IRQ_UART0);
 	}
 
 	/* Successful if we consumed all output */
@@ -409,7 +411,7 @@ void uart_flush_output(void)
 		 * printf() and back. */
 		if (!(LM4_UART_IM(0) & 0x20)) {
 			LM4_UART_IM(0) |= 0x20;
-			LM4_NVIC_SWTRIG = 5;
+			task_trigger_irq(LM4_IRQ_UART0);
 		}
 	}
 
@@ -437,7 +439,7 @@ void uart_emergency_flush(void)
 void uart_flush_input(void)
 {
 	/* Disable interrupts */
-	LM4_NVIC_DIS(0) = (1 << 5);
+	task_disable_irq(LM4_IRQ_UART0);
 
 	/* Call interrupt handler to empty the hardware FIFO */
 	uart_0_interrupt();
@@ -446,7 +448,7 @@ void uart_flush_input(void)
 	rx_buf_tail = rx_buf_head;
 
 	/* Re-enable interrupts */
-	LM4_NVIC_EN(0) = (1 << 5);
+	task_enable_irq(LM4_IRQ_UART0);
 }
 
 
@@ -457,7 +459,7 @@ int uart_peek(int c)
 
 	/* Disable interrupts while we pull characters out, because the
 	 * interrupt handler can also modify the tail pointer. */
-	LM4_NVIC_DIS(0) = (1 << 5);
+	task_disable_irq(LM4_IRQ_UART0);
 
 	/* Call interrupt handler to empty the hardware FIFO.  The minimum
 	 * FIFO trigger depth is 1/8 (2 chars), so this is the only way to
@@ -473,7 +475,7 @@ int uart_peek(int c)
 	}
 
 	/* Re-enable interrupts */
-	LM4_NVIC_EN(0) = (1 << 5);
+	task_enable_irq(LM4_IRQ_UART0);
 
 	return index;
 }
@@ -484,7 +486,7 @@ int uart_getc(void)
 	int c;
 
 	/* Disable interrupts */
-	LM4_NVIC_DIS(0) = (1 << 5);
+	task_disable_irq(LM4_IRQ_UART0);
 
 	/* Call interrupt handler to empty the hardware FIFO */
 	uart_0_interrupt();
@@ -497,7 +499,7 @@ int uart_getc(void)
 	}
 
 	/* Re-enable interrupts */
-	LM4_NVIC_EN(0) = (1 << 5);
+	task_enable_irq(LM4_IRQ_UART0);
 
 	return c;
 }
@@ -510,7 +512,7 @@ int uart_gets(char *dest, int size)
 
 	/* Disable interrupts while we pull characters out, because the
 	 * interrupt handler can also modify the tail pointer. */
-	LM4_NVIC_DIS(0) = (1 << 5);
+	task_disable_irq(LM4_IRQ_UART0);
 
 	/* Call interrupt handler to empty the hardware FIFO */
 	uart_0_interrupt();
@@ -525,7 +527,7 @@ int uart_gets(char *dest, int size)
 	}
 
 	/* Re-enable interrupts */
-	LM4_NVIC_EN(0) = (1 << 5);
+	task_enable_irq(LM4_IRQ_UART0);
 
 	/* Null-terminate */
 	dest[got] = '\0';
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c
index d42716abf5..42a8c8961d 100644
--- a/chip/lm4/watchdog.c
+++ b/chip/lm4/watchdog.c
@@ -46,7 +46,7 @@ void watchdog_trace(uint32_t excep_lr, uint32_t excep_sp)
 	 * instead de-activate the interrupt in the NVIC :
 	 * so, we will get the trace only once
 	 */
-	LM4_NVIC_DIS(0) = 1 << 18;
+	task_disable_irq(LM4_IRQ_WATCHDOG);
 
 	asm("mrs %0, psp":"=r"(psp));
 	if ((excep_lr & 0xf) == 1) {
@@ -81,7 +81,8 @@ void irq_18_handler(void)
 		     "b task_resched_if_needed\n");
 }
 const struct irq_priority prio_18 __attribute__((section(".rodata.irqprio")))
-		= {18, 0}; /* put the watchdog at the highest priority */
+		= {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest
+					    priority */
 
 void watchdog_reload(void)
 {