diff options
author | Namyoon Woo <namyoon@chromium.org> | 2019-08-02 11:25:35 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-01-28 02:28:58 +0000 |
commit | 627284895b3400482e2c1aee6b4de955858f7cd3 (patch) | |
tree | ff523cabc19d7736cd1a2225d459293610e3f9bf /chip | |
parent | c422b7bdbb06ecb8024318351a298d2553746faf (diff) | |
download | chrome-ec-627284895b3400482e2c1aee6b4de955858f7cd3.tar.gz |
extend INT_AP_L pulse
This patch extends INT_AP_L pulses to be at least 6.5 micro seconds.
It is a tentative solution to to meet Intel TGL/JSL requirement on
interrupt duration.
BUG=b:130515803
BRANCH=cr50
TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec
with logic analyzer on Hatch.
Checked dmesg and coreboot log has no TPM errors.
Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 2367420fd6f4a7db36c7cb566aa256e873fb33eb)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014047
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Commit-Queue: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit 6e78756f64d2041867d50d746d3562cc567adb67)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2024361
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/hwtimer.c | 9 | ||||
-rw-r--r-- | chip/g/sps.c | 10 |
2 files changed, 19 insertions, 0 deletions
diff --git a/chip/g/hwtimer.c b/chip/g/hwtimer.c index 91dba78c40..69c329f374 100644 --- a/chip/g/hwtimer.c +++ b/chip/g/hwtimer.c @@ -211,3 +211,12 @@ void udelay(unsigned us) ; } #endif /* CONFIG_HW_SPECIFIC_UDELAY */ + +void tick_delay(uint32_t ticks) +{ + uint32_t cur_tick = GREG32(TIMELS, SOURCE(VALUE)); + + /* Note: the counter counts down. */ + while ((cur_tick - GREG32(TIMELS, SOURCE(VALUE))) < ticks) + ; +} diff --git a/chip/g/sps.c b/chip/g/sps.c index 5fd6735dd8..7f8b81de9b 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -344,6 +344,16 @@ static void sps_rx_interrupt(uint32_t port, int cs_deasserted) * completed. */ gpio_set_level(GPIO_INT_AP_L, 0); + + /* + * This is to meet the AP requirement of minimum 4 usec + * duration of INT_AP_L assertion. + * + * TODO(b/130515803): Ideally, this should be improved + * to support any duration requirement in future. + */ + tick_delay(2); + gpio_set_level(GPIO_INT_AP_L, 1); seen_data = 0; } |