it83xx/spi: enable rx valid length interrupt

Enable IT83XX_SPI_RX_VALID_INT which can obtain data length field of
host requested. When received data to reach, Rx valid interrupt will
be fired then start to parse.
Instead of waiting for Rx 256 bytes reach interrupt method, this is
effectively saving time to complete once transaction.

BUG=b:160662061; b:161509047
BRANCH=none
TEST=Boot to kernel with it81202 on asurada.
     No error on the command of get EC protocol info with
     1MHz clock frequency.

Change-Id: Ib56e3034d3ee39fa64818b95747eb7e9e5821294
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076826
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>

3 files changed, 50 insertions, 0 deletions

diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
index e7c4e880de..dbcd6b9dd9 100644
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ b/chip/it83xx/config_chip_it8xxx2.h
@@ -124,6 +124,8 @@
 #define IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED
 /* Auto reset rx fifo while CS# deasserted. */
 #define IT83XX_SPI_AUTO_RESET_RX_FIFO
+/* CPU accesses FIFO to reach rx valid data length. */
+#define IT83XX_SPI_RX_VALID_INT
 /* Individual setting CC1 and CC2 resistance. */
 #define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
 /* Chip actually has TCPC physical port count. */
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index f925691dab..56a4500bf6 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1325,7 +1325,13 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
 #define IT83XX_SPI_RXFRDRB0     REG32(IT83XX_SPI_BASE+0x0C)
 #define IT83XX_SPI_FTCB0R       REG8(IT83XX_SPI_BASE+0x18)
 #define IT83XX_SPI_FTCB1R       REG8(IT83XX_SPI_BASE+0x19)
+#define IT83XX_SPI_TCCB0        REG8(IT83XX_SPI_BASE+0x1A)
+#define IT83XX_SPI_TCCB1        REG8(IT83XX_SPI_BASE+0x1B)
 #define IT83XX_SPI_HPR2         REG8(IT83XX_SPI_BASE+0x1E)
+#define IT83XX_SPI_RX_VLISMR    REG8(IT83XX_SPI_BASE+0x26)
+#define IT83XX_SPI_RVLIM           BIT(0)
+#define IT83XX_SPI_RX_VLISR     REG8(IT83XX_SPI_BASE+0x27)
+#define IT83XX_SPI_RVLI            BIT(0)
 
 /* Platform Environment Control Interface (PECI) */
 #define IT83XX_PECI_BASE  0x00F02C00
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
index 4c70634bc2..30690d4140 100644
--- a/chip/it83xx/spi.c
+++ b/chip/it83xx/spi.c
@@ -246,8 +246,10 @@ void spi_slv_int_handler(void)
 		/* Reset fifo and prepare to receive next transaction */
 		reset_rx_fifo();
 #endif
+#ifndef IT83XX_SPI_RX_VALID_INT
 		/* Enable Rx byte reach interrupt */
 		IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH;
+#endif
 		/* Ready to receive */
 		spi_set_state(SPI_STATE_READY_TO_RECV);
 		/*
@@ -259,6 +261,7 @@ void spi_slv_int_handler(void)
 		IT83XX_SPI_ISR = 0xff;
 	}
 
+#ifndef IT83XX_SPI_RX_VALID_INT
 	/*
 	 * The status of Rx byte reach interrupt bit is set,
 	 * start to parse transaction.
@@ -277,6 +280,19 @@ void spi_slv_int_handler(void)
 		/* Parse header for version of spi-protocol */
 		spi_parse_header();
 	}
+#else
+	/*
+	 * The status of Rx valid length interrupt bit is set that indicates
+	 * reached target count(IT83XX_SPI_FTCB1R, IT83XX_SPI_FTCB0R) and the
+	 * length of length field of the host requested data.
+	 */
+	if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) {
+		/* write clear slave status */
+		IT83XX_SPI_RX_VLISR = IT83XX_SPI_RVLI;
+		/* Parse header for version of spi-protocol */
+		spi_parse_header();
+	}
+#endif
 
 	/* Clear the interrupt status */
 	task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE);
@@ -284,6 +300,18 @@ void spi_slv_int_handler(void)
 
 static void spi_init(void)
 {
+#ifdef IT83XX_SPI_RX_VALID_INT
+	struct ec_host_request cmd_head;
+	/*
+	 * Target count means the size of host request.
+	 * And plus extra 4 bytes because the CPU accesses FIFO base on word.
+	 * If host requested data length is one byte, we need to align the
+	 * data length to 4 bytes.
+	 */
+	int target_count = sizeof(cmd_head) + 4;
+	/* Offset of data_len member of host request. */
+	int offset = (char *)&cmd_head.data_len - (char *)&cmd_head;
+#endif
 	/* Set SPI pins to alternate function */
 	gpio_config_module(MODULE_SPI, 1);
 	/*
@@ -294,8 +322,20 @@ static void spi_init(void)
 	/* Set unused blocked byte */
 	IT83XX_SPI_HPR2 = 0x00;
 	/* Set FIFO data target count */
+#ifdef IT83XX_SPI_RX_VALID_INT
+	IT83XX_SPI_FTCB1R = (target_count >> 8) & 0xff;
+	IT83XX_SPI_FTCB0R = target_count & 0xff;
+	/* The register setting can capture the length field of host request. */
+	IT83XX_SPI_TCCB1 = (offset >> 8) & 0xff;
+	IT83XX_SPI_TCCB0 = offset & 0xff;
+#else
 	IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff;
 	IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff;
+#endif
+#ifdef IT83XX_SPI_RX_VALID_INT
+	/* Rx valid length interrupt enabled */
+	IT83XX_SPI_RX_VLISMR &= ~IT83XX_SPI_RVLIM;
+#endif
 #ifdef IT83XX_SPI_AUTO_RESET_RX_FIFO
 	/*
 	 * General control register2
@@ -314,8 +354,10 @@ static void spi_init(void)
 	IT83XX_SPI_IMR &= ~IT83XX_SPI_EDIM;
 	/* Reset fifo and prepare to for next transaction */
 	reset_rx_fifo();
+#ifndef IT83XX_SPI_RX_VALID_INT
 	/* Enable Rx byte reach interrupt */
 	IT83XX_SPI_IMR &= ~IT83XX_SPI_RX_REACH;
+#endif
 	/* Ready to receive */
 	spi_set_state(SPI_STATE_READY_TO_RECV);
 	/* Interrupt status register(write one to clear) */