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| author | Scott Collyer <scollyer@google.com> | 2020-04-06 17:11:10 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-29 03:49:10 +0000 |
| commit | cfc1ae3de25687f6c4350dc99878c2a980ff0a90 (patch) | |
| tree | 2ede0da8d79ca9dab542bc04ec7d9eefbfd01197 /chip | |
| parent | ad2d43937e22bea80e42af692c1593d928828ae4 (diff) | |
| download | chrome-ec-cfc1ae3de25687f6c4350dc99878c2a980ff0a90.tar.gz | |
stm32g4: Modifications required for system.c
This CL updates stm32 specific system.c for the stm32g4 chip family. A
comment was added to clarify what's required for enabling the backup
domain. In addition, debug mode and detection of a warm boot.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I8b5063419ae6dc1be165b8bb3754703c1e728ae9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195544
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/system.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index a32606df99..aad35820c7 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -179,6 +179,17 @@ void chip_pre_init(void) STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; +#elif defined(CHIP_FAMILY_STM32G4) + apb1fz_reg = + STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 | + STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 | + STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 | + STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG | + STM32_DBGMCU_APB1FZ_IWDG; + apb2fz_reg = + STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 | + STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 | + STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20; #elif defined(CHIP_FAMILY_STM32H7) /* TODO(b/67081508) */ #endif @@ -279,7 +290,7 @@ void system_pre_init(void) } #elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32F4) || \ - defined(CHIP_FAMILY_STM32H7) + defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4) if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) { /* The RTC settings are bad, we need to reset it */ STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; @@ -541,6 +552,9 @@ int system_is_reboot_warm(void) #elif defined(CHIP_FAMILY_STM32F4) return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) == gpio_required_clocks()); +#elif defined(CHIP_FAMILY_STM32G4) + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) + == gpio_required_clocks()); #elif defined(CHIP_FAMILY_STM32H7) return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) == STM32_RCC_AHB4ENR_GPIOMASK); |