Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper --relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-fpmcu-bloonchipper-release

Relevant changes:

git log --oneline ad46fafb27..a46d3f3fea -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

981fb88cf8 docs/fingerprint: Resolve contradictory FPMCU factory flashing instructions
38ef6b7306 tree: Files should end with single newline
60032a8828 docs/fingerprint: Clean up formatting in fingerprint-factory-quick-guide.md
f49eb6f894 docs/fingerprint: Run mdformat
64aa5fc7bb docs/fingerprint: Add links to info on fuzz testing
8bd99cc434 fpsensor: Use correct return type
2b2d7a991d fpsensor: Use correct return type

BRANCH=None
BUG=b:234772776 b:234181908 b:172020503 b:234181908
TEST=`make -j buildall`

Cq-Include-Trybots: chromeos/cq:cq-orchestrator
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Change-Id: I18b58de542c8b439d0f9327a7d4f0ec897da080f

12 files changed, 116 insertions, 21 deletions

diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
index d06aa8d204..0bbfe89b59 100644
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ b/chip/it83xx/config_chip_it8xxx2.h
@@ -6,6 +6,8 @@
 #ifndef __CROS_EC_CONFIG_CHIP_IT8XXX2_H
 #define __CROS_EC_CONFIG_CHIP_IT8XXX2_H
 
+#define __RAM_CODE_ILM0_SECTION_NAME ".ram_code_ilm0"
+
 /* CPU core BFD configuration */
 #include "core/riscv-rv32i/config_core.h"
 
@@ -85,6 +87,13 @@
 || defined(CHIP_VARIANT_IT81302BX_512) \
 || defined(CHIP_VARIANT_IT81202BX_1024)
 
+/*
+ * Workaround mul instruction bug, see:
+ * https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
+ */
+#undef CONFIG_RISCV_EXTENSION_M
+#define CONFIG_IT8XXX2_MUL_WORKAROUND
+
 #if defined(CHIP_VARIANT_IT81302BX_512)
 #define CONFIG_FLASH_SIZE_BYTES     0x00080000
 #define CONFIG_RAM_BASE             0x80080000
diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
index e0f5636b2e..ea1ea6c330 100644
--- a/chip/max32660/build.mk
+++ b/chip/max32660/build.mk
@@ -9,7 +9,7 @@
 # MAX32660 SoC has a Cortex-M4F ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Required chip modules
 chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o
@@ -18,4 +18,3 @@ chip-$(CONFIG_I2C)+=i2c_chip.o
 # Optional chip modules
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o
 chip-$(CONFIG_WATCHDOG)+=wdt_chip.o
-
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 6dec772ce3..1e3de24d06 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -15,7 +15,7 @@ endif
 # MCHP MEC SoC's have a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # JTAG debug with Keil ARM MDK debugger
 # do not allow GCC dwarf debug extensions
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
index a17a2cad5f..7dadf60c88 100644
--- a/chip/mec1322/build.mk
+++ b/chip/mec1322/build.mk
@@ -9,7 +9,7 @@
 # MEC1322 SoC has a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 ifeq ($(CONFIG_LTO),y)
 # Re-include the core's build.mk file so we can remove the lto flag.
diff --git a/chip/mt_scp/mt818x/build.mk b/chip/mt_scp/mt818x/build.mk
index bf450fb135..e9f77a2833 100644
--- a/chip/mt_scp/mt818x/build.mk
+++ b/chip/mt_scp/mt818x/build.mk
@@ -4,7 +4,7 @@
 # found in the LICENSE file.
 
 CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Required chip modules
 chip-y+=mt818x/clock_$(CHIP_VARIANT).o
diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk
index c81bd83595..e61cdafb01 100644
--- a/chip/mt_scp/mt8192/build.mk
+++ b/chip/mt_scp/mt8192/build.mk
@@ -7,4 +7,3 @@
 chip-y+=$(CHIP_VARIANT)/uart.o
 chip-y+=$(CHIP_VARIANT)/clock.o
 chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk
index c81bd83595..e61cdafb01 100644
--- a/chip/mt_scp/mt8195/build.mk
+++ b/chip/mt_scp/mt8195/build.mk
@@ -7,4 +7,3 @@
 chip-y+=$(CHIP_VARIANT)/uart.o
 chip-y+=$(CHIP_VARIANT)/clock.o
 chip-y+=$(CHIP_VARIANT)/video.o
-
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index 1fe524763b..d7e61de4de 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -9,7 +9,7 @@
 # NPCX SoC has a Cortex-M4F ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 
 # Disable overlapping section warning that linker emits due to NPCX_RO_HEADER.
 LDFLAGS_EXTRA+=-Wl,--no-check-sections
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 13a6aa752a..0d47a0131a 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -9,33 +9,28 @@
 ifeq ($(CHIP_FAMILY),stm32f0)
 # STM32F0xx sub-family has a Cortex-M0 ARM core
 CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
+CFLAGS_CPU+=-mcpu=cortex-m0
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
 stm32g4))
 # STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
 # STM32FH7xx family has a Cortex-M7 ARM core
 CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+# Allow the full Cortex-M7 instruction set.
+CFLAGS_CPU+=-mcpu=cortex-m7
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
 # STM32FL5xx family has a Cortex-M33 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M33 instruction set
-CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33
+CFLAGS_CPU+=-mcpu=cortex-m33
 else
 # other STM32 SoCs have a Cortex-M3 ARM core
 CORE:=cortex-m
 # Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
+CFLAGS_CPU+=-mcpu=cortex-m3
 endif
 
 # Select between 16-bit and 32-bit timer for clock source
diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c
index 17bb5d8e32..e34afde7e1 100644
--- a/chip/stm32/spi_controller.c
+++ b/chip/stm32/spi_controller.c
@@ -334,6 +334,8 @@ static int spi_dma_wait(int port)
 	return rv;
 }
 
+static uint8_t spi_chip_select_already_asserted[ARRAY_SIZE(SPI_REGS)];
+
 int spi_transaction_async(const struct spi_device_t *spi_device,
 			  const uint8_t *txdata, int txlen,
 			  uint8_t *rxdata, int rxlen)
@@ -360,6 +362,11 @@ int spi_transaction_async(const struct spi_device_t *spi_device,
 	}
 #endif
 
+	if (IS_ENABLED(CONFIG_USB_SPI)) {
+		spi_chip_select_already_asserted[port] =
+			!gpio_get_level(spi_device->gpio_cs);
+	}
+
 	/* Drive SS low */
 	gpio_set_level(spi_device->gpio_cs, 0);
 
@@ -403,8 +410,11 @@ int spi_transaction_flush(const struct spi_device_t *spi_device)
 {
 	int rv = spi_dma_wait(spi_device->port);
 
-	/* Drive SS high */
-	gpio_set_level(spi_device->gpio_cs, 1);
+	if (!IS_ENABLED(CONFIG_USB_SPI)
+	    || !spi_chip_select_already_asserted[spi_device->port]) {
+		/* Drive SS high */
+		gpio_set_level(spi_device->gpio_cs, 1);
+	}
 
 	return rv;
 }
diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c
index 86254ddaac..e80d15b6cd 100644
--- a/chip/stm32/usb_spi.c
+++ b/chip/stm32/usb_spi.c
@@ -4,6 +4,7 @@
  */
 
 #include "common.h"
+#include "gpio.h"
 #include "link_defs.h"
 #include "registers.h"
 #include "spi.h"
@@ -178,6 +179,15 @@ static void create_spi_config_response(struct usb_spi_config const *config,
 		sizeof(struct usb_spi_response_configuration_v2);
 }
 
+static void create_spi_chip_select_response(struct usb_spi_config const *config,
+					    struct usb_spi_packet_ctx *packet)
+{
+	/* Construct the response packet. */
+	packet->rsp_cs.packet_id = USB_SPI_PKT_ID_RSP_CHIP_SELECT;
+	packet->rsp_cs.status_code = 0;
+	packet->packet_size = sizeof(packet->rsp_cs);
+}
+
 /*
  * If we have a transfer response in progress, this will construct the
  * next entry. If no transfer is in progress or if we are unable to
@@ -334,6 +344,24 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
 
 		break;
 	}
+	case USB_SPI_PKT_ID_CMD_CHIP_SELECT:
+	{
+		/*
+		 * The host is requesting the chip select line be
+		 * asserted or deasserted.
+		 */
+		uint16_t flags = packet->cmd_cs.flags;
+
+		if (flags & USB_SPI_CHIP_SELECT) {
+			/* Set chip select low (asserted). */
+			gpio_set_level(SPI_FLASH_DEVICE->gpio_cs, 0);
+		} else {
+			/* Set chip select high (adesserted). */
+			gpio_set_level(SPI_FLASH_DEVICE->gpio_cs, 1);
+		}
+		config->state->mode = USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE;
+		break;
+	}
 	default:
 	{
 		/* An unknown USB packet was delivered. */
@@ -388,6 +416,13 @@ void usb_spi_deferred(struct usb_spi_config const *config)
 		config->state->mode = USB_SPI_MODE_IDLE;
 		return;
 	}
+	/* Need to send response to USB SPI chip select. */
+	if (config->state->mode == USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE) {
+		create_spi_chip_select_response(config, transmit_packet);
+		usb_spi_write_packet(config, transmit_packet);
+		config->state->mode = USB_SPI_MODE_IDLE;
+		return;
+	}
 
 	/* Start a new SPI transfer. */
 	if (config->state->mode == USB_SPI_MODE_START_SPI) {
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
index a1be2c11fb..fa86ba3651 100644
--- a/chip/stm32/usb_spi.h
+++ b/chip/stm32/usb_spi.h
@@ -232,6 +232,30 @@
  *
  *     packet id:         2 byte enum USB_SPI_PKT_ID_CMD_RESTART_RESPONSE
  *
+ * Command chip select Packet (Host to Device):
+ *
+ *     +----------------+-------------+
+ *     | packet id : 2B | action : 2B |
+ *     +----------------+-------------+
+ *
+ *     packet id:         2 byte enum USB_SPI_PKT_ID_CMD_CHIP_SELECT
+ *
+ *     action:            2 byte, current options:
+ *                            0: Deassert chip select
+ *                            1: Assert chip select
+ *
+ * Response chip select Packet (Device to Host):
+ *
+ *     +----------------+------------------+
+ *     | packet id : 2B | status code : 2B |
+ *     +----------------+------------------+
+ *
+ *     packet id:     2 byte enum USB_SPI_PKT_ID_RSP_CHIP_SELECT
+ *
+ *     status code: 2 byte status code
+ *         0x0000: Success
+ *         others: Error
+ *
  * USB Error Codes:
  *
  * send_command return codes have the following format:
@@ -280,6 +304,12 @@ enum packet_id_type {
 	USB_SPI_PKT_ID_RSP_TRANSFER_START     = 5,
 	/* Additional packets containing read payload. */
 	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE  = 6,
+	/*
+	 * Request assertion or deassertion of chip select
+	 */
+	USB_SPI_PKT_ID_CMD_CHIP_SELECT        = 7,
+	/* Response to above request. */
+	USB_SPI_PKT_ID_RSP_CHIP_SELECT        = 8,
 };
 
 enum feature_bitmap {
@@ -314,6 +344,21 @@ struct usb_spi_continue_v2 {
 	uint8_t data[USB_SPI_PAYLOAD_SIZE_V2_CONTINUE];
 } __packed;
 
+enum chip_select_flags {
+	/* Indicates chip select should be asserted. */
+	USB_SPI_CHIP_SELECT = BIT(0)
+};
+
+struct usb_spi_chip_select_command {
+	uint16_t packet_id;
+	uint16_t flags;
+} __packed;
+
+struct usb_spi_chip_select_response {
+	uint16_t packet_id;
+	uint16_t status_code;
+} __packed;
+
 struct usb_spi_packet_ctx {
 	union {
 		uint8_t bytes[USB_MAX_PACKET_SIZE];
@@ -323,6 +368,8 @@ struct usb_spi_packet_ctx {
 		struct usb_spi_response_configuration_v2 rsp_config;
 		struct usb_spi_response_v2 rsp_start;
 		struct usb_spi_continue_v2 rsp_continue;
+		struct usb_spi_chip_select_command cmd_cs;
+		struct usb_spi_chip_select_response rsp_cs;
 	} __packed;
 	/*
 	 * By storing the number of bytes in the header and knowing that the
@@ -392,6 +439,8 @@ enum usb_spi_mode {
 	USB_SPI_MODE_IDLE = 0,
 	/* Indicates the device needs to send it's USB SPI configuration.*/
 	USB_SPI_MODE_SEND_CONFIGURATION,
+	/* Indicates the device needs to respond to chip select. */
+	USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE,
 	/* Indicates we device needs start the SPI transfer. */
 	USB_SPI_MODE_START_SPI,
 	/* Indicates we should start a transfer response. */