ish: commit persistent data during d3 entry

Refactor D3 entry to use ish_pm_reset, as it performs the same
operations modulo the pm_state, save persistent data when entering D3.

BUG=b:134089952
BRANCH=none
TEST=rmmod ish modules, insmod again on arcada

Change-Id: Ifed49d49d42b55cd220ff5d8e8d98843d28dfa22
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674470
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>

5 files changed, 14 insertions, 32 deletions

diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h
index c8664165ea..e804bd72e8 100644
--- a/chip/ish/aontaskfw/ish_aon_share.h
+++ b/chip/ish/aontaskfw/ish_aon_share.h
@@ -8,6 +8,7 @@
 
 #include "common.h"
 #include "ia_structs.h"
+#include "power_mgt.h"
 
 /* magic ID for valid aontask image sanity check */
 #define AON_MAGIC_ID			        0x544E4F41  /*"AONT"*/
@@ -33,7 +34,7 @@ struct ish_aon_share {
 	/* aontask's LDT's limit size */
 	uint32_t aon_ldt_size;
 	/* current power state, see chip/ish/power_mgt.h */
-	int pm_state;
+	enum ish_pm_state pm_state;
 	/* for store/restore main FW's IDT */
 	struct idt_header main_fw_idt_hdr;
 
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index bc8b2f6084..2f548a3aa2 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -76,7 +76,7 @@
 #define AON_IDT_ENTRY_VEC_LAST         ISH_PMU_WAKEUP_VEC
 #endif
 
-static void handle_reset(int pm_state);
+static void handle_reset(enum ish_pm_state pm_state);
 
 /* ISR for PMU wakeup interrupt */
 static void pmu_wakeup_isr(void)
@@ -540,7 +540,7 @@ static void handle_d3(void)
 	handle_reset(ISH_PM_STATE_RESET);
 }
 
-static void handle_reset(int pm_state)
+static void handle_reset(enum ish_pm_state pm_state)
 {
 	/* disable watch dog */
 	WDT_CONTROL &= ~WDT_CONTROL_ENABLE_BIT;
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
index cd5d17034e..470dfd2573 100644
--- a/chip/ish/power_mgt.c
+++ b/chip/ish/power_mgt.c
@@ -8,6 +8,7 @@
 #include "hwtimer.h"
 #include "interrupts.h"
 #include "ish_dma.h"
+#include "ish_persistent_data.h"
 #include "power_mgt.h"
 #include "system.h"
 #include "task.h"
@@ -236,7 +237,7 @@ static void switch_to_aontask(void)
 }
 
 __attribute__ ((noreturn))
-static void handle_reset_in_aontask(int pm_state)
+static void handle_reset_in_aontask(enum ish_pm_state pm_state)
 {
 	pm_ctx.aon_share->pm_state = pm_state;
 
@@ -556,11 +557,11 @@ void ish_pm_init(void)
 }
 
 __attribute__ ((noreturn))
-void ish_pm_reset(void)
+void ish_pm_reset(enum ish_pm_state pm_state)
 {
 	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) &&
 	    pm_ctx.aon_valid) {
-		handle_reset_in_aontask(ISH_PM_STATE_RESET_PREP);
+		handle_reset_in_aontask(pm_state);
 	} else {
 		ish_mia_reset();
 	}
@@ -687,11 +688,7 @@ static void handle_d3(uint32_t irq_vec)
 	PMU_D3_STATUS = PMU_D3_STATUS;
 
 	if (PMU_D3_STATUS & (PMU_D3_BIT_RISING_EDGE_STATUS | PMU_D3_BIT_SET)) {
-
-		if (!pm_ctx.aon_valid)
-			ish_mia_reset();
-
-		/**
+		/*
 		 * Indicate completion of servicing the interrupt to IOAPIC
 		 * first then indicate completion of servicing the interrupt
 		 * to LAPIC
@@ -699,24 +696,8 @@ static void handle_d3(uint32_t irq_vec)
 		IOAPIC_EOI_REG = irq_vec;
 		LAPIC_EOI_REG = 0x0;
 
-		pm_ctx.aon_share->pm_state = ISH_PM_STATE_D3;
-
-		/* only enable PMU wakeup interrupt */
-		disable_all_interrupts();
-		task_enable_irq(ISH_PMU_WAKEUP_IRQ);
-
-		if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP))
-			task_enable_irq(ISH_RESET_PREP_IRQ);
-
-		/* enable Trunk Clock Gating (TCG) of ISH */
-		CCU_TCG_EN = 1;
-
-		/* enable power gating of RF(Cache) and ROMs */
-		PMU_RF_ROM_PWR_CTRL = 1;
-
-		switch_to_aontask();
-
-		__builtin_unreachable();
+		ish_persistent_data_commit();
+		ish_pm_reset(ISH_PM_STATE_D3);
 	}
 }
 
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h
index 06181df077..d66bb96550 100644
--- a/chip/ish/power_mgt.h
+++ b/chip/ish/power_mgt.h
@@ -10,7 +10,7 @@
 #include "registers.h"
 
 /* power states for ISH */
-enum {
+enum ish_pm_state {
 	/* D0 state: active mode */
 	ISH_PM_STATE_D0 = 0,
 	/* sleep state: cpu halt */
@@ -72,7 +72,7 @@ __maybe_unused static void ish_pm_init(void)
 /**
  * reset ISH (reset minute-ia cpu core, and power off main SRAM)
  */
-void ish_pm_reset(void) __attribute__((noreturn));
+void ish_pm_reset(enum ish_pm_state pm_state) __attribute__((noreturn));
 
 /**
  * notify the power management module that the UART for the console is in use.
diff --git a/chip/ish/system.c b/chip/ish/system.c
index f634981817..c18261e0da 100644
--- a/chip/ish/system.c
+++ b/chip/ish/system.c
@@ -99,7 +99,7 @@ void system_reset(int flags)
 	chip_save_reset_flags(save_flags);
 
 	ish_persistent_data_commit();
-	ish_pm_reset();
+	ish_pm_reset(ISH_PM_STATE_RESET);
 	__builtin_unreachable();
 }