diff options
author | Jett Rink <jettrink@chromium.org> | 2018-06-08 16:10:31 -0600 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-11 17:29:48 -0700 |
commit | 7d36fb8991e7a249ae56db508078480c27914f2e (patch) | |
tree | bac641d2be2a906670a1a882040c0cece711e948 /chip | |
parent | 7c6f336362770c85a5df02064fd274eee1ff8555 (diff) | |
download | chrome-ec-7d36fb8991e7a249ae56db508078480c27914f2e.tar.gz |
gpio: extend flags size to accommodate GPIO_ flags
Widen the flags field from 16-bit to 32-bit to fit all of the
current GPIO_flags. Also reorder fields within struct to allow arm
compiler to use 16-bit instructions instead of 32-bit instructions when
accessing fields (which is important for kevin board, otherwise
it runs out of space)
Lastly, re-tool macros to all reordering of gpio_alt_func struct fields.
BRANCH=none
BUG=b:109884927
TEST=builds on all boards
Change-Id: I20b136c94a607c19031a88bddd255cc34cc57bbd
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096018
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/config_chip.h | 2 | ||||
-rw-r--r-- | chip/host/config_chip.h | 2 | ||||
-rw-r--r-- | chip/ish/config_chip.h | 2 | ||||
-rw-r--r-- | chip/it83xx/config_chip.h | 2 | ||||
-rw-r--r-- | chip/lm4/config_chip.h | 2 | ||||
-rw-r--r-- | chip/mchp/config_chip.h | 3 | ||||
-rw-r--r-- | chip/mec1322/config_chip.h | 2 | ||||
-rw-r--r-- | chip/npcx/config_chip.h | 2 | ||||
-rw-r--r-- | chip/nrf51/config_chip.h | 2 | ||||
-rw-r--r-- | chip/stm32/config_chip.h | 2 |
10 files changed, 10 insertions, 11 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 0e6e319007..a79ecf2ee0 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -56,7 +56,7 @@ /* Magic for gpio.inc */ #define GPIO_PIN(port, index) (port), (1 << (index)) -#define GPIO_PIN_MASK(port, mask) (port), (mask) +#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) #define DUMMY_GPIO_BANK 0 #define PCLK_FREQ (24 * 1000 * 1000) diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index dceb685ed5..8cb8bba79c 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -45,7 +45,7 @@ extern char __host_flash[CONFIG_FLASH_SIZE]; #undef CONFIG_COMMON_TIMER #define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #define I2C_PORT_COUNT 1 diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 422e49936f..224f63b627 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -74,6 +74,6 @@ /* GPIO - to be implemented */ #define GPIO_PIN(index) (index) -#define GPIO_PIN_MASK(pin, mask) ((pin), (mask)) +#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index c56a974ba1..5e7a501a8f 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -109,6 +109,6 @@ #define CONFIG_CHIP_PRE_INIT #define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 9d3c53ded2..4db95cc42d 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -102,6 +102,6 @@ #define CONFIG_CHIP_PRE_INIT #define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h index 4272f47d9b..183440a8c4 100644 --- a/chip/mchp/config_chip.h +++ b/chip/mchp/config_chip.h @@ -183,8 +183,7 @@ #define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F)) #define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index) - -#define GPIO_PIN_MASK(bank, mask) (bank), (mask) +#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) #ifndef __ASSEMBLER__ diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index 206e444038..609891a688 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -108,6 +108,6 @@ #define CONFIG_SWITCH #define GPIO_PIN(index) (index / 10), (1 << (index % 10)) -#define GPIO_PIN_MASK(pin, mask) (pin), (mask) +#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 1311edca4f..9dac257850 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -71,6 +71,6 @@ #define CONFIG_CHIP_PRE_INIT #define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h index f14f292f77..374101d1bb 100644 --- a/chip/nrf51/config_chip.h +++ b/chip/nrf51/config_chip.h @@ -58,7 +58,7 @@ #define CONFIG_UART_TX_BUF_SIZE 1024 #define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 4a2f686e6b..5fc0f47681 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -138,7 +138,7 @@ #define GPIO_NAME_BY_PIN(port, index) #port#index #define GPIO_PIN(port, index) GPIO_##port, (1 << index) -#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) +#define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) /* Prescaler values for PLL. Currently used only by STM32L476. */ #define STM32_PLLM 0 |