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| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2021-08-16 11:12:31 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-12-23 10:14:57 +0000 |
| commit | d68d233fb3ec937678e77f27c5eca28ffb0f0d42 (patch) | |
| tree | 62a4af7ebabe4e193881ceb9d679dcbe7d35316d /chip | |
| parent | 2bf1d6820345956e3fcf1cc57f996e48267a404f (diff) | |
| download | chrome-ec-d68d233fb3ec937678e77f27c5eca28ffb0f0d42.tar.gz | |
chip/mt_scp: fix mt8195 irq table entries 70~75 and 93~95
Update entry name to match mt8195 SCP irq table.
BRANCH=none
BUG=b:189356151
TEST=make BOARD=cherry_scp pass
Change-Id: I30118aef1898954edfa25db3403f5bca7d282c8c
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120618
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/mt_scp/mt8195/intc.h | 12 | ||||
| -rw-r--r-- | chip/mt_scp/rv32i_common/intc.c | 18 |
2 files changed, 15 insertions, 15 deletions
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h index 87181c46ca..ba77f069f2 100644 --- a/chip/mt_scp/mt8195/intc.h +++ b/chip/mt_scp/mt8195/intc.h @@ -102,13 +102,13 @@ /* 68 */ #define SCP_IRQ_APU_MBOX 68 #define SCP_IRQ_DEVAPC_SECURE_VIO 69 -#define SCP_IRQ_CAMSYS_29 70 -#define SCP_IRQ_CAMSYS_28 71 +#define SCP_IRQ_APDMA0 70 +#define SCP_IRQ_APDMA1 71 /* 72 */ -#define SCP_IRQ_CAMSYS_5 72 -#define SCP_IRQ_CAMSYS_4 73 -#define SCP_IRQ_CAMSYS_3 74 -#define SCP_IRQ_CAMSYS_2 75 +#define SCP_IRQ_APDMA2 72 +#define SCP_IRQ_APDMA3 73 +#define SCP_IRQ_APDMA4 74 +#define SCP_IRQ_APDMA5 75 /* 76 */ #define SCP_IRQ_HDMIRX_PM_DVI_SQH 76 #define SCP_IRQ_HDMIRX_RESERVED 77 diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c index 7e6b39e1f2..1e4fd1cef4 100644 --- a/chip/mt_scp/rv32i_common/intc.c +++ b/chip/mt_scp/rv32i_common/intc.c @@ -243,13 +243,13 @@ static struct { /* 68 */ [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_29] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_28] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA0] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA1] = { INTC_GRP_0 }, /* 72 */ - [SCP_IRQ_CAMSYS_5] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_4] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_3] = { INTC_GRP_0 }, - [SCP_IRQ_CAMSYS_2] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA2] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA3] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA4] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA5] = { INTC_GRP_0 }, /* 76 */ [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, @@ -272,9 +272,9 @@ static struct { [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, /* 92 */ [SCP_IRQ_EARC] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, + [SCP_IRQ_CEC] = { INTC_GRP_0 }, + [SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 }, /* 96 */ [SCP_IRQ_I2C2] = { INTC_GRP_0 }, [SCP_IRQ_I2C3] = { INTC_GRP_0 }, |