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| author | Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> | 2022-08-24 13:20:12 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-08-26 10:59:29 +0000 |
| commit | 5d5611dfa23fda1f3f692316f0039b471dc903c0 (patch) | |
| tree | 91317d46644e127dd171d68af9d19ae25d0e35ce /chip | |
| parent | 573bcf3ac69bc9e8a4bb79f3cf0bd4a6ea49026d (diff) | |
| download | chrome-ec-5d5611dfa23fda1f3f692316f0039b471dc903c0.tar.gz | |
mtk_scp: Enable I/D-cache for mt8186
1. Enable cache mapping on scp boot.
2. Add interrupt disable/enable to prevent preempt when setting cache
range.
BRANCH=none
BUG=b:218771968
TEST=Boot kukui scp and open cam ok
make BOARD=corsola_scp -j ALLOW_CONFIG=1
Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I8d586afc33cba55d388d553dd2a2fc2047089553
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3853765
Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Wei-Shun Chang <weishunc@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/mt_scp/mt818x/memmap.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/chip/mt_scp/mt818x/memmap.c b/chip/mt_scp/mt818x/memmap.c index e3b6eed192..8df36dae0d 100644 --- a/chip/mt_scp/mt818x/memmap.c +++ b/chip/mt_scp/mt818x/memmap.c @@ -12,6 +12,7 @@ #include "memmap.h" #include "registers.h" #include "util.h" +#include "task.h" /* * Map SCP address (bits 31~28) to AP address @@ -49,8 +50,6 @@ static const uint8_t addr_map[16] = { */ #define CACHE_TRANS_AP_ADDR 0x50000000 #define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000 -/* FIXME: This should be configurable */ -#define CACHE_TRANS_AP_SIZE 0x00400000 #ifdef CONFIG_DRAM_BASE BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR); @@ -78,6 +77,8 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length) size_t pos; uintptr_t addr; + interrupt_disable(); + for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) { addr = base + pos; SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; @@ -86,7 +87,9 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length) /* Read necessary to confirm the invalidation finish. */ REG32(addr); } + asm volatile("dsb;"); + interrupt_enable(); } void cpu_clean_invalidate_dcache(void) @@ -106,6 +109,7 @@ void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length) size_t pos; uintptr_t addr; + interrupt_disable(); for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) { addr = base + pos; SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK; @@ -117,7 +121,9 @@ void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length) /* Read necessary to confirm the invalidation finish. */ REG32(addr); } + asm volatile("dsb;"); + interrupt_enable(); } static void scp_cache_init(void) |